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authorTristan Gingold <tgingold@free.fr>2019-07-04 18:22:21 +0200
committerTristan Gingold <tgingold@free.fr>2019-07-04 18:22:21 +0200
commit457ab6ebd8b17685c79047ad6d50e1b26665c5c3 (patch)
tree894cd30ab8ecdf774bd181021bf17151f62e2af2 /src/synth/synth-expr.adb
parent9b70a1f0bf970706a62dc14e382c91f3616ab51c (diff)
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synth: handle some "/=".
Diffstat (limited to 'src/synth/synth-expr.adb')
-rw-r--r--src/synth/synth-expr.adb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index 23d97a129..ecdb99cb0 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -751,6 +751,9 @@ package body Synth.Expr is
| Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Slv =>
-- "=" (Unsigned, Unsigned) [resize]
return Synth_Compare_Uns_Uns (Id_Eq);
+ when Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Nat =>
+ -- "/=" (Unsigned, Natural)
+ return Synth_Compare_Uns_Nat (Id_Ne);
when Iir_Predefined_Ieee_Numeric_Std_Lt_Uns_Nat =>
-- "<" (Unsigned, Natural)
if Is_Const (Right) and then Right.Scal = 0 then