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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-28 19:08:32 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-28 19:08:32 +0200 |
| commit | ec43db0fb7543b62ab9d326e978cceb70defe58e (patch) | |
| tree | 22eed14e17fedfbd140525f2aab2fa6660297217 /src/synth/synth-expr.adb | |
| parent | 40c7b033a8e005503a5719901ac420bd39145a7b (diff) | |
| download | ghdl-ec43db0fb7543b62ab9d326e978cceb70defe58e.tar.gz ghdl-ec43db0fb7543b62ab9d326e978cceb70defe58e.tar.bz2 ghdl-ec43db0fb7543b62ab9d326e978cceb70defe58e.zip | |
synth: disp_vhdl: merge literals.
Diffstat (limited to 'src/synth/synth-expr.adb')
| -rw-r--r-- | src/synth/synth-expr.adb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index cb2dc64b6..3f6e2efc5 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -158,6 +158,13 @@ package body Synth.Expr is function Synth_Uresize (Val : Value_Acc; Vtype : Node; W : Width) return Net is begin + if Is_Const (Val) + and then (Get_Kind (Get_Base_Type (Vtype)) + = Iir_Kind_Integer_Type_Definition) + then + return Build_Const_UB32 + (Build_Context, Uns32 (Val.Scal), W); + end if; return Synth_Uresize (Get_Net (Val, Vtype), W); end Synth_Uresize; |