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synth
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netlists-disp_verilog.adb
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Author
Age
Files
Lines
*
netlists-disp_verilog(disp_const_log): fix output. Fix #2149
Tristan Gingold
2022-07-28
1
-2
/
+2
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*
synth: Display dlatch
Tristan Gingold
2022-07-14
1
-0
/
+4
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*
netlists-disp_verilog: do not connect to null-range output. For #2113
Tristan Gingold
2022-07-08
1
-41
/
+47
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*
netlists-disp_verilog: fix output for id_abs. For #2123
Tristan Gingold
2022-07-06
1
-1
/
+2
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*
netlists-disp_verilog: handle Id_Abs. Fix #2113
Tristan Gingold
2022-07-04
1
-1
/
+1
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*
netlists-disp_verilog: adjust, discard null signals. For #2113
Tristan Gingold
2022-06-28
1
-1
/
+6
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*
netlists-disp_verilog: fix warning
Tristan Gingold
2022-06-27
1
-1
/
+2
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*
synth/netlists-disp_verilog: skip null input port. Fix #2113
Tristan Gingold
2022-06-27
1
-15
/
+20
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*
synth: rework #2109 - remove null wires
Tristan Gingold
2022-06-27
1
-3
/
+0
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*
synth/netlists-disp_verilog: adjust previous patch. For #2109
Tristan Gingold
2022-06-27
1
-1
/
+2
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*
netlists-disp_verilog: do not display ports of width 0. Fix #2109
Tristan Gingold
2022-06-27
1
-5
/
+19
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*
netlists-disp_verilog: do not display blackboxes. Fix #2092
Tristan Gingold
2022-06-13
1
-0
/
+5
|
*
netlists-disp_verilog: Use blocking assignments in non-clocked blocks
Anton Blanchard
2022-06-13
1
-10
/
+10
|
*
netlists-disp_verilog: output default value for pmux. Fix #2041
Tristan Gingold
2022-04-21
1
-0
/
+1
|
*
netlists-disp_verilog: fix disp_const_bit
Tristan Gingold
2022-03-12
1
-2
/
+2
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*
synth: put direction into port desc
Tristan Gingold
2021-11-17
1
-8
/
+4
|
*
synth: renaming to instance_attributes.
Tristan Gingold
2021-11-17
1
-2
/
+2
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*
synth/netlists-disp_verilog: display port attributes
Tristan Gingold
2021-11-17
1
-18
/
+42
|
*
netlists-disp_verilog: fix name for memory initialization
Tristan Gingold
2021-09-28
1
-3
/
+4
|
*
netlists-disp_verilog: fix output of parameter assignments. Fix #1866
Tristan Gingold
2021-09-15
1
-12
/
+12
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*
netlists-disp_verilog.adb: add 'parameter' before parameters declaration
Tristan Gingold
2021-09-15
1
-1
/
+1
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For #1866
*
synth/netlists-disp_verilog: fix output of parameter values. For #1866
Tristan Gingold
2021-09-15
1
-1
/
+13
|
*
netlists-disp_verilog: handle initial value for idff and isignal
Tristan Gingold
2021-08-28
1
-8
/
+18
|
*
netlists-disp_verilog: fix handling of unconnected port
Tristan Gingold
2021-08-26
1
-3
/
+1
|
*
synth: reuse signal name while creating memories. Fix #1838
Tristan Gingold
2021-08-25
1
-4
/
+4
|
*
netlists-disp_verilog: fix display of constants
Tristan Gingold
2021-05-07
1
-10
/
+20
|
*
netlists-disp_verilog.adb: handle memidx, dyn_insert, dyn_extract.
Tristan Gingold
2021-05-04
1
-74
/
+14
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*
synth: add verilog output
Tristan Gingold
2021-04-28
1
-0
/
+1396