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| author | Tristan Gingold <tgingold@free.fr> | 2022-04-21 07:23:07 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-04-21 07:23:07 +0200 |
| commit | 3c6df8a24f8ebfe5e1e95d1b718a9ca97f17d5d7 (patch) | |
| tree | ac7d7837ca02476f9579933389e9ac19f6f3bb64 /src/synth/netlists-disp_verilog.adb | |
| parent | e85b7d29d04801b99ae15415d26553319f8f9875 (diff) | |
| download | ghdl-3c6df8a24f8ebfe5e1e95d1b718a9ca97f17d5d7.tar.gz ghdl-3c6df8a24f8ebfe5e1e95d1b718a9ca97f17d5d7.tar.bz2 ghdl-3c6df8a24f8ebfe5e1e95d1b718a9ca97f17d5d7.zip | |
netlists-disp_verilog: output default value for pmux. Fix #2041
Diffstat (limited to 'src/synth/netlists-disp_verilog.adb')
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 23b9d99e5..18c5091df 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -764,6 +764,7 @@ package body Netlists.Disp_Verilog is (Get_Input_Net (Inst, Port_Idx (2 + W - I)), Inst, Conv_None); Put_Line (";"); end loop; + Disp_Template (" default: \o0 <= \i1;" & NL, Inst); Disp_Template (" endcase" & NL, Inst); end Disp_Pmux; |