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author | Tristan Gingold <tgingold@free.fr> | 2021-11-17 21:43:10 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-11-17 21:43:10 +0100 |
commit | 29b56efcbdaea0002b4f71e229ee44c1ebe75a08 (patch) | |
tree | 5d9792f5a8a3532f695a83f20b3e4cf54fc71b5e /src/synth/netlists-disp_verilog.adb | |
parent | d6f1c6a47fb8df07fca517fb68078c324c761a97 (diff) | |
download | ghdl-29b56efcbdaea0002b4f71e229ee44c1ebe75a08.tar.gz ghdl-29b56efcbdaea0002b4f71e229ee44c1ebe75a08.tar.bz2 ghdl-29b56efcbdaea0002b4f71e229ee44c1ebe75a08.zip |
synth: put direction into port desc
Diffstat (limited to 'src/synth/netlists-disp_verilog.adb')
-rw-r--r-- | src/synth/netlists-disp_verilog.adb | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index b6ceece5a..6bdb9186e 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -1240,7 +1240,6 @@ package body Netlists.Disp_Verilog is end Disp_Module_Statements; procedure Disp_Module_Port (Desc : Port_Desc; - Dir : Port_Kind; Attrs : Attribute; First : in out Boolean) is @@ -1268,7 +1267,7 @@ package body Netlists.Disp_Verilog is Put (" *) "); end if; - case Dir is + case Desc.Dir is when Port_In => Put ("input "); when Port_Out => @@ -1288,17 +1287,14 @@ package body Netlists.Disp_Verilog is begin First := True; for I in 1 .. Get_Nbr_Inputs (M) loop + Desc := Get_Input_Desc (M, I - 1); Attr := Get_Input_Port_First_Attribute (M, I - 1); - Disp_Module_Port (Get_Input_Desc (M, I - 1), Port_In, Attr, First); + Disp_Module_Port (Desc, Attr, First); end loop; for I in 1 .. Get_Nbr_Outputs (M) loop Desc := Get_Output_Desc (M, I - 1); Attr := Get_Output_Port_First_Attribute (M, I - 1); - if Desc.Is_Inout then - Disp_Module_Port (Desc, Port_Inout, Attr, First); - else - Disp_Module_Port (Desc, Port_Out, Attr, First); - end if; + Disp_Module_Port (Desc, Attr, First); end loop; if not First then Put (")"); |