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| author | Anton Blanchard <anton@ozlabs.org> | 2022-06-13 16:19:06 +1000 |
|---|---|---|
| committer | Anton Blanchard <anton@ozlabs.org> | 2022-06-13 16:38:19 +1000 |
| commit | b9a6f4965ec7d34bba07897970cb3fafaa9ff287 (patch) | |
| tree | 0c504756ac5652163430ecbb6f312dd292ea3f54 /src/synth/netlists-disp_verilog.adb | |
| parent | 74475ced39581983e8cefa5ac66e999d8c4efd9d (diff) | |
| download | ghdl-b9a6f4965ec7d34bba07897970cb3fafaa9ff287.tar.gz ghdl-b9a6f4965ec7d34bba07897970cb3fafaa9ff287.tar.bz2 ghdl-b9a6f4965ec7d34bba07897970cb3fafaa9ff287.zip | |
netlists-disp_verilog: Use blocking assignments in non-clocked blocks
Diffstat (limited to 'src/synth/netlists-disp_verilog.adb')
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 18c5091df..baa9db2c0 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -759,12 +759,12 @@ package body Netlists.Disp_Verilog is Put ('0'); end if; end loop; - Disp_Template (": \o0 <= ", Inst); + Disp_Template (": \o0 = ", Inst); Disp_Net_Expr (Get_Input_Net (Inst, Port_Idx (2 + W - I)), Inst, Conv_None); Put_Line (";"); end loop; - Disp_Template (" default: \o0 <= \i1;" & NL, Inst); + Disp_Template (" default: \o0 = \i1;" & NL, Inst); Disp_Template (" endcase" & NL, Inst); end Disp_Pmux; @@ -826,7 +826,7 @@ package body Netlists.Disp_Verilog is " \o0 = \i0; // (isignal)" & NL, Inst); end if; Disp_Template (" initial" & NL & - " \o0 <= \i1;" & NL, Inst); + " \o0 = \i1;" & NL, Inst); end; when Id_Port => Disp_Template (" \o0 <= \i0; -- (port)" & NL, Inst); @@ -889,13 +889,13 @@ package body Netlists.Disp_Verilog is Iw : constant Width := Get_Width (Get_Input_Net (Inst, 1)); begin Put (" always @* begin // (dyn_insert)" & NL); - Disp_Template (" \o0 <= \i0;" & NL, Inst); + Disp_Template (" \o0 = \i0;" & NL, Inst); if Id = Id_Dyn_Insert_En then -- TODO: fix indentation. Disp_Template (" if (\i3)" & NL, Inst); end if; Disp_Template - (" \o0 [\i2 + \p0 -: \n0] <= \i1;" & NL, + (" \o0 [\i2 + \p0 -: \n0] = \i1;" & NL, Inst, (0 => Iw - 1)); Disp_Template (" end" & NL, Inst); end; @@ -921,17 +921,17 @@ package body Netlists.Disp_Verilog is " \o0 <= \i1;" & NL, Inst); if Id = Id_Idff then Disp_Template (" initial" & NL & - " \o0 <= \i2;" & NL, Inst); + " \o0 = \i2;" & NL, Inst); end if; when Id_Mux2 => Disp_Template (" assign \o0 = \i0 ? \i2 : \i1;" & NL, Inst); when Id_Mux4 => Disp_Template (" always @*" & NL & " case (\i0)" & NL & - " 2'b00: \o0 <= \i1;" & NL & - " 2'b01: \o0 <= \i2;" & NL & - " 2'b10: \o0 <= \i3;" & NL & - " 2'b11: \o0 <= \i4;" & NL & + " 2'b00: \o0 = \i1;" & NL & + " 2'b01: \o0 = \i2;" & NL & + " 2'b10: \o0 = \i3;" & NL & + " 2'b11: \o0 = \i4;" & NL & " endcase" & NL, Inst); when Id_Pmux => Disp_Pmux (Inst); |