| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | simul: refactoring, expose more subprograms | Tristan Gingold | 2023-02-04 | 1 | -1/+12 |
| * | ghdlsimul: extract simul-main from simul-vhdl_simul | Tristan Gingold | 2023-01-31 | 1 | -12/+0 |
| * | simul: add debug command 'run -s' | Tristan Gingold | 2023-01-11 | 1 | -0/+1 |
| * | simul: handle suspendable procedure call from sensitized process. | Tristan Gingold | 2022-10-05 | 1 | -0/+4 |
| * | synth: use areapools | Tristan Gingold | 2022-09-02 | 1 | -2/+2 |
| * | simul-vhdl_simul: add support for PSL directives | Tristan Gingold | 2022-08-20 | 1 | -4/+15 |
| * | ghdlsimul: add an option to debug before elaboration | Tristan Gingold | 2022-08-18 | 1 | -0/+1 |
| * | simul: create terminals (WIP) | Tristan Gingold | 2022-08-17 | 1 | -1/+1 |
| * | simul-vhdl_simul: add scalar terminal table | Tristan Gingold | 2022-07-28 | 1 | -0/+16 |
| * | src/simul: rewrite of ghdl/simul based on synth | Tristan Gingold | 2022-07-24 | 1 | -0/+120 |
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index : iCE40/ghdl | |
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