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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-28 12:27:45 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-02 02:31:06 +0200 |
| commit | 8a8f3d867598a1f9e3125c9d0648ae20a7144253 (patch) | |
| tree | 9802e5c0c5e68e92acbc5c41caf3025fbe1efe02 /src/simul/simul-vhdl_simul.ads | |
| parent | 91303467eac522662572d9106e2a3cb724b24a0d (diff) | |
| download | ghdl-8a8f3d867598a1f9e3125c9d0648ae20a7144253.tar.gz ghdl-8a8f3d867598a1f9e3125c9d0648ae20a7144253.tar.bz2 ghdl-8a8f3d867598a1f9e3125c9d0648ae20a7144253.zip | |
synth: use areapools
Diffstat (limited to 'src/simul/simul-vhdl_simul.ads')
| -rw-r--r-- | src/simul/simul-vhdl_simul.ads | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_simul.ads b/src/simul/simul-vhdl_simul.ads index 38d3173f0..f2cf98212 100644 --- a/src/simul/simul-vhdl_simul.ads +++ b/src/simul/simul-vhdl_simul.ads @@ -18,7 +18,7 @@ with Types; use Types; with Tables; -with Areapools; use Areapools; +with Areapools; with Vhdl.Nodes; use Vhdl.Nodes; @@ -60,7 +60,7 @@ package Simul.Vhdl_Simul is case Kind is when Kind_Process => -- Memory pool to allocate objects from. - Pool : Areapool_Acc; + Pool : Areapools.Areapool_Acc; when Kind_PSL => Done : Boolean; States: Boolean_Vector_Acc; |