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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:02:53 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:02:53 +0100 |
| commit | 8b2a821eb457c200db22443ba0b562b94d0d90b5 (patch) | |
| tree | f72dd464fd2c9ee6f991af29a47452b117b2a276 /src/simul/simul-vhdl_simul.ads | |
| parent | 976b7863df71850e8a3e1b791d2c38907db397b3 (diff) | |
| download | ghdl-8b2a821eb457c200db22443ba0b562b94d0d90b5.tar.gz ghdl-8b2a821eb457c200db22443ba0b562b94d0d90b5.tar.bz2 ghdl-8b2a821eb457c200db22443ba0b562b94d0d90b5.zip | |
simul: add debug command 'run -s'
Diffstat (limited to 'src/simul/simul-vhdl_simul.ads')
| -rw-r--r-- | src/simul/simul-vhdl_simul.ads | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_simul.ads b/src/simul/simul-vhdl_simul.ads index 66a032f22..47c1273be 100644 --- a/src/simul/simul-vhdl_simul.ads +++ b/src/simul/simul-vhdl_simul.ads @@ -33,6 +33,7 @@ with Grt.Signals; package Simul.Vhdl_Simul is Break_Time : Std_Time; + Break_Step : Boolean; Trace_Simulation : Boolean := False; |