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simul
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simul-vhdl_simul.adb
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Author
Age
Files
Lines
*
simul: handle PSL endpoints
Tristan Gingold
2023-01-18
1
-7
/
+25
|
*
simul: fix last_value for post vhdl 87
Tristan Gingold
2023-01-18
1
-103
/
+143
|
*
simul: disable --trace-signals
Tristan Gingold
2023-01-15
1
-0
/
+4
|
*
synth: handle protected functions in conversion functions
Tristan Gingold
2023-01-12
1
-1
/
+2
|
*
simul: handle PSL aborts
Tristan Gingold
2023-01-12
1
-0
/
+45
|
*
simul: avoid a crash after an error in a condition
Tristan Gingold
2023-01-11
1
-1
/
+6
|
*
simul: allow function calls in signal association by value
Tristan Gingold
2023-01-11
1
-0
/
+2
|
*
simul: add sensitivity for psl processes
Tristan Gingold
2023-01-11
1
-4
/
+7
|
*
simul: improve assertion messages for psl
Tristan Gingold
2023-01-11
1
-5
/
+15
|
*
simul: add debug command 'run -s'
Tristan Gingold
2023-01-11
1
-2
/
+5
|
*
simul: handle array element resolution
Tristan Gingold
2023-01-11
1
-1
/
+6
|
*
simul: enable all debug features during elaboration
Tristan Gingold
2023-01-10
1
-1
/
+3
|
*
synth: handle indexes in arrays conversion
Tristan Gingold
2023-01-10
1
-2
/
+2
|
*
simul: handle inertial assignments
Tristan Gingold
2023-01-10
1
-2
/
+14
|
*
simul: set assertion hook before elaboration
Tristan Gingold
2023-01-09
1
-3
/
+3
|
*
simul-vhdl_simul: fix effective value writes
Tristan Gingold
2023-01-09
1
-1
/
+20
|
*
simul: handle PSL cover
Tristan Gingold
2023-01-09
1
-1
/
+2
|
*
simul: handle force/release signal assignments
Tristan Gingold
2023-01-03
1
-0
/
+174
|
*
synth: introduce type_array_unbounded
Tristan Gingold
2023-01-03
1
-0
/
+2
|
*
simul: handle driving and driving_value attributes
Tristan Gingold
2022-12-26
1
-6
/
+39
|
*
simul: handle transaction attribute
Tristan Gingold
2022-12-26
1
-3
/
+4
|
*
simul: handle aggregate is guarded signal assignment target
Tristan Gingold
2022-12-26
1
-7
/
+29
|
*
vhdl-canon: handle unaffected
Tristan Gingold
2022-12-26
1
-0
/
+5
|
*
synth: add value_sig_val to handle individual signal associations
Tristan Gingold
2022-12-26
1
-28
/
+166
|
*
vhdl: fix some compiler warnings
Tristan Gingold
2022-11-08
1
-2
/
+0
|
*
simul: handle delayed attribute
Tristan Gingold
2022-10-14
1
-6
/
+55
|
*
simul: handle last_event and last_active
Tristan Gingold
2022-10-13
1
-4
/
+98
|
*
simul-vhdl_simul: keep default value of collapsed signals
Tristan Gingold
2022-10-13
1
-1
/
+10
|
*
simul: fix a crash due to missing stride
Tristan Gingold
2022-10-13
1
-5
/
+7
|
*
simul: handle guarded concurrent assignments
Tristan Gingold
2022-10-10
1
-14
/
+32
|
*
simul: complete concurrent procedure calls
Tristan Gingold
2022-10-06
1
-27
/
+38
|
*
simul: fix initial value of record signals
Tristan Gingold
2022-10-06
1
-2
/
+2
|
*
simul: handle suspendable procedure call from sensitized process.
Tristan Gingold
2022-10-05
1
-3
/
+7
|
*
simul: finalize empty procedures
Tristan Gingold
2022-10-01
1
-9
/
+11
|
*
simul: minor rewrite
Tristan Gingold
2022-10-01
1
-3
/
+2
|
*
simul: finalize declarations of procedure calls
Tristan Gingold
2022-10-01
1
-0
/
+4
|
*
simul: handle stable attribute
Tristan Gingold
2022-09-30
1
-5
/
+33
|
*
synth: factorize code
Tristan Gingold
2022-09-30
1
-0
/
+8
|
*
simul: create disconnections
Tristan Gingold
2022-09-30
1
-1
/
+42
|
*
simul: handle quiet attribute
Tristan Gingold
2022-09-29
1
-7
/
+43
|
*
simul: factorize code, add sub_signal_type
Tristan Gingold
2022-09-29
1
-11
/
+11
|
*
simul: support guarded signal assignments (WIP)
Tristan Gingold
2022-09-29
1
-8
/
+79
|
*
simul: handle last_value attribute
Tristan Gingold
2022-09-28
1
-1
/
+23
|
*
simul: fix handling of labels in next/exit statements
Tristan Gingold
2022-09-28
1
-4
/
+13
|
*
synth: handle null-range loops
Tristan Gingold
2022-09-28
1
-4
/
+3
|
*
simul: handle null signal assignments
Tristan Gingold
2022-09-27
1
-12
/
+36
|
*
synth: handle attributes in configurations
Tristan Gingold
2022-09-26
1
-1
/
+1
|
*
synth: rework error procedure, always pass the instance
Tristan Gingold
2022-09-25
1
-1
/
+1
|
*
simul: gather disconnection specifications, create guard signal
Tristan Gingold
2022-09-25
1
-4
/
+94
|
*
simul: handle empty procedures
Tristan Gingold
2022-09-25
1
-1
/
+9
|
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