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src
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simul
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simul-vhdl_debug.adb
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Author
Age
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*
ghdlsimul: extract simul-main from simul-vhdl_simul
Tristan Gingold
2023-01-31
1
-2
/
+3
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*
simul: improve info sig and info time
Tristan Gingold
2023-01-30
1
-52
/
+78
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*
simul: fix last_value for post vhdl 87
Tristan Gingold
2023-01-18
1
-0
/
+2
|
*
simul: add debug command 'run -s'
Tristan Gingold
2023-01-11
1
-6
/
+12
|
*
simul: improve debugger output
Tristan Gingold
2023-01-11
1
-5
/
+5
|
*
synth: introduce type_array_unbounded
Tristan Gingold
2023-01-03
1
-0
/
+1
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*
simul-vhdl_debug: handle state before elaboration
Tristan Gingold
2022-10-10
1
-0
/
+8
|
*
simul: improve debugger (display of signals value)
Tristan Gingold
2022-10-06
1
-27
/
+26
|
*
simul: factorize code, add sub_signal_type
Tristan Gingold
2022-09-29
1
-5
/
+5
|
*
synth: handle guard signal in debugger
Tristan Gingold
2022-09-28
1
-56
/
+65
|
*
simul: factorize code to compute number of sources
Tristan Gingold
2022-08-23
1
-1
/
+3
|
*
simul-vhdl_debug: disp nbr sources
Tristan Gingold
2022-08-23
1
-1
/
+15
|
*
simul-vhdl_debug: display connections
Tristan Gingold
2022-08-19
1
-5
/
+63
|
*
simul: add create_connects
Tristan Gingold
2022-08-17
1
-2
/
+2
|
*
simul-vhdl_debug: add info terminal
Tristan Gingold
2022-07-28
1
-20
/
+69
|
*
src/simul: rewrite of ghdl/simul based on synth
Tristan Gingold
2022-07-24
1
-0
/
+728