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author | Tristan Gingold <tgingold@free.fr> | 2023-01-11 04:53:45 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-01-11 04:53:45 +0100 |
commit | 9c74053b14345ba80bc8b785e50c016918e68789 (patch) | |
tree | 1efb163b0c33c09f49e3c1ed6f8daa5f74dc8335 /src/simul/simul-vhdl_debug.adb | |
parent | c652e4aa93c3657fad06d8457847ff317b5db583 (diff) | |
download | ghdl-9c74053b14345ba80bc8b785e50c016918e68789.tar.gz ghdl-9c74053b14345ba80bc8b785e50c016918e68789.tar.bz2 ghdl-9c74053b14345ba80bc8b785e50c016918e68789.zip |
simul: improve debugger output
Diffstat (limited to 'src/simul/simul-vhdl_debug.adb')
-rw-r--r-- | src/simul/simul-vhdl_debug.adb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb index fe49e2292..11bd17f43 100644 --- a/src/simul/simul-vhdl_debug.adb +++ b/src/simul/simul-vhdl_debug.adb @@ -343,7 +343,7 @@ package body Simul.Vhdl_Debug is return; end if; Put_Addr (Sig.all'Address); - Put (' '); + Put (':'); Ev := Sig.Event_List; while Ev /= null loop Ctxt := Get_Rti_Context (Ev.Proc); @@ -546,7 +546,7 @@ package body Simul.Vhdl_Debug is end if; if Opts.Actions and then S.Sig /= null then - Put_Line ("actions:"); + Put_Line ("actions (for each scalar):"); Info_Signal_Action ((S.Typ, S.Sig), Get_Type (S.Decl)); end if; end Info_Signal_Opts; @@ -791,14 +791,14 @@ package body Simul.Vhdl_Debug is begin Fn := Skip_Blanks (Line, Line'First); if Fn > Line'Last then - Put ("missing trace name"); + Put_Line ("missing trace name"); return; end if; Ln := Get_Word (Line, Fn); Fv := Skip_Blanks (Line, Ln + 1); if Fv > Line'Last then - Put ("missing on/off/0/1"); + Put_Line ("missing on/off/0/1"); return; end if; Lv := Get_Word (Line, Fv); @@ -807,7 +807,7 @@ package body Simul.Vhdl_Debug is elsif Line (Fv .. Lv) = "off" or Line (Fv .. Lv) = "0" then State := False; else - Put ("expect on/off/0/1"); + Put_Line ("expect on/off/0/1"); return; end if; |