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path: root/src/simul/simul-vhdl_debug.adb
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* ghdlsimul: extract simul-main from simul-vhdl_simulTristan Gingold2023-01-311-2/+3
* simul: improve info sig and info timeTristan Gingold2023-01-301-52/+78
* simul: fix last_value for post vhdl 87Tristan Gingold2023-01-181-0/+2
* simul: add debug command 'run -s'Tristan Gingold2023-01-111-6/+12
* simul: improve debugger outputTristan Gingold2023-01-111-5/+5
* synth: introduce type_array_unboundedTristan Gingold2023-01-031-0/+1
* simul-vhdl_debug: handle state before elaborationTristan Gingold2022-10-101-0/+8
* simul: improve debugger (display of signals value)Tristan Gingold2022-10-061-27/+26
* simul: factorize code, add sub_signal_typeTristan Gingold2022-09-291-5/+5
* synth: handle guard signal in debuggerTristan Gingold2022-09-281-56/+65
* simul: factorize code to compute number of sourcesTristan Gingold2022-08-231-1/+3
* simul-vhdl_debug: disp nbr sourcesTristan Gingold2022-08-231-1/+15
* simul-vhdl_debug: display connectionsTristan Gingold2022-08-191-5/+63
* simul: add create_connectsTristan Gingold2022-08-171-2/+2
* simul-vhdl_debug: add info terminalTristan Gingold2022-07-281-20/+69
* src/simul: rewrite of ghdl/simul based on synthTristan Gingold2022-07-241-0/+728
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