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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-17 03:19:30 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-17 03:19:30 +0200 |
| commit | a546ecfe5c8643c72435318de3973cbf83993fa4 (patch) | |
| tree | 76c82ce2422c8e110efa496a8d13dc9f591a447d /src/simul/simul-vhdl_debug.adb | |
| parent | e57ba3e335d1f3692805f46d7d9cba49ffea4219 (diff) | |
| download | ghdl-a546ecfe5c8643c72435318de3973cbf83993fa4.tar.gz ghdl-a546ecfe5c8643c72435318de3973cbf83993fa4.tar.bz2 ghdl-a546ecfe5c8643c72435318de3973cbf83993fa4.zip | |
simul: add create_connects
Diffstat (limited to 'src/simul/simul-vhdl_debug.adb')
| -rw-r--r-- | src/simul/simul-vhdl_debug.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb index 067e06186..0c8a707f1 100644 --- a/src/simul/simul-vhdl_debug.adb +++ b/src/simul/simul-vhdl_debug.adb @@ -376,13 +376,13 @@ package body Simul.Vhdl_Debug is declare C : Connect_Entry renames Connect_Table.Table (Conn); begin - if C.Formal_Base = Idx then + if C.Formal.Base = Idx then if C.Drive_Formal then Nbr_Conn_Drv := Nbr_Conn_Drv + 1; end if; Conn := C.Formal_Link; else - pragma Assert (C.Actual_Base = Idx); + pragma Assert (C.Actual.Base = Idx); if C.Drive_Actual then Nbr_Conn_Drv := Nbr_Conn_Drv + 1; end if; |