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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-18 18:19:18 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-18 18:19:18 +0100 |
| commit | de7fe2bf3f78a2753809b4533fcc8575892fa000 (patch) | |
| tree | 4670816b7e8c9fa789821679777a4eda77b01e6a /src/simul/simul-vhdl_debug.adb | |
| parent | 1b0c3819af5eb1f481db51e4dbdfd7e00757ddaf (diff) | |
| download | ghdl-de7fe2bf3f78a2753809b4533fcc8575892fa000.tar.gz ghdl-de7fe2bf3f78a2753809b4533fcc8575892fa000.tar.bz2 ghdl-de7fe2bf3f78a2753809b4533fcc8575892fa000.zip | |
simul: fix last_value for post vhdl 87
Diffstat (limited to 'src/simul/simul-vhdl_debug.adb')
| -rw-r--r-- | src/simul/simul-vhdl_debug.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb index 33ffdb798..d4dde12f7 100644 --- a/src/simul/simul-vhdl_debug.adb +++ b/src/simul/simul-vhdl_debug.adb @@ -227,6 +227,8 @@ package body Simul.Vhdl_Debug is Disp_Value (Sig.Value_Ptr, Sig.Mode, Stype); Put ("; drv="); Disp_Value (Sig.Driving_Value, Sig.Mode, Stype); + Put ("; last_val="); + Disp_Value (Sig.Last_Value, Sig.Mode, Stype); if Sig.Nbr_Ports > 0 then Put (';'); Put_Int32 (Int32 (Sig.Nbr_Ports)); |