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* synth: subtype conversion before compare.Tristan Gingold2019-09-031-2/+7
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* testsuite: add reproducer for issue #912Tristan Gingold2019-09-023-0/+67
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* synth: handle conditional variable assignment.Tristan Gingold2019-09-021-0/+34
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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-0210-42/+45
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* vhdl synth: recognize more operators (add uns log).Tristan Gingold2019-09-024-100/+157
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* revert "configure: fix setting abs_srcdir on MSYS2/MINGW" (#911) (#914)1138-4EB2019-09-021-6/+5
| | | This reverts commit 7b02418ec508af9e340cad5e93ab06e8f1fb84c8.
* Fix UPF (#905)1138-4EB2019-09-014-5/+21
| | | | | | * add test for UPF * fix: add UPF when openieee=false too
* Fix configure (#911)1138-4EB2019-09-011-216/+222
| | | | | | | | | | | | * configure: fix indentation * configure: add comment about using 'cmp -n' * configure: check if 'cmp' is available * configure: fix setting abs_srcdir on MSYS2/MINGW * configure: fix comment
* fix(configure): ignore line ending when comparing ghdl_version and ↵1138-4EB2019-09-011-1/+1
| | | | libghdl_version (#910)
* readme: fix refs to 'Building' (#909)1138-4EB2019-08-311-3/+3
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* [doc] Update section 'Getting GHDL' (#906)1138-4EB2019-08-3121-425/+268
| | | | | | | | * doc: fix version extraction from 'configure' * doc: update section 'Getting GHDL' * readme: update
* Merge pull request #907 from sharkcz/llvm-fixtgingold2019-08-311-1/+1
|\ | | | | fix llvm build with synth enabled
| * fix llvm build with synth enabledDan Horák2019-08-311-1/+1
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* synth: remove insert gate.Tristan Gingold2019-08-314-70/+0
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* synth: improve synth_uresize.Tristan Gingold2019-08-313-26/+50
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* synth: elab subprogram interfaces subtypeTristan Gingold2019-08-311-2/+13
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* [PATCH] synth-environment: fix thinkos.Tristan Gingold2019-08-318-15/+231
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* synth: add physical division (#904)tgingold2019-08-303-1/+36
|\ | | | | | | | | | | * synth: added division of physical type * testsuite/synth: added test for the physical division
| * testsuite/synth: added test for the physical divisionMartin Doerfelt2019-08-302-0/+25
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| * synth: added division of physical typeMartin Doerfelt2019-08-301-1/+11
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* | synth: add support for --synth on llvm, link with -lm.Tristan Gingold2019-08-302-0/+6
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* | synth: fix type elaboration of interfaces.Tristan Gingold2019-08-301-2/+0
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* | synth: remove unused const gates.Tristan Gingold2019-08-302-13/+5
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* | vhdl-annotations: ignore conditional variable assignment.Tristan Gingold2019-08-301-1/+2
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* | vhdl-annotate: handle shared anonymous subtype in interfaces.Tristan Gingold2019-08-301-1/+4
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* | synth: ignore report statement.Tristan Gingold2019-08-301-0/+2
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* | vhdl: recognize ieee.numeric_std std_match.Tristan Gingold2019-08-304-196/+241
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* | std_names: add std_matchTristan Gingold2019-08-302-3/+5
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* | vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-305-114/+137
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* | synth: handle enumeration subtype in ranges.Tristan Gingold2019-08-301-1/+2
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* | synth: fix named association in record aggregate.Tristan Gingold2019-08-301-1/+3
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* testsuite/synth: add testcase for records. Temporary disable stmt01Tristan Gingold2019-08-295-0/+168
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* synth: add support for record types.Tristan Gingold2019-08-2913-82/+361
| | | | (WIP: need to fix regression of stmt01).
* synth: Integer operators (#902)marph912019-08-283-0/+47
| | | | | | | | * synth: added missing integer operators I. e. inequality and remainder. * testsuite/synth: added testcase for the missing integer operators
* testsuite/synth: testcase for conditional signal assignment.Tristan Gingold2019-08-273-0/+61
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* synth: support sequential conditional signal assignment.Tristan Gingold2019-08-272-0/+3
| | | | Fix tgingold/ghdlsynth-beta#40
* testsuite/synth: add cases for assign.Tristan Gingold2019-08-274-4/+62
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* testsuite/synth: add asgn01Tristan Gingold2019-08-275-0/+124
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* synth: rework partial assignmentsTristan Gingold2019-08-2710-182/+608
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* netlists-disp_vhdl: do not used literals for prefixes.Tristan Gingold2019-08-271-12/+53
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* Makefile.in: Add .NOTPARALLEL. For #888Tristan Gingold2019-08-271-0/+9
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* testsuite/synth: add fsm02 test.Tristan Gingold2019-08-275-0/+181
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* ignore restrict in simulation (#897)Pepijn de Vos2019-08-202-18/+17
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* synth: add support for constant exponentiation.Tristan Gingold2019-08-201-0/+10
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* synth: set name to assert/assume gates.Tristan Gingold2019-08-204-12/+44
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* netlist: fix minor pasto.Tristan Gingold2019-08-201-1/+1
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* initial support for reduce and/or (#900)Pepijn de Vos2019-08-207-6/+77
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* vhdl psl: fully scan PSL keywords in scanner.Tristan Gingold2019-08-207-67/+148
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* vhdl-prints: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-0/+7
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* testsuite/synth: add a test for previous commit.Tristan Gingold2019-08-202-0/+13
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