diff options
| author | Tristan Gingold <tgingold@free.fr> | 2019-08-27 13:55:57 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-27 13:55:57 +0200 |
| commit | 4870e051898d752407da802d4297d1f83bfbe433 (patch) | |
| tree | 41a5e01ce5bf619d23dc15377dee0605670efde7 | |
| parent | 26c13e748d27454a43ea1c341570b48a40cd2067 (diff) | |
| download | ghdl-4870e051898d752407da802d4297d1f83bfbe433.tar.gz ghdl-4870e051898d752407da802d4297d1f83bfbe433.tar.bz2 ghdl-4870e051898d752407da802d4297d1f83bfbe433.zip | |
synth: support sequential conditional signal assignment.
Fix tgingold/ghdlsynth-beta#40
| -rw-r--r-- | src/synth/synth-stmts.adb | 2 | ||||
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index f37b1388e..b16952d17 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1144,6 +1144,8 @@ package body Synth.Stmts is Synth_If_Statement (Syn_Inst, Stmt); when Iir_Kind_Simple_Signal_Assignment_Statement => Synth_Simple_Signal_Assignment (Syn_Inst, Stmt); + when Iir_Kind_Conditional_Signal_Assignment_Statement => + Synth_Conditional_Signal_Assignment (Syn_Inst, Stmt); when Iir_Kind_Variable_Assignment_Statement => Synth_Variable_Assignment (Syn_Inst, Stmt); when Iir_Kind_Case_Statement => diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index b23e4b6e6..1e3b00043 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -872,6 +872,7 @@ package body Vhdl.Annotations is null; when Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement + | Iir_Kind_Conditional_Signal_Assignment_Statement | Iir_Kind_Variable_Assignment_Statement => null; when Iir_Kind_Procedure_Call_Statement => |