vhdl synth: recognize more operators (add uns log).

4 files changed, 157 insertions, 100 deletions

diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py
index 8b99eefc4..3b99fafc4 100644
--- a/python/libghdl/thin/vhdl/nodes.py
+++ b/python/libghdl/thin/vhdl/nodes.py
@@ -1074,97 +1074,101 @@ class Iir_Predefined:
     Ieee_Numeric_Std_Add_Uns_Uns = 199
     Ieee_Numeric_Std_Add_Uns_Nat = 200
     Ieee_Numeric_Std_Add_Nat_Uns = 201
-    Ieee_Numeric_Std_Add_Sgn_Sgn = 202
-    Ieee_Numeric_Std_Add_Sgn_Int = 203
-    Ieee_Numeric_Std_Add_Int_Sgn = 204
-    Ieee_Numeric_Std_Sub_Uns_Uns = 205
-    Ieee_Numeric_Std_Sub_Uns_Nat = 206
-    Ieee_Numeric_Std_Sub_Nat_Uns = 207
-    Ieee_Numeric_Std_Sub_Sgn_Sgn = 208
-    Ieee_Numeric_Std_Sub_Sgn_Int = 209
-    Ieee_Numeric_Std_Sub_Int_Sgn = 210
-    Ieee_Numeric_Std_Gt_Uns_Uns = 211
-    Ieee_Numeric_Std_Gt_Uns_Nat = 212
-    Ieee_Numeric_Std_Gt_Nat_Uns = 213
-    Ieee_Numeric_Std_Gt_Sgn_Sgn = 214
-    Ieee_Numeric_Std_Gt_Sgn_Int = 215
-    Ieee_Numeric_Std_Gt_Int_Sgn = 216
-    Ieee_Numeric_Std_Lt_Uns_Uns = 217
-    Ieee_Numeric_Std_Lt_Uns_Nat = 218
-    Ieee_Numeric_Std_Lt_Nat_Uns = 219
-    Ieee_Numeric_Std_Lt_Sgn_Sgn = 220
-    Ieee_Numeric_Std_Lt_Sgn_Int = 221
-    Ieee_Numeric_Std_Lt_Int_Sgn = 222
-    Ieee_Numeric_Std_Le_Uns_Uns = 223
-    Ieee_Numeric_Std_Le_Uns_Nat = 224
-    Ieee_Numeric_Std_Le_Nat_Uns = 225
-    Ieee_Numeric_Std_Le_Sgn_Sgn = 226
-    Ieee_Numeric_Std_Le_Sgn_Int = 227
-    Ieee_Numeric_Std_Le_Int_Sgn = 228
-    Ieee_Numeric_Std_Ge_Uns_Uns = 229
-    Ieee_Numeric_Std_Ge_Uns_Nat = 230
-    Ieee_Numeric_Std_Ge_Nat_Uns = 231
-    Ieee_Numeric_Std_Ge_Sgn_Sgn = 232
-    Ieee_Numeric_Std_Ge_Sgn_Int = 233
-    Ieee_Numeric_Std_Ge_Int_Sgn = 234
-    Ieee_Numeric_Std_Eq_Uns_Uns = 235
-    Ieee_Numeric_Std_Eq_Uns_Nat = 236
-    Ieee_Numeric_Std_Eq_Nat_Uns = 237
-    Ieee_Numeric_Std_Eq_Sgn_Sgn = 238
-    Ieee_Numeric_Std_Eq_Sgn_Int = 239
-    Ieee_Numeric_Std_Eq_Int_Sgn = 240
-    Ieee_Numeric_Std_Ne_Uns_Uns = 241
-    Ieee_Numeric_Std_Ne_Uns_Nat = 242
-    Ieee_Numeric_Std_Ne_Nat_Uns = 243
-    Ieee_Numeric_Std_Ne_Sgn_Sgn = 244
-    Ieee_Numeric_Std_Ne_Sgn_Int = 245
-    Ieee_Numeric_Std_Ne_Int_Sgn = 246
-    Ieee_Numeric_Std_Not_Uns = 247
-    Ieee_Numeric_Std_Not_Sgn = 248
-    Ieee_Numeric_Std_And_Uns_Uns = 249
-    Ieee_Numeric_Std_And_Sgn_Sgn = 250
-    Ieee_Numeric_Std_Or_Uns_Uns = 251
-    Ieee_Numeric_Std_Or_Sgn_Sgn = 252
-    Ieee_Numeric_Std_Nand_Uns_Uns = 253
-    Ieee_Numeric_Std_Nand_Sgn_Sgn = 254
-    Ieee_Numeric_Std_Nor_Uns_Uns = 255
-    Ieee_Numeric_Std_Nor_Sgn_Sgn = 256
-    Ieee_Numeric_Std_Xor_Uns_Uns = 257
-    Ieee_Numeric_Std_Xor_Sgn_Sgn = 258
-    Ieee_Numeric_Std_Xnor_Uns_Uns = 259
-    Ieee_Numeric_Std_Xnor_Sgn_Sgn = 260
-    Ieee_Numeric_Std_Neg_Uns = 261
-    Ieee_Numeric_Std_Neg_Sgn = 262
-    Ieee_Numeric_Std_Match_Log = 263
-    Ieee_Numeric_Std_Match_Uns = 264
-    Ieee_Numeric_Std_Match_Sgn = 265
-    Ieee_Numeric_Std_Match_Slv = 266
-    Ieee_Numeric_Std_Match_Suv = 267
-    Ieee_Math_Real_Ceil = 268
-    Ieee_Math_Real_Log2 = 269
-    Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 270
-    Ieee_Std_Logic_Unsigned_Add_Slv_Int = 271
-    Ieee_Std_Logic_Unsigned_Add_Int_Slv = 272
-    Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 273
-    Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 274
-    Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 275
-    Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 276
-    Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 277
-    Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 278
-    Ieee_Std_Logic_Unsigned_Le_Slv_Int = 279
-    Ieee_Std_Logic_Unsigned_Le_Int_Slv = 280
-    Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 281
-    Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 282
-    Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 283
-    Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 284
-    Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 285
-    Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 286
-    Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 287
-    Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 288
-    Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 289
-    Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 290
-    Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 291
-    Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 292
+    Ieee_Numeric_Std_Add_Uns_Log = 202
+    Ieee_Numeric_Std_Add_Log_Uns = 203
+    Ieee_Numeric_Std_Add_Sgn_Sgn = 204
+    Ieee_Numeric_Std_Add_Sgn_Int = 205
+    Ieee_Numeric_Std_Add_Int_Sgn = 206
+    Ieee_Numeric_Std_Add_Sgn_Log = 207
+    Ieee_Numeric_Std_Add_Log_Sgn = 208
+    Ieee_Numeric_Std_Sub_Uns_Uns = 209
+    Ieee_Numeric_Std_Sub_Uns_Nat = 210
+    Ieee_Numeric_Std_Sub_Nat_Uns = 211
+    Ieee_Numeric_Std_Sub_Sgn_Sgn = 212
+    Ieee_Numeric_Std_Sub_Sgn_Int = 213
+    Ieee_Numeric_Std_Sub_Int_Sgn = 214
+    Ieee_Numeric_Std_Gt_Uns_Uns = 215
+    Ieee_Numeric_Std_Gt_Uns_Nat = 216
+    Ieee_Numeric_Std_Gt_Nat_Uns = 217
+    Ieee_Numeric_Std_Gt_Sgn_Sgn = 218
+    Ieee_Numeric_Std_Gt_Sgn_Int = 219
+    Ieee_Numeric_Std_Gt_Int_Sgn = 220
+    Ieee_Numeric_Std_Lt_Uns_Uns = 221
+    Ieee_Numeric_Std_Lt_Uns_Nat = 222
+    Ieee_Numeric_Std_Lt_Nat_Uns = 223
+    Ieee_Numeric_Std_Lt_Sgn_Sgn = 224
+    Ieee_Numeric_Std_Lt_Sgn_Int = 225
+    Ieee_Numeric_Std_Lt_Int_Sgn = 226
+    Ieee_Numeric_Std_Le_Uns_Uns = 227
+    Ieee_Numeric_Std_Le_Uns_Nat = 228
+    Ieee_Numeric_Std_Le_Nat_Uns = 229
+    Ieee_Numeric_Std_Le_Sgn_Sgn = 230
+    Ieee_Numeric_Std_Le_Sgn_Int = 231
+    Ieee_Numeric_Std_Le_Int_Sgn = 232
+    Ieee_Numeric_Std_Ge_Uns_Uns = 233
+    Ieee_Numeric_Std_Ge_Uns_Nat = 234
+    Ieee_Numeric_Std_Ge_Nat_Uns = 235
+    Ieee_Numeric_Std_Ge_Sgn_Sgn = 236
+    Ieee_Numeric_Std_Ge_Sgn_Int = 237
+    Ieee_Numeric_Std_Ge_Int_Sgn = 238
+    Ieee_Numeric_Std_Eq_Uns_Uns = 239
+    Ieee_Numeric_Std_Eq_Uns_Nat = 240
+    Ieee_Numeric_Std_Eq_Nat_Uns = 241
+    Ieee_Numeric_Std_Eq_Sgn_Sgn = 242
+    Ieee_Numeric_Std_Eq_Sgn_Int = 243
+    Ieee_Numeric_Std_Eq_Int_Sgn = 244
+    Ieee_Numeric_Std_Ne_Uns_Uns = 245
+    Ieee_Numeric_Std_Ne_Uns_Nat = 246
+    Ieee_Numeric_Std_Ne_Nat_Uns = 247
+    Ieee_Numeric_Std_Ne_Sgn_Sgn = 248
+    Ieee_Numeric_Std_Ne_Sgn_Int = 249
+    Ieee_Numeric_Std_Ne_Int_Sgn = 250
+    Ieee_Numeric_Std_Not_Uns = 251
+    Ieee_Numeric_Std_Not_Sgn = 252
+    Ieee_Numeric_Std_And_Uns_Uns = 253
+    Ieee_Numeric_Std_And_Sgn_Sgn = 254
+    Ieee_Numeric_Std_Or_Uns_Uns = 255
+    Ieee_Numeric_Std_Or_Sgn_Sgn = 256
+    Ieee_Numeric_Std_Nand_Uns_Uns = 257
+    Ieee_Numeric_Std_Nand_Sgn_Sgn = 258
+    Ieee_Numeric_Std_Nor_Uns_Uns = 259
+    Ieee_Numeric_Std_Nor_Sgn_Sgn = 260
+    Ieee_Numeric_Std_Xor_Uns_Uns = 261
+    Ieee_Numeric_Std_Xor_Sgn_Sgn = 262
+    Ieee_Numeric_Std_Xnor_Uns_Uns = 263
+    Ieee_Numeric_Std_Xnor_Sgn_Sgn = 264
+    Ieee_Numeric_Std_Neg_Uns = 265
+    Ieee_Numeric_Std_Neg_Sgn = 266
+    Ieee_Numeric_Std_Match_Log = 267
+    Ieee_Numeric_Std_Match_Uns = 268
+    Ieee_Numeric_Std_Match_Sgn = 269
+    Ieee_Numeric_Std_Match_Slv = 270
+    Ieee_Numeric_Std_Match_Suv = 271
+    Ieee_Math_Real_Ceil = 272
+    Ieee_Math_Real_Log2 = 273
+    Ieee_Std_Logic_Unsigned_Add_Slv_Slv = 274
+    Ieee_Std_Logic_Unsigned_Add_Slv_Int = 275
+    Ieee_Std_Logic_Unsigned_Add_Int_Slv = 276
+    Ieee_Std_Logic_Unsigned_Add_Slv_Sl = 277
+    Ieee_Std_Logic_Unsigned_Add_Sl_Slv = 278
+    Ieee_Std_Logic_Unsigned_Lt_Slv_Slv = 279
+    Ieee_Std_Logic_Unsigned_Lt_Slv_Int = 280
+    Ieee_Std_Logic_Unsigned_Lt_Int_Slv = 281
+    Ieee_Std_Logic_Unsigned_Le_Slv_Slv = 282
+    Ieee_Std_Logic_Unsigned_Le_Slv_Int = 283
+    Ieee_Std_Logic_Unsigned_Le_Int_Slv = 284
+    Ieee_Std_Logic_Unsigned_Gt_Slv_Slv = 285
+    Ieee_Std_Logic_Unsigned_Gt_Slv_Int = 286
+    Ieee_Std_Logic_Unsigned_Gt_Int_Slv = 287
+    Ieee_Std_Logic_Unsigned_Ge_Slv_Slv = 288
+    Ieee_Std_Logic_Unsigned_Ge_Slv_Int = 289
+    Ieee_Std_Logic_Unsigned_Ge_Int_Slv = 290
+    Ieee_Std_Logic_Unsigned_Eq_Slv_Slv = 291
+    Ieee_Std_Logic_Unsigned_Eq_Slv_Int = 292
+    Ieee_Std_Logic_Unsigned_Eq_Int_Slv = 293
+    Ieee_Std_Logic_Unsigned_Ne_Slv_Slv = 294
+    Ieee_Std_Logic_Unsigned_Ne_Slv_Int = 295
+    Ieee_Std_Logic_Unsigned_Ne_Int_Slv = 296
 
 Get_Kind = libghdl.vhdl__nodes__get_kind
 Get_Location = libghdl.vhdl__nodes__get_location
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index d99e1acc1..8320f2897 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -165,18 +165,42 @@ package body Synth.Expr is
 
    function Synth_Uresize (N : Net; W : Width; Loc : Node) return Net
    is
-      pragma Unreferenced (Loc);
       Wn : constant Width := Get_Width (N);
+      Res : Net;
    begin
-      if Wn > W then
-         return Build_Trunc (Build_Context, Id_Utrunc, N, W);
-      elsif Wn < W then
-         return Build_Extend (Build_Context, Id_Uextend, N, W);
-      else
+      if Wn = W then
          return N;
+      else
+         if Wn > W then
+            Res := Build_Trunc (Build_Context, Id_Utrunc, N, W);
+         else
+            pragma Assert (Wn < W);
+            Res := Build_Extend (Build_Context, Id_Uextend, N, W);
+         end if;
+         Set_Location (Res, Loc);
+         return Res;
       end if;
    end Synth_Uresize;
 
+   function Synth_Sresize (N : Net; W : Width; Loc : Node) return Net
+   is
+      Wn : constant Width := Get_Width (N);
+      Res : Net;
+   begin
+      if Wn = W then
+         return N;
+      else
+         if Wn > W then
+            Res := Build_Trunc (Build_Context, Id_Strunc, N, W);
+         else
+            pragma Assert (Wn < W);
+            Res := Build_Extend (Build_Context, Id_Sextend, N, W);
+         end if;
+         Set_Location (Res, Loc);
+         return Res;
+      end if;
+   end Synth_Sresize;
+
    function Synth_Uresize (Val : Value_Acc; W : Width; Loc : Node) return Net
    is
       Res : Net;
@@ -225,7 +249,6 @@ package body Synth.Expr is
       end if;
    end Synth_Resize;
 
-
    function Get_Index_Offset
      (Index : Value_Acc; Bounds : Bound_Type; Expr : Iir) return Uns32 is
    begin
@@ -984,6 +1007,28 @@ package body Synth.Expr is
          return Create_Value_Net (N, Rtype);
       end Synth_Dyadic_Uns;
 
+      function Synth_Dyadic_Sgn (Id : Dyadic_Module_Id; Is_Res_Vec : Boolean)
+                                return Value_Acc
+      is
+         L : constant Net := Get_Net (Left);
+         R : constant Net := Get_Net (Right);
+         W : constant Width := Width'Max (Get_Width (L), Get_Width (R));
+         Rtype : Type_Acc;
+         L1, R1 : Net;
+         N : Net;
+      begin
+         if Is_Res_Vec then
+            Rtype := Create_Vec_Type_By_Length (W, Left.Typ.Vec_El);
+         else
+            Rtype := Left.Typ;
+         end if;
+         L1 := Synth_Sresize (L, W, Expr);
+         R1 := Synth_Sresize (R, W, Expr);
+         N := Build_Dyadic (Build_Context, Id, L1, R1);
+         Set_Location (N, Expr);
+         return Create_Value_Net (N, Rtype);
+      end Synth_Dyadic_Sgn;
+
       function Synth_Compare_Uns_Uns (Id : Compare_Module_Id)
                                      return Value_Acc
       is
@@ -1108,9 +1153,13 @@ package body Synth.Expr is
             --  "+" (Unsigned, Natural)
             return Synth_Dyadic_Uns_Nat (Id_Add);
          when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns
+           | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log
            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl =>
             --  "+" (Unsigned, Unsigned)
             return Synth_Dyadic_Uns (Id_Add, True);
+         when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn =>
+            --  "+" (Signed, Signed)
+            return Synth_Dyadic_Sgn (Id_Add, True);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat =>
             --  "-" (Unsigned, Natural)
             return Synth_Dyadic_Uns_Nat (Id_Sub);
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb
index a1ac7927e..cf0f7db26 100644
--- a/src/vhdl/vhdl-ieee-numeric.adb
+++ b/src/vhdl/vhdl-ieee-numeric.adb
@@ -43,8 +43,8 @@ package body Vhdl.Ieee.Numeric is
            (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns,
             Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat,
             Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns,
-            Arg_Vect_Log  => Iir_Predefined_None,
-            Arg_Log_Vect  => Iir_Predefined_None),
+            Arg_Vect_Log  => Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log,
+            Arg_Log_Vect  => Iir_Predefined_Ieee_Numeric_Std_Add_Log_Uns),
          Type_Signed =>
            (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn,
             Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int,
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 3a2bcb20b..fe7b89066 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -4927,9 +4927,13 @@ package Vhdl.Nodes is
       Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns,
       Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat,
       Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns,
+      Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log,
+      Iir_Predefined_Ieee_Numeric_Std_Add_Log_Uns,
       Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn,
       Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int,
       Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn,
+      Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log,
+      Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn,
 
       Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns,
       Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat,