synth: Integer operators (#902)

* synth: added missing integer operators

I. e. inequality and remainder.

* testsuite/synth: added testcase for the missing integer operators

3 files changed, 47 insertions, 0 deletions

diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index a21309b47..063257008 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -1196,6 +1196,15 @@ package body Synth.Expr is
                Error_Msg_Synth (+Expr, "non-constant mod not supported");
                return null;
             end if;
+         when Iir_Predefined_Integer_Rem =>
+            if Is_Const (Left) and then Is_Const (Right) then
+               return Create_Value_Discrete
+                 (Left.Scal rem Right.Scal,
+                  Get_Value_Type (Syn_Inst, Get_Type (Expr)));
+            else
+               Error_Msg_Synth (+Expr, "non-constant rem not supported");
+               return null;
+            end if;
          when Iir_Predefined_Integer_Exp =>
             if Is_Const (Left) and then Is_Const (Right) then
                return Create_Value_Discrete
@@ -1241,6 +1250,13 @@ package body Synth.Expr is
             else
                return Synth_Compare (Id_Eq);
             end if;
+         when Iir_Predefined_Integer_Inequality =>
+            if Is_Const (Left) and then Is_Const (Right) then
+               return Create_Value_Discrete
+                 (Boolean'Pos (Left.Scal /= Right.Scal), Boolean_Type);
+            else
+               return Synth_Compare (Id_Ne);
+            end if;
 
          when others =>
             Error_Msg_Synth (+Expr, "synth_dyadic_operation: unhandled "
diff --git a/testsuite/synth/int01/int_operators.vhdl b/testsuite/synth/int01/int_operators.vhdl
new file mode 100644
index 000000000..6a09c0621
--- /dev/null
+++ b/testsuite/synth/int01/int_operators.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity int_operators is
+  generic (
+    gen_a : integer := 5;
+    gen_b : integer := 3
+  );
+  port (
+    sig_a : in integer range 0 to 7;
+    sig_b : out std_logic;
+    sig_c : out integer
+  );
+end int_operators;
+
+architecture rtl of int_operators is
+begin
+  sig_b <= '0' when sig_a /= gen_a else '1';
+  sig_c <= gen_a rem gen_b;
+end rtl;
diff --git a/testsuite/synth/int01/testsuite.sh b/testsuite/synth/int01/testsuite.sh
new file mode 100755
index 000000000..a590cde72
--- /dev/null
+++ b/testsuite/synth/int01/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in int_operators; do
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl
+    clean
+done
+
+echo "Test successful"