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* vhdl-sem: avoid a crash after error. Fix #2201Tristan Gingold2022-09-281-0/+1
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* synth: handle names in record aggregate targetsTristan Gingold2022-09-281-0/+12
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* synth: handle array target aggregateTristan Gingold2022-09-271-2/+6
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* synth: handle error on variable default valueTristan Gingold2022-09-271-0/+5
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* simul: handle null signal assignmentsTristan Gingold2022-09-271-12/+36
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* synth-vhdl_eval: handle nor, nandTristan Gingold2022-09-261-0/+21
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* simul-vhdl_elab: avoid a crash for null-range signalsTristan Gingold2022-09-261-10/+14
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* synth: handle attributes in configurationsTristan Gingold2022-09-264-3/+16
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* synth: improve error checks (type conversion, string literals)Tristan Gingold2022-09-253-33/+37
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* synth: rework error procedure, always pass the instanceTristan Gingold2022-09-2517-254/+406
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* synth-vhdl_eval: handle vhdl-87 array array concatenationTristan Gingold2022-09-251-2/+31
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* testsuite/gna: add a test for #2196Tristan Gingold2022-09-252-0/+55
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* vhdl-sem_decls: handle protected type subtypesTristan Gingold2022-09-251-1/+4
| | | | Fix #2196
* testsuite/gna: add a test for #2198Tristan Gingold2022-09-252-0/+60
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* vhdl-sem_names: handle architecture bodies in sem_denoting_nameTristan Gingold2022-09-251-1/+2
| | | | Fix #2198
* synth-vhdl_stmts: fix missing newline in default assertion messagesTristan Gingold2022-09-251-3/+3
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* synth: handle default expression for IN variables in assocsTristan Gingold2022-09-251-4/+10
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* synth: handle selected names in targetsTristan Gingold2022-09-251-1/+2
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* synth-vhdl_eval: handle null-null in array concatenationsTristan Gingold2022-09-251-0/+6
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* simul: gather disconnection specifications, create guard signalTristan Gingold2022-09-254-36/+194
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* synth: ignore groups and group templatesTristan Gingold2022-09-253-1/+15
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* grt: do not initialial GUARD signals on creation.Tristan Gingold2022-09-251-1/+4
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* synth: handle attribute namesTristan Gingold2022-09-251-13/+16
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* synth: handle individual subprogram associations for expressionsTristan Gingold2022-09-251-55/+61
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* simul: handle empty proceduresTristan Gingold2022-09-251-1/+9
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* synth: rework association conversionsTristan Gingold2022-09-253-62/+75
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* synth-vhdl_stmts: rework for subprogram associations (WIP)Tristan Gingold2022-09-251-57/+36
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* synth-vhdl_stmts: support of individual paramater associations (WIP)Tristan Gingold2022-09-252-106/+238
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* simul: reuse drivers extraction from elaborationTristan Gingold2022-09-252-74/+26
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* synth-vhdl_stmts: refactore synth_subprogram_associationsTristan Gingold2022-09-251-49/+52
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* suite_driver.sh: print a message in case of failureTristan Gingold2022-09-251-0/+1
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* synth-vhdl_stmts: refactoreTristan Gingold2022-09-251-23/+32
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* synth-vhdl_stmts: refactoringTristan Gingold2022-09-251-189/+208
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* synth-vhdl_stmts: rework in progress of subprogram associationsTristan Gingold2022-09-251-108/+115
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* pyGHDL: added missing type annotations. Fix #2192 (#2195)fhuemer2022-09-231-2/+2
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* synth-vhdl_insts: move pragma unreferencedTristan Gingold2022-09-211-1/+2
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* configure: tentatively enable llvm 15Tristan Gingold2022-09-211-0/+1
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* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-192-51/+3
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* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-195-197/+31
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* synth: rename vhdl.annotations to elab.vhdl_annotationsTristan Gingold2022-09-198-18/+20
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* synth: rework subprogram associations (WIP)Tristan Gingold2022-09-193-42/+87
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* synth-vhdl_stmts: minor renamingTristan Gingold2022-09-184-12/+12
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* synth: fix assert failure on attribute specificationTristan Gingold2022-09-181-1/+5
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* simul: handle individual port associations with expressionsTristan Gingold2022-09-181-1/+5
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* simul: handle type conversions in port associationsTristan Gingold2022-09-183-49/+57
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* synth: handle open variable associationTristan Gingold2022-09-171-22/+31
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* simul: fix resolved associationTristan Gingold2022-09-172-2/+3
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* simul: use synth_declarations for processes and proceduresTristan Gingold2022-09-174-18/+15
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* synth: factorize code (reuse synth_constant_declaration)Tristan Gingold2022-09-178-71/+22
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* synth: handle protected types in subprogramsTristan Gingold2022-09-173-38/+53
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