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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-18 08:57:27 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-18 08:57:27 +0200 |
| commit | f0900d17ff6ac00d3653e7aea5af166b603b155a (patch) | |
| tree | b7631cf8c8115cf8d1151f5c714c25a785c46efd | |
| parent | 712c08710de22ecbcbf42527ef516160591a1000 (diff) | |
| download | ghdl-f0900d17ff6ac00d3653e7aea5af166b603b155a.tar.gz ghdl-f0900d17ff6ac00d3653e7aea5af166b603b155a.tar.bz2 ghdl-f0900d17ff6ac00d3653e7aea5af166b603b155a.zip | |
synth-vhdl_stmts: minor renaming
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 10 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.ads | 8 |
4 files changed, 12 insertions, 12 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index b5f14a067..4a8ef443f 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -758,7 +758,7 @@ package body Simul.Vhdl_Simul is pragma Assert (Obj = Null_Node); Sub_Inst := Synth_Subprogram_Call_Instance (Inst, Imp, Imp); - Synth_Subprogram_Association + Synth_Subprogram_Associations (Sub_Inst, Inst, Inter_Chain, Assoc_Chain); Synth.Vhdl_Static_Proc.Synth_Static_Procedure @@ -791,7 +791,7 @@ package body Simul.Vhdl_Simul is -- Note: in fact the uninstantiated scope is the instantiated -- one! Set_Uninstantiated_Scope (Sub_Inst, Imp); - Synth_Subprogram_Association + Synth_Subprogram_Associations (Sub_Inst, Inst, Inter_Chain, Assoc_Chain); Process.Instance := Sub_Inst; diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 7feb61c5b..2996ea0dd 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -2188,7 +2188,7 @@ package body Synth.Vhdl_Oper is Areapools.Mark (M, Instance_Pool.all); Subprg_Inst := Make_Instance (Syn_Inst, Imp); - Synth_Subprogram_Association + Synth_Subprogram_Associations (Subprg_Inst, Syn_Inst, Inter_Chain, Assoc_Chain); if Is_Error (Subprg_Inst) then diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index b0726d03b..ffa780625 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -2137,16 +2137,16 @@ package body Synth.Vhdl_Stmts is end loop; end Synth_Subprogram_Associations; - procedure Synth_Subprogram_Association (Subprg_Inst : Synth_Instance_Acc; - Caller_Inst : Synth_Instance_Acc; - Inter_Chain : Node; - Assoc_Chain : Node) + procedure Synth_Subprogram_Associations (Subprg_Inst : Synth_Instance_Acc; + Caller_Inst : Synth_Instance_Acc; + Inter_Chain : Node; + Assoc_Chain : Node) is Init : Association_Iterator_Init; begin Init := Association_Iterator_Build (Inter_Chain, Assoc_Chain); Synth_Subprogram_Associations (Subprg_Inst, Caller_Inst, Init); - end Synth_Subprogram_Association; + end Synth_Subprogram_Associations; -- Create wires for out and inout interface variables. procedure Synth_Subprogram_Association_Wires diff --git a/src/synth/synth-vhdl_stmts.ads b/src/synth/synth-vhdl_stmts.ads index fde8fd8cd..6afd115d3 100644 --- a/src/synth/synth-vhdl_stmts.ads +++ b/src/synth/synth-vhdl_stmts.ads @@ -48,10 +48,10 @@ package Synth.Vhdl_Stmts is Bod : Node) return Synth_Instance_Acc; - procedure Synth_Subprogram_Association (Subprg_Inst : Synth_Instance_Acc; - Caller_Inst : Synth_Instance_Acc; - Inter_Chain : Node; - Assoc_Chain : Node); + procedure Synth_Subprogram_Associations (Subprg_Inst : Synth_Instance_Acc; + Caller_Inst : Synth_Instance_Acc; + Inter_Chain : Node; + Assoc_Chain : Node); -- Dynamic index for Synth_Assignment_Prefix. -- As dynamic is about dynamic (!) index, the index is a net. |