diff options
108 files changed, 16200 insertions, 0 deletions
diff --git a/testsuite/gna/bug040/add_200.vhd b/testsuite/gna/bug040/add_200.vhd new file mode 100644 index 000000000..8aea8c6a5 --- /dev/null +++ b/testsuite/gna/bug040/add_200.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_200 is + port ( + output : out std_logic_vector(38 downto 0); + in_b : in std_logic_vector(38 downto 0); + in_a : in std_logic_vector(38 downto 0) + ); +end add_200; + +architecture augh of add_200 is + + signal carry_inA : std_logic_vector(40 downto 0); + signal carry_inB : std_logic_vector(40 downto 0); + signal carry_res : std_logic_vector(40 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(39 downto 1); + +end architecture; diff --git a/testsuite/gna/bug040/add_201.vhd b/testsuite/gna/bug040/add_201.vhd new file mode 100644 index 000000000..726ffce26 --- /dev/null +++ b/testsuite/gna/bug040/add_201.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_201 is + port ( + output : out std_logic_vector(38 downto 0); + in_b : in std_logic_vector(38 downto 0); + in_a : in std_logic_vector(38 downto 0) + ); +end add_201; + +architecture augh of add_201 is + + signal carry_inA : std_logic_vector(40 downto 0); + signal carry_inB : std_logic_vector(40 downto 0); + signal carry_res : std_logic_vector(40 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(39 downto 1); + +end architecture; diff --git a/testsuite/gna/bug040/add_202.vhd b/testsuite/gna/bug040/add_202.vhd new file mode 100644 index 000000000..a0108a493 --- /dev/null +++ b/testsuite/gna/bug040/add_202.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_202 is + port ( + output : out std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); +end add_202; + +architecture augh of add_202 is + + signal carry_inA : std_logic_vector(33 downto 0); + signal carry_inB : std_logic_vector(33 downto 0); + signal carry_res : std_logic_vector(33 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(32 downto 1); + +end architecture; diff --git a/testsuite/gna/bug040/add_203.vhd b/testsuite/gna/bug040/add_203.vhd new file mode 100644 index 000000000..1baea25f9 --- /dev/null +++ b/testsuite/gna/bug040/add_203.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_203 is + port ( + output : out std_logic_vector(38 downto 0); + in_b : in std_logic_vector(38 downto 0); + in_a : in std_logic_vector(38 downto 0) + ); +end add_203; + +architecture augh of add_203 is + + signal carry_inA : std_logic_vector(40 downto 0); + signal carry_inB : std_logic_vector(40 downto 0); + signal carry_res : std_logic_vector(40 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(39 downto 1); + +end architecture; diff --git a/testsuite/gna/bug040/add_204.vhd b/testsuite/gna/bug040/add_204.vhd new file mode 100644 index 000000000..ba94a29c0 --- /dev/null +++ b/testsuite/gna/bug040/add_204.vhd @@ -0,0 +1,33 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity add_204 is + port ( + output : out std_logic_vector(24 downto 0); + in_b : in std_logic_vector(24 downto 0); + in_a : in std_logic_vector(24 downto 0) + ); +end add_204; + +architecture augh of add_204 is + + signal carry_inA : std_logic_vector(26 downto 0); + signal carry_inB : std_logic_vector(26 downto 0); + signal carry_res : std_logic_vector(26 downto 0); + +begin + + -- To handle the CI input, the operation is '1' + CI + -- If CI is not present, the operation is '1' + '0' + carry_inA <= '0' & in_a & '1'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(25 downto 1); + +end architecture; diff --git a/testsuite/gna/bug040/bit_set_mask.vhd b/testsuite/gna/bug040/bit_set_mask.vhd new file mode 100644 index 000000000..123b0ddcf --- /dev/null +++ b/testsuite/gna/bug040/bit_set_mask.vhd @@ -0,0 +1,60 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity bit_set_mask is + port ( + clk : in std_logic; + ra0_addr : in std_logic_vector(4 downto 0); + ra0_data : out std_logic_vector(31 downto 0) + ); +end bit_set_mask; +architecture augh of bit_set_mask is + + -- Embedded RAM + + type ram_type is array (0 to 31) of std_logic_vector(31 downto 0); + signal ram : ram_type := ( + "00000000000000000000000000000001", "00000000000000000000000000000010", "00000000000000000000000000000100", + "00000000000000000000000000001000", "00000000000000000000000000010000", "00000000000000000000000000100000", + "00000000000000000000000001000000", "00000000000000000000000010000000", "00000000000000000000000100000000", + "00000000000000000000001000000000", "00000000000000000000010000000000", "00000000000000000000100000000000", + "00000000000000000001000000000000", "00000000000000000010000000000000", "00000000000000000100000000000000", + "00000000000000001000000000000000", "00000000000000010000000000000000", "00000000000000100000000000000000", + "00000000000001000000000000000000", "00000000000010000000000000000000", "00000000000100000000000000000000", + "00000000001000000000000000000000", "00000000010000000000000000000000", "00000000100000000000000000000000", + "00000001000000000000000000000000", "00000010000000000000000000000000", "00000100000000000000000000000000", + "00001000000000000000000000000000", "00010000000000000000000000000000", "00100000000000000000000000000000", + "01000000000000000000000000000000", "10000000000000000000000000000000" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- The component is a ROM. + -- There is no Write side. + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_775.vhd b/testsuite/gna/bug040/cmp_775.vhd new file mode 100644 index 000000000..f6f8279d4 --- /dev/null +++ b/testsuite/gna/bug040/cmp_775.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_775 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_775; + +architecture augh of cmp_775 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_779.vhd b/testsuite/gna/bug040/cmp_779.vhd new file mode 100644 index 000000000..d65be5113 --- /dev/null +++ b/testsuite/gna/bug040/cmp_779.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_779 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_779; + +architecture augh of cmp_779 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_780.vhd b/testsuite/gna/bug040/cmp_780.vhd new file mode 100644 index 000000000..a54a3aca8 --- /dev/null +++ b/testsuite/gna/bug040/cmp_780.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_780 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_780; + +architecture augh of cmp_780 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_787.vhd b/testsuite/gna/bug040/cmp_787.vhd new file mode 100644 index 000000000..117475299 --- /dev/null +++ b/testsuite/gna/bug040/cmp_787.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_787 is + port ( + eq : out std_logic; + in1 : in std_logic; + in0 : in std_logic + ); +end cmp_787; + +architecture augh of cmp_787 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_788.vhd b/testsuite/gna/bug040/cmp_788.vhd new file mode 100644 index 000000000..0f7853e7a --- /dev/null +++ b/testsuite/gna/bug040/cmp_788.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_788 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(2 downto 0); + in0 : in std_logic_vector(2 downto 0) + ); +end cmp_788; + +architecture augh of cmp_788 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_790.vhd b/testsuite/gna/bug040/cmp_790.vhd new file mode 100644 index 000000000..b724b9862 --- /dev/null +++ b/testsuite/gna/bug040/cmp_790.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_790 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(3 downto 0); + in0 : in std_logic_vector(3 downto 0) + ); +end cmp_790; + +architecture augh of cmp_790 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_791.vhd b/testsuite/gna/bug040/cmp_791.vhd new file mode 100644 index 000000000..e442eb06a --- /dev/null +++ b/testsuite/gna/bug040/cmp_791.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_791 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_791; + +architecture augh of cmp_791 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_792.vhd b/testsuite/gna/bug040/cmp_792.vhd new file mode 100644 index 000000000..41a6b9216 --- /dev/null +++ b/testsuite/gna/bug040/cmp_792.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_792 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_792; + +architecture augh of cmp_792 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_793.vhd b/testsuite/gna/bug040/cmp_793.vhd new file mode 100644 index 000000000..74d51d9d0 --- /dev/null +++ b/testsuite/gna/bug040/cmp_793.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_793 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_793; + +architecture augh of cmp_793 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_794.vhd b/testsuite/gna/bug040/cmp_794.vhd new file mode 100644 index 000000000..b608fd157 --- /dev/null +++ b/testsuite/gna/bug040/cmp_794.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_794 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_794; + +architecture augh of cmp_794 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_799.vhd b/testsuite/gna/bug040/cmp_799.vhd new file mode 100644 index 000000000..76a0e2c7c --- /dev/null +++ b/testsuite/gna/bug040/cmp_799.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_799 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_799; + +architecture augh of cmp_799 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_800.vhd b/testsuite/gna/bug040/cmp_800.vhd new file mode 100644 index 000000000..ce70200f3 --- /dev/null +++ b/testsuite/gna/bug040/cmp_800.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_800 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_800; + +architecture augh of cmp_800 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_804.vhd b/testsuite/gna/bug040/cmp_804.vhd new file mode 100644 index 000000000..885d672ae --- /dev/null +++ b/testsuite/gna/bug040/cmp_804.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_804 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_804; + +architecture augh of cmp_804 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_846.vhd b/testsuite/gna/bug040/cmp_846.vhd new file mode 100644 index 000000000..09ad2ff58 --- /dev/null +++ b/testsuite/gna/bug040/cmp_846.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_846 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_846; + +architecture augh of cmp_846 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_847.vhd b/testsuite/gna/bug040/cmp_847.vhd new file mode 100644 index 000000000..bb2b2cfca --- /dev/null +++ b/testsuite/gna/bug040/cmp_847.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_847 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_847; + +architecture augh of cmp_847 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_848.vhd b/testsuite/gna/bug040/cmp_848.vhd new file mode 100644 index 000000000..bf313d81d --- /dev/null +++ b/testsuite/gna/bug040/cmp_848.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_848 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_848; + +architecture augh of cmp_848 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_849.vhd b/testsuite/gna/bug040/cmp_849.vhd new file mode 100644 index 000000000..60717e3c0 --- /dev/null +++ b/testsuite/gna/bug040/cmp_849.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_849 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_849; + +architecture augh of cmp_849 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_850.vhd b/testsuite/gna/bug040/cmp_850.vhd new file mode 100644 index 000000000..d8c1744f3 --- /dev/null +++ b/testsuite/gna/bug040/cmp_850.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_850 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_850; + +architecture augh of cmp_850 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_851.vhd b/testsuite/gna/bug040/cmp_851.vhd new file mode 100644 index 000000000..14a8cb088 --- /dev/null +++ b/testsuite/gna/bug040/cmp_851.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_851 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_851; + +architecture augh of cmp_851 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_852.vhd b/testsuite/gna/bug040/cmp_852.vhd new file mode 100644 index 000000000..353410e41 --- /dev/null +++ b/testsuite/gna/bug040/cmp_852.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_852 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_852; + +architecture augh of cmp_852 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_855.vhd b/testsuite/gna/bug040/cmp_855.vhd new file mode 100644 index 000000000..9060c456d --- /dev/null +++ b/testsuite/gna/bug040/cmp_855.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_855 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_855; + +architecture augh of cmp_855 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_861.vhd b/testsuite/gna/bug040/cmp_861.vhd new file mode 100644 index 000000000..08041ae1f --- /dev/null +++ b/testsuite/gna/bug040/cmp_861.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_861 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_861; + +architecture augh of cmp_861 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_863.vhd b/testsuite/gna/bug040/cmp_863.vhd new file mode 100644 index 000000000..15b7e5878 --- /dev/null +++ b/testsuite/gna/bug040/cmp_863.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_863 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(2 downto 0); + in0 : in std_logic_vector(2 downto 0) + ); +end cmp_863; + +architecture augh of cmp_863 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_865.vhd b/testsuite/gna/bug040/cmp_865.vhd new file mode 100644 index 000000000..a29ab68b6 --- /dev/null +++ b/testsuite/gna/bug040/cmp_865.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_865 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(2 downto 0); + in0 : in std_logic_vector(2 downto 0) + ); +end cmp_865; + +architecture augh of cmp_865 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_868.vhd b/testsuite/gna/bug040/cmp_868.vhd new file mode 100644 index 000000000..2c9fc418b --- /dev/null +++ b/testsuite/gna/bug040/cmp_868.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_868 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(23 downto 0); + in0 : in std_logic_vector(23 downto 0) + ); +end cmp_868; + +architecture augh of cmp_868 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_869.vhd b/testsuite/gna/bug040/cmp_869.vhd new file mode 100644 index 000000000..7b875b1cc --- /dev/null +++ b/testsuite/gna/bug040/cmp_869.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_869 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(7 downto 0); + in0 : in std_logic_vector(7 downto 0) + ); +end cmp_869; + +architecture augh of cmp_869 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_871.vhd b/testsuite/gna/bug040/cmp_871.vhd new file mode 100644 index 000000000..6907c612e --- /dev/null +++ b/testsuite/gna/bug040/cmp_871.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_871 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_871; + +architecture augh of cmp_871 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_873.vhd b/testsuite/gna/bug040/cmp_873.vhd new file mode 100644 index 000000000..5d6b683d6 --- /dev/null +++ b/testsuite/gna/bug040/cmp_873.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_873 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(7 downto 0); + in0 : in std_logic_vector(7 downto 0) + ); +end cmp_873; + +architecture augh of cmp_873 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_877.vhd b/testsuite/gna/bug040/cmp_877.vhd new file mode 100644 index 000000000..fa9ff87b9 --- /dev/null +++ b/testsuite/gna/bug040/cmp_877.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_877 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_877; + +architecture augh of cmp_877 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_878.vhd b/testsuite/gna/bug040/cmp_878.vhd new file mode 100644 index 000000000..498d8a396 --- /dev/null +++ b/testsuite/gna/bug040/cmp_878.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_878 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_878; + +architecture augh of cmp_878 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_879.vhd b/testsuite/gna/bug040/cmp_879.vhd new file mode 100644 index 000000000..6a9edcb01 --- /dev/null +++ b/testsuite/gna/bug040/cmp_879.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_879 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_879; + +architecture augh of cmp_879 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_880.vhd b/testsuite/gna/bug040/cmp_880.vhd new file mode 100644 index 000000000..1ec7f5c1f --- /dev/null +++ b/testsuite/gna/bug040/cmp_880.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_880 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_880; + +architecture augh of cmp_880 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_882.vhd b/testsuite/gna/bug040/cmp_882.vhd new file mode 100644 index 000000000..d33165a83 --- /dev/null +++ b/testsuite/gna/bug040/cmp_882.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_882 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_882; + +architecture augh of cmp_882 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_885.vhd b/testsuite/gna/bug040/cmp_885.vhd new file mode 100644 index 000000000..bb202ca0a --- /dev/null +++ b/testsuite/gna/bug040/cmp_885.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_885 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_885; + +architecture augh of cmp_885 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_887.vhd b/testsuite/gna/bug040/cmp_887.vhd new file mode 100644 index 000000000..bfab0e377 --- /dev/null +++ b/testsuite/gna/bug040/cmp_887.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_887 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_887; + +architecture augh of cmp_887 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_962.vhd b/testsuite/gna/bug040/cmp_962.vhd new file mode 100644 index 000000000..1f56e5e0a --- /dev/null +++ b/testsuite/gna/bug040/cmp_962.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_962 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_962; + +architecture augh of cmp_962 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_964.vhd b/testsuite/gna/bug040/cmp_964.vhd new file mode 100644 index 000000000..d8a03a0f5 --- /dev/null +++ b/testsuite/gna/bug040/cmp_964.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_964 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_964; + +architecture augh of cmp_964 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_971.vhd b/testsuite/gna/bug040/cmp_971.vhd new file mode 100644 index 000000000..2b63b4726 --- /dev/null +++ b/testsuite/gna/bug040/cmp_971.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_971 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_971; + +architecture augh of cmp_971 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_972.vhd b/testsuite/gna/bug040/cmp_972.vhd new file mode 100644 index 000000000..23158220d --- /dev/null +++ b/testsuite/gna/bug040/cmp_972.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_972 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_972; + +architecture augh of cmp_972 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_973.vhd b/testsuite/gna/bug040/cmp_973.vhd new file mode 100644 index 000000000..b9c616d4b --- /dev/null +++ b/testsuite/gna/bug040/cmp_973.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_973 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_973; + +architecture augh of cmp_973 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_974.vhd b/testsuite/gna/bug040/cmp_974.vhd new file mode 100644 index 000000000..6b807c46a --- /dev/null +++ b/testsuite/gna/bug040/cmp_974.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_974 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_974; + +architecture augh of cmp_974 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_975.vhd b/testsuite/gna/bug040/cmp_975.vhd new file mode 100644 index 000000000..1dd29b182 --- /dev/null +++ b/testsuite/gna/bug040/cmp_975.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_975 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_975; + +architecture augh of cmp_975 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_977.vhd b/testsuite/gna/bug040/cmp_977.vhd new file mode 100644 index 000000000..c0a069f4a --- /dev/null +++ b/testsuite/gna/bug040/cmp_977.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_977 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_977; + +architecture augh of cmp_977 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/cmp_978.vhd b/testsuite/gna/bug040/cmp_978.vhd new file mode 100644 index 000000000..293fa1f4e --- /dev/null +++ b/testsuite/gna/bug040/cmp_978.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_978 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_978; + +architecture augh of cmp_978 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_979.vhd b/testsuite/gna/bug040/cmp_979.vhd new file mode 100644 index 000000000..4b0d4954b --- /dev/null +++ b/testsuite/gna/bug040/cmp_979.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_979 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_979; + +architecture augh of cmp_979 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + ne <= not(tmp); + +end architecture; diff --git a/testsuite/gna/bug040/cmp_985.vhd b/testsuite/gna/bug040/cmp_985.vhd new file mode 100644 index 000000000..943f296ae --- /dev/null +++ b/testsuite/gna/bug040/cmp_985.vhd @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity cmp_985 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); +end cmp_985; + +architecture augh of cmp_985 is + + signal tmp : std_logic; + +begin + + -- Compute the result + tmp <= + '0' when in1 /= in0 else + '1'; + + -- Set the outputs + eq <= tmp; + +end architecture; diff --git a/testsuite/gna/bug040/extend_mask.vhd b/testsuite/gna/bug040/extend_mask.vhd new file mode 100644 index 000000000..36122ab8b --- /dev/null +++ b/testsuite/gna/bug040/extend_mask.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity extend_mask is + port ( + clk : in std_logic; + ra0_addr : in std_logic_vector(4 downto 0); + ra0_data : out std_logic_vector(20 downto 0) + ); +end extend_mask; +architecture augh of extend_mask is + + -- Embedded RAM + + type ram_type is array (0 to 19) of std_logic_vector(20 downto 0); + signal ram : ram_type := ( + "111111111111111111110", "111111111111111111100", "111111111111111111000", "111111111111111110000", + "111111111111111100000", "111111111111111000000", "111111111111110000000", "111111111111100000000", + "111111111111000000000", "111111111110000000000", "111111111100000000000", "111111111000000000000", + "111111110000000000000", "111111100000000000000", "111111000000000000000", "111110000000000000000", + "111100000000000000000", "111000000000000000000", "110000000000000000000", "100000000000000000000" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- The component is a ROM. + -- There is no Write side. + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 20 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/fsm_224.vhd b/testsuite/gna/bug040/fsm_224.vhd new file mode 100644 index 000000000..d4d2e7986 --- /dev/null +++ b/testsuite/gna/bug040/fsm_224.vhd @@ -0,0 +1,3028 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity fsm_224 is + port ( + clock : in std_logic; + reset : in std_logic; + out40 : out std_logic; + in2 : in std_logic; + in11 : in std_logic; + out146 : out std_logic; + out148 : out std_logic; + out150 : out std_logic; + out152 : out std_logic; + in12 : in std_logic; + out153 : out std_logic; + out154 : out std_logic; + in13 : in std_logic; + out156 : out std_logic; + out157 : out std_logic; + out160 : out std_logic; + out162 : out std_logic; + out165 : out std_logic; + out170 : out std_logic; + out171 : out std_logic; + out173 : out std_logic; + out175 : out std_logic; + out177 : out std_logic; + out180 : out std_logic; + out184 : out std_logic; + in14 : in std_logic; + out186 : out std_logic; + out189 : out std_logic; + out191 : out std_logic; + out192 : out std_logic; + out193 : out std_logic; + out197 : out std_logic; + out199 : out std_logic; + out201 : out std_logic; + out202 : out std_logic; + out205 : out std_logic; + out207 : out std_logic; + out208 : out std_logic; + out209 : out std_logic; + out210 : out std_logic; + out212 : out std_logic; + out213 : out std_logic; + in15 : in std_logic; + out221 : out std_logic; + out222 : out std_logic; + out224 : out std_logic; + out225 : out std_logic; + out228 : out std_logic; + out229 : out std_logic; + out230 : out std_logic; + out231 : out std_logic; + out99 : out std_logic; + in6 : in std_logic; + out92 : out std_logic; + out232 : out std_logic; + in16 : in std_logic; + out234 : out std_logic; + out236 : out std_logic; + out239 : out std_logic; + out240 : out std_logic; + out241 : out std_logic; + out245 : out std_logic; + out246 : out std_logic; + out247 : out std_logic; + out251 : out std_logic; + out252 : out std_logic; + out253 : out std_logic; + out255 : out std_logic; + out256 : out std_logic; + out258 : out std_logic; + out259 : out std_logic; + in17 : in std_logic; + out263 : out std_logic; + out264 : out std_logic; + out266 : out std_logic; + in18 : in std_logic; + out267 : out std_logic; + out268 : out std_logic; + out270 : out std_logic; + out273 : out std_logic; + out275 : out std_logic; + out276 : out std_logic; + in19 : in std_logic; + out279 : out std_logic; + in20 : in std_logic; + out281 : out std_logic; + out282 : out std_logic; + in21 : in std_logic; + out283 : out std_logic; + out286 : out std_logic; + out289 : out std_logic; + out296 : out std_logic; + out297 : out std_logic; + out299 : out std_logic; + out300 : out std_logic; + out304 : out std_logic; + out305 : out std_logic; + in22 : in std_logic; + out306 : out std_logic; + out310 : out std_logic; + out311 : out std_logic; + out313 : out std_logic; + out314 : out std_logic; + in23 : in std_logic; + out316 : out std_logic; + out317 : out std_logic; + out320 : out std_logic; + out322 : out std_logic; + out324 : out std_logic; + out325 : out std_logic; + out326 : out std_logic; + out328 : out std_logic; + out332 : out std_logic; + out333 : out std_logic; + out334 : out std_logic; + out335 : out std_logic; + out338 : out std_logic; + out339 : out std_logic; + out341 : out std_logic; + out342 : out std_logic; + out344 : out std_logic; + out93 : out std_logic; + out98 : out std_logic; + out85 : out std_logic; + out87 : out std_logic; + out88 : out std_logic; + out80 : out std_logic; + out82 : out std_logic; + out83 : out std_logic; + out84 : out std_logic; + in5 : in std_logic; + out77 : out std_logic; + out78 : out std_logic; + out71 : out std_logic; + out72 : out std_logic; + in4 : in std_logic; + out65 : out std_logic; + out67 : out std_logic; + out60 : out std_logic; + out64 : out std_logic; + in3 : in std_logic; + out59 : out std_logic; + out53 : out std_logic; + out55 : out std_logic; + out49 : out std_logic; + out44 : out std_logic; + out104 : out std_logic; + out107 : out std_logic; + out111 : out std_logic; + out112 : out std_logic; + out114 : out std_logic; + in7 : in std_logic; + out117 : out std_logic; + out119 : out std_logic; + out122 : out std_logic; + in8 : in std_logic; + out128 : out std_logic; + in9 : in std_logic; + out129 : out std_logic; + out130 : out std_logic; + out133 : out std_logic; + out134 : out std_logic; + out136 : out std_logic; + out137 : out std_logic; + in10 : in std_logic; + out139 : out std_logic; + out143 : out std_logic; + out144 : out std_logic; + out32 : out std_logic; + out35 : out std_logic; + out27 : out std_logic; + out25 : out std_logic; + out26 : out std_logic; + in1 : in std_logic; + out15 : out std_logic; + out16 : out std_logic; + out11 : out std_logic; + out13 : out std_logic; + out14 : out std_logic; + out7 : out std_logic; + out1 : out std_logic; + out2 : out std_logic; + out3 : out std_logic; + out4 : out std_logic; + in0 : in std_logic; + in24 : in std_logic; + out346 : out std_logic; + out347 : out std_logic; + out348 : out std_logic; + out349 : out std_logic; + in25 : in std_logic; + out350 : out std_logic; + out351 : out std_logic; + out355 : out std_logic; + out356 : out std_logic; + out357 : out std_logic; + out358 : out std_logic; + out360 : out std_logic; + out362 : out std_logic; + out363 : out std_logic; + out364 : out std_logic; + out365 : out std_logic; + out366 : out std_logic; + out370 : out std_logic; + out371 : out std_logic; + out372 : out std_logic; + out373 : out std_logic; + out375 : out std_logic; + in26 : in std_logic; + out376 : out std_logic; + out378 : out std_logic; + out379 : out std_logic; + out381 : out std_logic; + out382 : out std_logic; + in27 : in std_logic; + out384 : out std_logic; + in28 : in std_logic; + out391 : out std_logic; + out395 : out std_logic; + out396 : out std_logic; + out401 : out std_logic; + out402 : out std_logic; + out403 : out std_logic; + out404 : out std_logic; + out405 : out std_logic; + out407 : out std_logic; + out408 : out std_logic; + out409 : out std_logic; + out410 : out std_logic; + in29 : in std_logic; + out412 : out std_logic; + out414 : out std_logic; + out415 : out std_logic; + out417 : out std_logic; + out418 : out std_logic; + out419 : out std_logic; + out420 : out std_logic; + out422 : out std_logic; + out424 : out std_logic; + out425 : out std_logic; + out426 : out std_logic; + in30 : in std_logic; + out428 : out std_logic; + out429 : out std_logic; + out432 : out std_logic; + out433 : out std_logic; + out434 : out std_logic; + out437 : out std_logic; + out440 : out std_logic; + out441 : out std_logic; + in31 : in std_logic; + out443 : out std_logic; + in32 : in std_logic; + out445 : out std_logic; + out447 : out std_logic; + out448 : out std_logic; + out450 : out std_logic; + in33 : in std_logic; + out453 : out std_logic; + out455 : out std_logic; + out458 : out std_logic; + in34 : in std_logic; + out462 : out std_logic; + out464 : out std_logic; + out467 : out std_logic; + out468 : out std_logic; + out472 : out std_logic; + in35 : in std_logic; + out478 : out std_logic; + out479 : out std_logic; + out480 : out std_logic; + out487 : out std_logic; + out488 : out std_logic; + in36 : in std_logic; + out491 : out std_logic; + out496 : out std_logic; + out497 : out std_logic; + out498 : out std_logic; + out500 : out std_logic; + out504 : out std_logic; + out505 : out std_logic; + in37 : in std_logic; + out506 : out std_logic; + out508 : out std_logic; + in38 : in std_logic; + out510 : out std_logic; + out513 : out std_logic; + out514 : out std_logic; + out515 : out std_logic; + out517 : out std_logic; + out519 : out std_logic; + in39 : in std_logic; + out523 : out std_logic; + out526 : out std_logic; + out527 : out std_logic; + out528 : out std_logic; + out530 : out std_logic; + out531 : out std_logic; + out533 : out std_logic; + out534 : out std_logic; + out537 : out std_logic; + out538 : out std_logic; + out549 : out std_logic; + out558 : out std_logic; + out559 : out std_logic; + out561 : out std_logic; + in40 : in std_logic; + out566 : out std_logic; + out567 : out std_logic; + out568 : out std_logic; + out569 : out std_logic; + out570 : out std_logic; + out572 : out std_logic; + out574 : out std_logic; + out575 : out std_logic; + out577 : out std_logic; + in41 : in std_logic; + out578 : out std_logic; + out581 : out std_logic; + out589 : out std_logic; + out590 : out std_logic; + out595 : out std_logic; + out597 : out std_logic; + out599 : out std_logic; + out601 : out std_logic; + out602 : out std_logic; + out607 : out std_logic; + out610 : out std_logic; + out612 : out std_logic; + in42 : in std_logic; + out614 : out std_logic; + out621 : out std_logic; + out628 : out std_logic; + out635 : out std_logic; + out636 : out std_logic; + out638 : out std_logic; + out640 : out std_logic; + out643 : out std_logic; + out646 : out std_logic; + out649 : out std_logic; + out651 : out std_logic; + out656 : out std_logic; + in43 : in std_logic; + out658 : out std_logic; + out659 : out std_logic; + out661 : out std_logic; + out663 : out std_logic; + out664 : out std_logic; + in44 : in std_logic; + out667 : out std_logic; + out668 : out std_logic; + out670 : out std_logic; + out672 : out std_logic; + out674 : out std_logic; + in45 : in std_logic; + out679 : out std_logic; + out681 : out std_logic; + out683 : out std_logic; + out686 : out std_logic; + out688 : out std_logic; + out690 : out std_logic; + out692 : out std_logic; + out694 : out std_logic; + out696 : out std_logic; + out697 : out std_logic; + out698 : out std_logic; + out699 : out std_logic; + out700 : out std_logic; + out703 : out std_logic; + out704 : out std_logic; + out706 : out std_logic; + out708 : out std_logic; + out710 : out std_logic; + out712 : out std_logic; + out715 : out std_logic; + out718 : out std_logic; + in46 : in std_logic; + out722 : out std_logic; + out724 : out std_logic; + out726 : out std_logic; + out728 : out std_logic; + out731 : out std_logic; + out733 : out std_logic; + out734 : out std_logic; + out737 : out std_logic; + out739 : out std_logic; + out740 : out std_logic; + out743 : out std_logic; + out745 : out std_logic; + out746 : out std_logic; + in47 : in std_logic; + out749 : out std_logic; + out753 : out std_logic; + out755 : out std_logic; + out759 : out std_logic; + in48 : in std_logic; + out762 : out std_logic; + out764 : out std_logic; + out765 : out std_logic; + out767 : out std_logic; + out768 : out std_logic; + in49 : in std_logic; + out772 : out std_logic; + in50 : in std_logic; + out775 : out std_logic; + out776 : out std_logic; + out778 : out std_logic; + out783 : out std_logic; + out784 : out std_logic; + out787 : out std_logic; + out791 : out std_logic; + in51 : in std_logic; + out794 : out std_logic; + out795 : out std_logic; + in52 : in std_logic; + out799 : out std_logic; + out802 : out std_logic; + out806 : out std_logic; + out809 : out std_logic; + out812 : out std_logic; + out815 : out std_logic; + out826 : out std_logic; + out828 : out std_logic; + in53 : in std_logic; + in54 : in std_logic; + out843 : out std_logic; + out848 : out std_logic; + out852 : out std_logic; + in55 : in std_logic; + out855 : out std_logic; + out858 : out std_logic; + in56 : in std_logic; + out860 : out std_logic; + out861 : out std_logic; + out863 : out std_logic; + out866 : out std_logic; + out872 : out std_logic; + in57 : in std_logic; + out874 : out std_logic; + out876 : out std_logic; + out879 : out std_logic; + out882 : out std_logic; + out886 : out std_logic; + out887 : out std_logic; + in58 : in std_logic; + out888 : out std_logic; + out892 : out std_logic; + out894 : out std_logic; + out895 : out std_logic; + out896 : out std_logic; + out901 : out std_logic; + out902 : out std_logic; + out903 : out std_logic; + out905 : out std_logic; + out907 : out std_logic; + out918 : out std_logic; + out920 : out std_logic; + out921 : out std_logic; + out923 : out std_logic; + out925 : out std_logic; + out928 : out std_logic; + out929 : out std_logic; + out931 : out std_logic; + out933 : out std_logic; + out936 : out std_logic; + out937 : out std_logic; + out938 : out std_logic; + out939 : out std_logic; + out942 : out std_logic; + out943 : out std_logic; + out944 : out std_logic; + out947 : out std_logic; + out948 : out std_logic; + out949 : out std_logic; + out951 : out std_logic; + in59 : in std_logic; + out952 : out std_logic; + out953 : out std_logic; + out955 : out std_logic; + out956 : out std_logic; + out957 : out std_logic; + out958 : out std_logic; + in60 : in std_logic; + in61 : in std_logic; + out962 : out std_logic; + out963 : out std_logic; + out972 : out std_logic; + out973 : out std_logic; + out974 : out std_logic; + in62 : in std_logic; + out978 : out std_logic; + out979 : out std_logic; + out981 : out std_logic; + out982 : out std_logic; + out985 : out std_logic; + out986 : out std_logic; + out989 : out std_logic; + in63 : in std_logic; + in64 : in std_logic; + in65 : in std_logic; + in66 : in std_logic; + in67 : in std_logic; + in68 : in std_logic; + in69 : in std_logic; + in70 : in std_logic; + in71 : in std_logic; + in72 : in std_logic; + in73 : in std_logic; + in74 : in std_logic; + in75 : in std_logic; + in76 : in std_logic; + in77 : in std_logic; + in78 : in std_logic; + out990 : out std_logic; + out991 : out std_logic; + out993 : out std_logic; + out994 : out std_logic; + out996 : out std_logic; + out997 : out std_logic; + out998 : out std_logic; + out999 : out std_logic; + out1000 : out std_logic; + out1002 : out std_logic; + out1003 : out std_logic; + out1005 : out std_logic; + out1006 : out std_logic; + out1007 : out std_logic; + out1009 : out std_logic; + out1011 : out std_logic; + out1012 : out std_logic; + out1013 : out std_logic; + out1014 : out std_logic; + out1015 : out std_logic; + out1016 : out std_logic; + out1018 : out std_logic; + out1019 : out std_logic; + out1021 : out std_logic; + out1022 : out std_logic; + out1024 : out std_logic; + out1026 : out std_logic; + out1027 : out std_logic; + out1029 : out std_logic; + out1030 : out std_logic; + out1032 : out std_logic; + out1033 : out std_logic; + out1035 : out std_logic; + out1036 : out std_logic; + out1037 : out std_logic; + out1057 : out std_logic; + out1068 : out std_logic; + out1069 : out std_logic; + out1070 : out std_logic; + out1072 : out std_logic; + out1073 : out std_logic; + out1075 : out std_logic; + out1078 : out std_logic; + out1080 : out std_logic; + out1082 : out std_logic; + out1083 : out std_logic; + out1084 : out std_logic; + out1085 : out std_logic; + out1088 : out std_logic; + out1089 : out std_logic; + out1091 : out std_logic; + out1092 : out std_logic; + out1094 : out std_logic; + out1096 : out std_logic; + out1098 : out std_logic; + out1101 : out std_logic; + out1104 : out std_logic; + out1107 : out std_logic; + out1109 : out std_logic; + out1111 : out std_logic; + out1114 : out std_logic; + out1119 : out std_logic; + out1121 : out std_logic; + out1125 : out std_logic; + out1126 : out std_logic; + out1128 : out std_logic; + out1131 : out std_logic; + out1134 : out std_logic; + out1137 : out std_logic; + out1139 : out std_logic; + out1141 : out std_logic; + out1145 : out std_logic; + out1146 : out std_logic; + out1147 : out std_logic; + out1150 : out std_logic; + out1151 : out std_logic; + out1152 : out std_logic; + out1155 : out std_logic; + out1158 : out std_logic; + out1160 : out std_logic; + out1164 : out std_logic; + out1166 : out std_logic; + out1169 : out std_logic; + out1171 : out std_logic; + out1174 : out std_logic; + out1175 : out std_logic; + out1176 : out std_logic; + out1180 : out std_logic; + out1181 : out std_logic; + out1182 : out std_logic; + out1185 : out std_logic; + out1186 : out std_logic; + out1187 : out std_logic; + out1190 : out std_logic; + out1213 : out std_logic; + out1215 : out std_logic; + out1217 : out std_logic; + out1220 : out std_logic; + out1221 : out std_logic; + out1223 : out std_logic; + out1228 : out std_logic; + out1229 : out std_logic; + out1231 : out std_logic; + out1235 : out std_logic; + out1236 : out std_logic; + out1240 : out std_logic; + out1243 : out std_logic; + out1250 : out std_logic; + out1252 : out std_logic; + out1253 : out std_logic; + out1258 : out std_logic; + out1262 : out std_logic; + out1266 : out std_logic; + out1269 : out std_logic; + out1275 : out std_logic; + out1278 : out std_logic; + out1279 : out std_logic; + out1284 : out std_logic; + out1286 : out std_logic; + out1287 : out std_logic; + out1289 : out std_logic; + out1290 : out std_logic; + out1292 : out std_logic; + out1293 : out std_logic; + out1295 : out std_logic; + out1298 : out std_logic; + out1301 : out std_logic; + out1302 : out std_logic; + out1303 : out std_logic; + out1308 : out std_logic; + out1309 : out std_logic; + out1311 : out std_logic; + out1318 : out std_logic; + out1319 : out std_logic; + out1320 : out std_logic; + out1323 : out std_logic; + out1324 : out std_logic; + out1326 : out std_logic; + out1327 : out std_logic; + out1329 : out std_logic; + out1337 : out std_logic; + out1339 : out std_logic; + out1340 : out std_logic; + out1341 : out std_logic; + out1344 : out std_logic; + out1346 : out std_logic; + out1349 : out std_logic; + out1353 : out std_logic; + out1356 : out std_logic; + out1362 : out std_logic; + out1363 : out std_logic; + out1364 : out std_logic; + out1365 : out std_logic; + out1366 : out std_logic; + out1368 : out std_logic; + out1370 : out std_logic; + out1375 : out std_logic; + out1378 : out std_logic; + out1381 : out std_logic; + out1383 : out std_logic; + out1387 : out std_logic + ); +end fsm_224; + +architecture augh of fsm_224 is + + signal state_cur : std_logic_vector(0 to 473) := (457 => '1', others => '0'); + signal state_next : std_logic_vector(0 to 473) := (457 => '1', others => '0'); + + -- Buffers for outputs + signal out1057_buf : std_logic := '0'; + signal out1057_bufn : std_logic; + signal out59_buf : std_logic := '0'; + signal out59_bufn : std_logic; + signal out447_buf : std_logic := '0'; + signal out447_bufn : std_logic; + signal out157_buf : std_logic := '0'; + signal out157_bufn : std_logic; + signal out450_buf : std_logic := '0'; + signal out450_bufn : std_logic; + signal out1012_buf : std_logic := '0'; + signal out1012_bufn : std_logic; + signal out1072_buf : std_logic := '0'; + signal out1072_bufn : std_logic; + signal out999_buf : std_logic := '0'; + signal out999_bufn : std_logic; + signal out437_buf : std_logic := '0'; + signal out437_bufn : std_logic; + signal out415_buf : std_logic := '0'; + signal out415_bufn : std_logic; + signal out426_buf : std_logic := '0'; + signal out426_bufn : std_logic; + signal out375_buf : std_logic := '0'; + signal out375_bufn : std_logic; + signal out704_buf : std_logic := '0'; + signal out704_bufn : std_logic; + signal out973_buf : std_logic := '0'; + signal out973_bufn : std_logic; + signal out11_buf : std_logic := '0'; + signal out11_bufn : std_logic; + signal out549_buf : std_logic := '0'; + signal out549_bufn : std_logic; + signal out453_buf : std_logic := '0'; + signal out453_bufn : std_logic; + signal out1231_buf : std_logic := '0'; + signal out1231_bufn : std_logic; + signal out87_buf : std_logic := '0'; + signal out87_bufn : std_logic; + signal out401_buf : std_logic := '0'; + signal out401_bufn : std_logic; + signal out990_buf : std_logic := '0'; + signal out990_bufn : std_logic; + signal out378_buf : std_logic := '0'; + signal out378_bufn : std_logic; + signal out1302_buf : std_logic := '0'; + signal out1302_bufn : std_logic; + signal out27_buf : std_logic := '0'; + signal out27_bufn : std_logic; + signal out569_buf : std_logic := '0'; + signal out569_bufn : std_logic; + signal out1030_buf : std_logic := '0'; + signal out1030_bufn : std_logic; + signal out537_buf : std_logic := '0'; + signal out537_bufn : std_logic; + signal out77_buf : std_logic := '0'; + signal out77_bufn : std_logic; + signal out1318_buf : std_logic := '0'; + signal out1318_bufn : std_logic; + signal out533_buf : std_logic := '0'; + signal out533_bufn : std_logic; + signal out32_buf : std_logic := '0'; + signal out32_bufn : std_logic; + signal out1027_buf : std_logic := '0'; + signal out1027_bufn : std_logic; + signal out599_buf : std_logic := '0'; + signal out599_bufn : std_logic; + signal out668_buf : std_logic := '0'; + signal out668_bufn : std_logic; + signal out568_buf : std_logic := '0'; + signal out568_bufn : std_logic; + signal out225_buf : std_logic := '0'; + signal out225_bufn : std_logic; + signal out700_buf : std_logic := '0'; + signal out700_bufn : std_logic; + signal out638_buf : std_logic := '0'; + signal out638_bufn : std_logic; + signal out670_buf : std_logic := '0'; + signal out670_bufn : std_logic; + signal out433_buf : std_logic := '0'; + signal out433_bufn : std_logic; + signal out896_buf : std_logic := '0'; + signal out896_bufn : std_logic; + signal out575_buf : std_logic := '0'; + signal out575_bufn : std_logic; + signal out428_buf : std_logic := '0'; + signal out428_bufn : std_logic; + signal out72_buf : std_logic := '0'; + signal out72_bufn : std_logic; + signal out404_buf : std_logic := '0'; + signal out404_bufn : std_logic; + signal out98_buf : std_logic := '0'; + signal out98_bufn : std_logic; + signal out67_buf : std_logic := '0'; + signal out67_bufn : std_logic; + signal out635_buf : std_logic := '0'; + signal out635_bufn : std_logic; + signal out381_buf : std_logic := '0'; + signal out381_bufn : std_logic; + signal out222_buf : std_logic := '0'; + signal out222_bufn : std_logic; + signal out339_buf : std_logic := '0'; + signal out339_bufn : std_logic; + signal out268_buf : std_logic := '0'; + signal out268_bufn : std_logic; + signal out419_buf : std_logic := '0'; + signal out419_bufn : std_logic; + signal out559_buf : std_logic := '0'; + signal out559_bufn : std_logic; + signal out1002_buf : std_logic := '0'; + signal out1002_bufn : std_logic; + signal out1006_buf : std_logic := '0'; + signal out1006_bufn : std_logic; + signal out276_buf : std_logic := '0'; + signal out276_bufn : std_logic; + signal out205_buf : std_logic := '0'; + signal out205_bufn : std_logic; + signal out943_buf : std_logic := '0'; + signal out943_bufn : std_logic; + signal out1080_buf : std_logic := '0'; + signal out1080_bufn : std_logic; + signal out408_buf : std_logic := '0'; + signal out408_bufn : std_logic; + signal out252_buf : std_logic := '0'; + signal out252_bufn : std_logic; + signal out71_buf : std_logic := '0'; + signal out71_bufn : std_logic; + signal out672_buf : std_logic := '0'; + signal out672_bufn : std_logic; + signal out357_buf : std_logic := '0'; + signal out357_bufn : std_logic; + signal out441_buf : std_logic := '0'; + signal out441_bufn : std_logic; + signal out1084_buf : std_logic := '0'; + signal out1084_bufn : std_logic; + signal out144_buf : std_logic := '0'; + signal out144_bufn : std_logic; + signal out574_buf : std_logic := '0'; + signal out574_bufn : std_logic; + signal out210_buf : std_logic := '0'; + signal out210_bufn : std_logic; + signal out128_buf : std_logic := '0'; + signal out128_bufn : std_logic; + signal out360_buf : std_logic := '0'; + signal out360_bufn : std_logic; + signal out948_buf : std_logic := '0'; + signal out948_bufn : std_logic; + signal out506_buf : std_logic := '0'; + signal out506_bufn : std_logic; + signal out207_buf : std_logic := '0'; + signal out207_bufn : std_logic; + signal out1083_buf : std_logic := '0'; + signal out1083_bufn : std_logic; + signal out491_buf : std_logic := '0'; + signal out491_bufn : std_logic; + signal out4_buf : std_logic := '0'; + signal out4_bufn : std_logic; + signal out784_buf : std_logic := '0'; + signal out784_bufn : std_logic; + signal out3_buf : std_logic := '0'; + signal out3_bufn : std_logic; + signal out746_buf : std_logic := '0'; + signal out746_bufn : std_logic; + signal out528_buf : std_logic := '0'; + signal out528_bufn : std_logic; + signal out372_buf : std_logic := '0'; + signal out372_bufn : std_logic; + signal out418_buf : std_logic := '0'; + signal out418_bufn : std_logic; + signal out708_buf : std_logic := '0'; + signal out708_bufn : std_logic; + signal out706_buf : std_logic := '0'; + signal out706_bufn : std_logic; + signal out445_buf : std_logic := '0'; + signal out445_bufn : std_logic; + signal out1021_buf : std_logic := '0'; + signal out1021_bufn : std_logic; + signal out405_buf : std_logic := '0'; + signal out405_bufn : std_logic; + signal out764_buf : std_logic := '0'; + signal out764_bufn : std_logic; + signal out581_buf : std_logic := '0'; + signal out581_bufn : std_logic; + signal out776_buf : std_logic := '0'; + signal out776_bufn : std_logic; + signal out213_buf : std_logic := '0'; + signal out213_bufn : std_logic; + signal out674_buf : std_logic := '0'; + signal out674_bufn : std_logic; + signal out1326_buf : std_logic := '0'; + signal out1326_bufn : std_logic; + signal out334_buf : std_logic := '0'; + signal out334_bufn : std_logic; + signal out843_buf : std_logic := '0'; + signal out843_bufn : std_logic; + signal out175_buf : std_logic := '0'; + signal out175_bufn : std_logic; + signal out1036_buf : std_logic := '0'; + signal out1036_bufn : std_logic; + signal out1015_buf : std_logic := '0'; + signal out1015_bufn : std_logic; + signal out236_buf : std_logic := '0'; + signal out236_bufn : std_logic; + signal out395_buf : std_logic := '0'; + signal out395_bufn : std_logic; + signal out1340_buf : std_logic := '0'; + signal out1340_bufn : std_logic; + signal out993_buf : std_logic := '0'; + signal out993_bufn : std_logic; + signal out356_buf : std_logic := '0'; + signal out356_bufn : std_logic; + signal out273_buf : std_logic := '0'; + signal out273_bufn : std_logic; + signal out403_buf : std_logic := '0'; + signal out403_bufn : std_logic; + signal out286_buf : std_logic := '0'; + signal out286_bufn : std_logic; + signal out364_buf : std_logic := '0'; + signal out364_bufn : std_logic; + signal out697_buf : std_logic := '0'; + signal out697_bufn : std_logic; + signal out283_buf : std_logic := '0'; + signal out283_bufn : std_logic; + signal out282_buf : std_logic := '0'; + signal out282_bufn : std_logic; + signal out1319_buf : std_logic := '0'; + signal out1319_bufn : std_logic; + signal out409_buf : std_logic := '0'; + signal out409_bufn : std_logic; + signal out1092_buf : std_logic := '0'; + signal out1092_bufn : std_logic; + signal out1075_buf : std_logic := '0'; + signal out1075_bufn : std_logic; + signal out925_buf : std_logic := '0'; + signal out925_bufn : std_logic; + signal out78_buf : std_logic := '0'; + signal out78_bufn : std_logic; + signal out1089_buf : std_logic := '0'; + signal out1089_bufn : std_logic; + signal out362_buf : std_logic := '0'; + signal out362_bufn : std_logic; + signal out982_buf : std_logic := '0'; + signal out982_bufn : std_logic; + signal out979_buf : std_logic := '0'; + signal out979_bufn : std_logic; + signal out952_buf : std_logic := '0'; + signal out952_bufn : std_logic; + signal out1109_buf : std_logic := '0'; + signal out1109_bufn : std_logic; + signal out16_buf : std_logic := '0'; + signal out16_bufn : std_logic; + signal out703_buf : std_logic := '0'; + signal out703_bufn : std_logic; + signal out371_buf : std_logic := '0'; + signal out371_bufn : std_logic; + signal out956_buf : std_logic := '0'; + signal out956_bufn : std_logic; + signal out1107_buf : std_logic := '0'; + signal out1107_bufn : std_logic; + signal out1033_buf : std_logic := '0'; + signal out1033_bufn : std_logic; + signal out148_buf : std_logic := '0'; + signal out148_bufn : std_logic; + signal out351_buf : std_logic := '0'; + signal out351_bufn : std_logic; + signal out740_buf : std_logic := '0'; + signal out740_bufn : std_logic; + signal out391_buf : std_logic := '0'; + signal out391_bufn : std_logic; + signal out129_buf : std_logic := '0'; + signal out129_bufn : std_logic; + signal out338_buf : std_logic := '0'; + signal out338_bufn : std_logic; + signal out425_buf : std_logic := '0'; + signal out425_bufn : std_logic; + signal out1078_buf : std_logic := '0'; + signal out1078_bufn : std_logic; + signal out349_buf : std_logic := '0'; + signal out349_bufn : std_logic; + signal out590_buf : std_logic := '0'; + signal out590_bufn : std_logic; + signal out325_buf : std_logic := '0'; + signal out325_bufn : std_logic; + signal out112_buf : std_logic := '0'; + signal out112_bufn : std_logic; + signal out224_buf : std_logic := '0'; + signal out224_bufn : std_logic; + signal out1220_buf : std_logic := '0'; + signal out1220_bufn : std_logic; + signal out1250_buf : std_logic := '0'; + signal out1250_bufn : std_logic; + signal out365_buf : std_logic := '0'; + signal out365_bufn : std_logic; + signal out699_buf : std_logic := '0'; + signal out699_bufn : std_logic; + signal out488_buf : std_logic := '0'; + signal out488_bufn : std_logic; + signal out1069_buf : std_logic := '0'; + signal out1069_bufn : std_logic; + signal out530_buf : std_logic := '0'; + signal out530_bufn : std_logic; + signal out326_buf : std_logic := '0'; + signal out326_bufn : std_logic; + signal out602_buf : std_logic := '0'; + signal out602_bufn : std_logic; + signal out83_buf : std_logic := '0'; + signal out83_bufn : std_logic; + signal out311_buf : std_logic := '0'; + signal out311_bufn : std_logic; + signal out253_buf : std_logic := '0'; + signal out253_bufn : std_logic; + signal out209_buf : std_logic := '0'; + signal out209_bufn : std_logic; + signal out1240_buf : std_logic := '0'; + signal out1240_bufn : std_logic; + signal out1018_buf : std_logic := '0'; + signal out1018_bufn : std_logic; + signal out1152_buf : std_logic := '0'; + signal out1152_bufn : std_logic; + signal out1236_buf : std_logic := '0'; + signal out1236_bufn : std_logic; + signal out130_buf : std_logic := '0'; + signal out130_bufn : std_logic; + signal out567_buf : std_logic := '0'; + signal out567_bufn : std_logic; + signal out646_buf : std_logic := '0'; + signal out646_bufn : std_logic; + + -- Function calls: return IDs + signal funccall0 : natural range 0 to 18 := 0; + signal funccall0_next : natural range 0 to 18 := 0; + signal funccall1 : natural range 0 to 6 := 0; + signal funccall1_next : natural range 0 to 6 := 0; + signal funccall2 : natural range 0 to 2 := 0; + signal funccall2_next : natural range 0 to 2 := 0; + signal funccall3 : natural range 0 to 3 := 0; + signal funccall3_next : natural range 0 to 3 := 0; + signal funccall4 : natural range 0 to 1 := 0; + signal funccall4_next : natural range 0 to 1 := 0; + signal funccall5 : natural range 0 to 1 := 0; + signal funccall5_next : natural range 0 to 1 := 0; + signal funccall6 : natural range 0 to 1 := 0; + signal funccall6_next : natural range 0 to 1 := 0; + signal funccall7 : natural range 0 to 4 := 0; + signal funccall7_next : natural range 0 to 4 := 0; + signal funccall8 : natural range 0 to 1 := 0; + signal funccall8_next : natural range 0 to 1 := 0; + signal funccall9 : natural range 0 to 3 := 0; + signal funccall9_next : natural range 0 to 3 := 0; + + -- A utility function to convert bool to std_logic + function to_stdl (b: boolean) return std_logic is + begin + if b = true then + return '1'; + end if; + return '0'; + end function; + +begin + + -- Sequential process + -- Set the current state + + process (clock) + begin + if rising_edge(clock) then + + -- Next state + state_cur <= state_next; + -- Buffers for outputs + out1057_buf <= out1057_bufn; + out59_buf <= out59_bufn; + out447_buf <= out447_bufn; + out157_buf <= out157_bufn; + out450_buf <= out450_bufn; + out1012_buf <= out1012_bufn; + out1072_buf <= out1072_bufn; + out999_buf <= out999_bufn; + out437_buf <= out437_bufn; + out415_buf <= out415_bufn; + out426_buf <= out426_bufn; + out375_buf <= out375_bufn; + out704_buf <= out704_bufn; + out973_buf <= out973_bufn; + out11_buf <= out11_bufn; + out549_buf <= out549_bufn; + out453_buf <= out453_bufn; + out1231_buf <= out1231_bufn; + out87_buf <= out87_bufn; + out401_buf <= out401_bufn; + out990_buf <= out990_bufn; + out378_buf <= out378_bufn; + out1302_buf <= out1302_bufn; + out27_buf <= out27_bufn; + out569_buf <= out569_bufn; + out1030_buf <= out1030_bufn; + out537_buf <= out537_bufn; + out77_buf <= out77_bufn; + out1318_buf <= out1318_bufn; + out533_buf <= out533_bufn; + out32_buf <= out32_bufn; + out1027_buf <= out1027_bufn; + out599_buf <= out599_bufn; + out668_buf <= out668_bufn; + out568_buf <= out568_bufn; + out225_buf <= out225_bufn; + out700_buf <= out700_bufn; + out638_buf <= out638_bufn; + out670_buf <= out670_bufn; + out433_buf <= out433_bufn; + out896_buf <= out896_bufn; + out575_buf <= out575_bufn; + out428_buf <= out428_bufn; + out72_buf <= out72_bufn; + out404_buf <= out404_bufn; + out98_buf <= out98_bufn; + out67_buf <= out67_bufn; + out635_buf <= out635_bufn; + out381_buf <= out381_bufn; + out222_buf <= out222_bufn; + out339_buf <= out339_bufn; + out268_buf <= out268_bufn; + out419_buf <= out419_bufn; + out559_buf <= out559_bufn; + out1002_buf <= out1002_bufn; + out1006_buf <= out1006_bufn; + out276_buf <= out276_bufn; + out205_buf <= out205_bufn; + out943_buf <= out943_bufn; + out1080_buf <= out1080_bufn; + out408_buf <= out408_bufn; + out252_buf <= out252_bufn; + out71_buf <= out71_bufn; + out672_buf <= out672_bufn; + out357_buf <= out357_bufn; + out441_buf <= out441_bufn; + out1084_buf <= out1084_bufn; + out144_buf <= out144_bufn; + out574_buf <= out574_bufn; + out210_buf <= out210_bufn; + out128_buf <= out128_bufn; + out360_buf <= out360_bufn; + out948_buf <= out948_bufn; + out506_buf <= out506_bufn; + out207_buf <= out207_bufn; + out1083_buf <= out1083_bufn; + out491_buf <= out491_bufn; + out4_buf <= out4_bufn; + out784_buf <= out784_bufn; + out3_buf <= out3_bufn; + out746_buf <= out746_bufn; + out528_buf <= out528_bufn; + out372_buf <= out372_bufn; + out418_buf <= out418_bufn; + out708_buf <= out708_bufn; + out706_buf <= out706_bufn; + out445_buf <= out445_bufn; + out1021_buf <= out1021_bufn; + out405_buf <= out405_bufn; + out764_buf <= out764_bufn; + out581_buf <= out581_bufn; + out776_buf <= out776_bufn; + out213_buf <= out213_bufn; + out674_buf <= out674_bufn; + out1326_buf <= out1326_bufn; + out334_buf <= out334_bufn; + out843_buf <= out843_bufn; + out175_buf <= out175_bufn; + out1036_buf <= out1036_bufn; + out1015_buf <= out1015_bufn; + out236_buf <= out236_bufn; + out395_buf <= out395_bufn; + out1340_buf <= out1340_bufn; + out993_buf <= out993_bufn; + out356_buf <= out356_bufn; + out273_buf <= out273_bufn; + out403_buf <= out403_bufn; + out286_buf <= out286_bufn; + out364_buf <= out364_bufn; + out697_buf <= out697_bufn; + out283_buf <= out283_bufn; + out282_buf <= out282_bufn; + out1319_buf <= out1319_bufn; + out409_buf <= out409_bufn; + out1092_buf <= out1092_bufn; + out1075_buf <= out1075_bufn; + out925_buf <= out925_bufn; + out78_buf <= out78_bufn; + out1089_buf <= out1089_bufn; + out362_buf <= out362_bufn; + out982_buf <= out982_bufn; + out979_buf <= out979_bufn; + out952_buf <= out952_bufn; + out1109_buf <= out1109_bufn; + out16_buf <= out16_bufn; + out703_buf <= out703_bufn; + out371_buf <= out371_bufn; + out956_buf <= out956_bufn; + out1107_buf <= out1107_bufn; + out1033_buf <= out1033_bufn; + out148_buf <= out148_bufn; + out351_buf <= out351_bufn; + out740_buf <= out740_bufn; + out391_buf <= out391_bufn; + out129_buf <= out129_bufn; + out338_buf <= out338_bufn; + out425_buf <= out425_bufn; + out1078_buf <= out1078_bufn; + out349_buf <= out349_bufn; + out590_buf <= out590_bufn; + out325_buf <= out325_bufn; + out112_buf <= out112_bufn; + out224_buf <= out224_bufn; + out1220_buf <= out1220_bufn; + out1250_buf <= out1250_bufn; + out365_buf <= out365_bufn; + out699_buf <= out699_bufn; + out488_buf <= out488_bufn; + out1069_buf <= out1069_bufn; + out530_buf <= out530_bufn; + out326_buf <= out326_bufn; + out602_buf <= out602_bufn; + out83_buf <= out83_bufn; + out311_buf <= out311_bufn; + out253_buf <= out253_bufn; + out209_buf <= out209_bufn; + out1240_buf <= out1240_bufn; + out1018_buf <= out1018_bufn; + out1152_buf <= out1152_bufn; + out1236_buf <= out1236_bufn; + out130_buf <= out130_bufn; + out567_buf <= out567_bufn; + out646_buf <= out646_bufn; + -- Function calls: return IDs + funccall0 <= funccall0_next; + funccall1 <= funccall1_next; + funccall2 <= funccall2_next; + funccall3 <= funccall3_next; + funccall4 <= funccall4_next; + funccall5 <= funccall5_next; + funccall6 <= funccall6_next; + funccall7 <= funccall7_next; + funccall8 <= funccall8_next; + funccall9 <= funccall9_next; + + end if; + end process; + + -- Function calls: The call IDs + + -- Function 'read_byte' + funccall0_next <= + 0 when ( state_cur(130) and in33 ) = '1' else + 2 when ( state_cur(130) and not ( in33 ) ) = '1' else + 18 when ( state_cur(137) and not ( in34 ) ) = '1' else + 17 when ( state_cur(148) and in36 ) = '1' else + 16 when ( state_cur(160) and in38 ) = '1' else + 15 when ( state_cur(170) and in39 ) = '1' else + 14 when ( state_cur(179) and in40 ) = '1' else + 10 when ( state_cur(207) and to_stdl(funccall1 = 3) ) = '1' else + 5 when ( state_cur(207) and to_stdl(funccall1 = 0) ) = '1' else + 12 when state_cur(211) = '1' else + 11 when ( state_cur(212) and in43 ) = '1' else + 9 when state_cur(237) = '1' else + 8 when state_cur(238) = '1' else + 7 when state_cur(242) = '1' else + 6 when state_cur(243) = '1' else + 2 when ( state_cur(246) and not ( in46 ) ) = '1' else + 3 when ( state_cur(249) and in47 ) = '1' else + 4 when ( state_cur(249) and not ( in47 ) ) = '1' else + 4 when ( state_cur(251) and in48 ) = '1' else + 13 when ( state_cur(338) and in52 ) = '1' else + 1 when ( state_cur(396) and to_stdl(funccall0 = 0) ) = '1' else + funccall0; + -- Function 'read_word' + funccall1_next <= + 5 when ( state_cur(126) and not ( in32 ) and in31 ) = '1' else + 4 when ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) = '1' else + 3 when ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) = '1' else + 0 when ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) = '1' else + 6 when ( state_cur(137) and in34 ) = '1' else + 2 when state_cur(244) = '1' else + 1 when ( state_cur(396) and to_stdl(funccall0 = 5) ) = '1' else + funccall1; + -- Function 'pgetc' + funccall2_next <= + 1 when state_cur(72) = '1' else + 2 when ( state_cur(73) and not ( in20 ) ) = '1' else + 0 when ( state_cur(78) and in23 ) = '1' else + funccall2; + -- Function 'buf_getb' + funccall3_next <= + 0 when state_cur(15) = '1' else + 3 when ( state_cur(25) and in6 ) = '1' else + 1 when ( state_cur(30) and in8 ) = '1' else + 2 when state_cur(270) = '1' else + funccall3; + -- Function 'buf_getv' + funccall4_next <= + 0 when state_cur(254) = '1' else + 1 when state_cur(256) = '1' else + funccall4; + -- Function 'huff_make_dhuff_tb_ac' + funccall5_next <= + 0 when state_cur(259) = '1' else + 1 when state_cur(260) = '1' else + funccall5; + -- Function 'huff_make_dhuff_tb_dc' + funccall6_next <= + 1 when state_cur(258) = '1' else + 0 when state_cur(333) = '1' else + funccall6; + -- Function 'WriteOneBlock' + funccall7_next <= + 1 when state_cur(257) = '1' else + 2 when state_cur(445) = '1' else + 3 when state_cur(461) = '1' else + 4 when state_cur(462) = '1' else + 0 when state_cur(469) = '1' else + funccall7; + -- Function 'YuvToRgb' + funccall8_next <= + 0 when state_cur(468) = '1' else + 1 when state_cur(472) = '1' else + funccall8; + -- Function 'decode_block' + funccall9_next <= + 0 when state_cur(418) = '1' else + 1 when state_cur(458) = '1' else + 2 when state_cur(470) = '1' else + 3 when state_cur(471) = '1' else + funccall9; + + -- Next state bits + + state_next(0) <= (not reset) and ( ( state_cur(422) and in65 ) ); + state_next(1) <= (not reset) and ( state_cur(385) ); + state_next(2) <= (not reset) and ( state_cur(8) or state_cur(3) ); + state_next(3) <= (not reset) and ( ( state_cur(2) and in0 ) ); + state_next(4) <= (not reset) and ( state_cur(377) ); + state_next(5) <= (not reset) and ( ( state_cur(6) and in1 ) ); + state_next(6) <= (not reset) and ( ( state_cur(424) and not ( in67 ) ) ); + state_next(7) <= (not reset) and ( ( state_cur(252) and not ( in49 ) ) or state_cur(202) ); + state_next(8) <= (not reset) and ( ( state_cur(460) and in78 ) or ( state_cur(13) and not ( in2 ) ) or ( state_cur(6) and not ( in1 ) ) ); + state_next(9) <= (not reset) and ( state_cur(327) ); + state_next(10) <= (not reset) and ( state_cur(140) ); + state_next(11) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 16) ) ); + state_next(12) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 15) ) ); + state_next(13) <= (not reset) and ( state_cur(14) or state_cur(7) or state_cur(5) ); + state_next(14) <= (not reset) and ( ( state_cur(17) and not ( in3 ) ) ); + state_next(15) <= (not reset) and ( ( state_cur(13) and in2 ) ); + state_next(16) <= (not reset) and ( ( state_cur(82) and in24 ) ); + state_next(17) <= (not reset) and ( state_cur(19) or state_cur(18) ); + state_next(18) <= (not reset) and ( state_cur(466) or ( state_cur(23) and not ( in4 ) ) ); + state_next(19) <= (not reset) and ( ( state_cur(17) and in3 ) ); + state_next(20) <= (not reset) and ( ( state_cur(454) and in76 ) ); + state_next(21) <= (not reset) and ( ( state_cur(121) and in26 ) ); + state_next(22) <= (not reset) and ( ( state_cur(24) and not ( in5 ) ) ); + state_next(23) <= (not reset) and ( state_cur(159) or state_cur(22) ); + state_next(24) <= (not reset) and ( ( state_cur(25) and not ( in6 ) ) ); + state_next(25) <= (not reset) and ( state_cur(28) or state_cur(26) ); + state_next(26) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 3) ) or ( state_cur(75) and to_stdl(funccall3 = 3) ) ); + state_next(27) <= (not reset) and ( ( state_cur(29) and not ( in7 ) ) ); + state_next(28) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 2) ) or ( state_cur(75) and to_stdl(funccall3 = 2) ) ); + state_next(29) <= (not reset) and ( ( state_cur(30) and not ( in8 ) ) ); + state_next(30) <= (not reset) and ( state_cur(32) or state_cur(31) ); + state_next(31) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 1) ) or ( state_cur(75) and to_stdl(funccall3 = 1) ) ); + state_next(32) <= (not reset) and ( ( state_cur(77) and to_stdl(funccall3 = 0) ) or ( state_cur(75) and to_stdl(funccall3 = 0) ) ); + state_next(33) <= (not reset) and ( state_cur(369) ); + state_next(34) <= (not reset) and ( state_cur(188) or state_cur(38) ); + state_next(35) <= (not reset) and ( ( state_cur(40) and not ( in10 ) ) ); + state_next(36) <= (not reset) and ( state_cur(444) ); + state_next(37) <= (not reset) and ( state_cur(328) ); + state_next(38) <= (not reset) and ( ( state_cur(39) and in9 ) ); + state_next(39) <= (not reset) and ( ( state_cur(40) and in10 ) ); + state_next(40) <= (not reset) and ( state_cur(42) or state_cur(34) ); + state_next(41) <= (not reset) and ( ( state_cur(53) and not ( in14 ) ) ); + state_next(42) <= (not reset) and ( ( state_cur(43) and in11 ) ); + state_next(43) <= (not reset) and ( ( state_cur(427) and not ( in68 ) ) ); + state_next(44) <= (not reset) and ( ( state_cur(45) and not ( in12 ) ) ); + state_next(45) <= (not reset) and ( state_cur(48) or state_cur(46) ); + state_next(46) <= (not reset) and ( ( state_cur(47) and in13 ) ); + state_next(47) <= (not reset) and ( state_cur(49) or state_cur(44) ); + state_next(48) <= (not reset) and ( ( state_cur(45) and in12 ) ); + state_next(49) <= (not reset) and ( ( state_cur(333) ) or ( state_cur(258) ) ); + state_next(50) <= (not reset) and ( state_cur(430) or state_cur(52) ); + state_next(51) <= (not reset) and ( ( state_cur(54) and not ( in15 ) ) ); + state_next(52) <= (not reset) and ( ( state_cur(53) and in14 ) ); + state_next(53) <= (not reset) and ( ( state_cur(54) and in15 ) ); + state_next(54) <= (not reset) and ( state_cur(57) or state_cur(50) ); + state_next(55) <= (not reset) and ( state_cur(372) ); + state_next(56) <= (not reset) and ( state_cur(266) ); + state_next(57) <= (not reset) and ( ( state_cur(59) and in16 ) ); + state_next(58) <= (not reset) and ( state_cur(56) ); + state_next(59) <= (not reset) and ( ( state_cur(366) and not ( in53 ) ) ); + state_next(60) <= (not reset) and ( state_cur(350) ); + state_next(61) <= (not reset) and ( ( state_cur(471) ) or ( state_cur(470) ) or ( state_cur(458) ) or ( state_cur(418) ) ); + state_next(62) <= (not reset) and ( state_cur(208) ); + state_next(63) <= (not reset) and ( ( state_cur(64) and not ( in17 ) ) ); + state_next(64) <= (not reset) and ( state_cur(67) or state_cur(65) ); + state_next(65) <= (not reset) and ( ( state_cur(66) and in18 ) ); + state_next(66) <= (not reset) and ( state_cur(68) or state_cur(63) ); + state_next(67) <= (not reset) and ( ( state_cur(64) and in17 ) ); + state_next(68) <= (not reset) and ( ( state_cur(260) ) or ( state_cur(259) ) ); + state_next(69) <= (not reset) and ( ( state_cur(74) and not ( in21 ) ) ); + state_next(70) <= (not reset) and ( ( state_cur(69) and in19 ) ); + state_next(71) <= (not reset) and ( ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) ) ); + state_next(72) <= (not reset) and ( ( state_cur(73) and in20 ) ); + state_next(73) <= (not reset) and ( ( state_cur(74) and in21 ) ); + state_next(74) <= (not reset) and ( state_cur(432) or state_cur(71) ); + state_next(75) <= (not reset) and ( ( state_cur(76) and not ( in22 ) ) ); + state_next(76) <= (not reset) and ( state_cur(81) or ( state_cur(78) and not ( in23 ) ) ); + state_next(77) <= (not reset) and ( ( state_cur(76) and in22 ) ); + state_next(78) <= (not reset) and ( ( state_cur(270) ) or ( state_cur(30) and in8 ) or ( state_cur(25) and in6 ) or ( state_cur(15) ) ); + state_next(79) <= (not reset) and ( ( state_cur(454) and not ( in76 ) ) or ( state_cur(240) and in44 ) ); + state_next(80) <= (not reset) and ( ( state_cur(240) and not ( in44 ) ) ); + state_next(81) <= (not reset) and ( ( state_cur(80) and to_stdl(funccall2 = 0) ) or ( state_cur(79) and to_stdl(funccall2 = 0) ) ); + state_next(82) <= (not reset) and ( state_cur(83) or state_cur(16) ); + state_next(83) <= (not reset) and ( ( state_cur(105) and not ( in25 ) ) ); + state_next(84) <= (not reset) and ( state_cur(302) ); + state_next(85) <= (not reset) and ( state_cur(282) ); + state_next(86) <= (not reset) and ( state_cur(388) ); + state_next(87) <= (not reset) and ( state_cur(122) ); + state_next(88) <= (not reset) and ( state_cur(112) ); + state_next(89) <= (not reset) and ( state_cur(283) ); + state_next(90) <= (not reset) and ( state_cur(89) ); + state_next(91) <= (not reset) and ( state_cur(315) ); + state_next(92) <= (not reset) and ( state_cur(292) ); + state_next(93) <= (not reset) and ( state_cur(99) ); + state_next(94) <= (not reset) and ( state_cur(93) ); + state_next(95) <= (not reset) and ( state_cur(306) ); + state_next(96) <= (not reset) and ( state_cur(317) ); + state_next(97) <= (not reset) and ( state_cur(295) ); + state_next(98) <= (not reset) and ( state_cur(296) ); + state_next(99) <= (not reset) and ( state_cur(290) ); + state_next(100) <= (not reset) and ( state_cur(98) ); + state_next(101) <= (not reset) and ( state_cur(299) ); + state_next(102) <= (not reset) and ( state_cur(106) ); + state_next(103) <= (not reset) and ( state_cur(102) ); + state_next(104) <= (not reset) and ( state_cur(300) ); + state_next(105) <= (not reset) and ( state_cur(224) or state_cur(107) ); + state_next(106) <= (not reset) and ( state_cur(104) ); + state_next(107) <= (not reset) and ( ( state_cur(121) and not ( in26 ) ) ); + state_next(108) <= (not reset) and ( state_cur(307) ); + state_next(109) <= (not reset) and ( state_cur(436) ); + state_next(110) <= (not reset) and ( state_cur(172) ); + state_next(111) <= (not reset) and ( state_cur(314) ); + state_next(112) <= (not reset) and ( state_cur(199) ); + state_next(113) <= (not reset) and ( state_cur(303) ); + state_next(114) <= (not reset) and ( state_cur(111) ); + state_next(115) <= (not reset) and ( state_cur(96) ); + state_next(116) <= (not reset) and ( state_cur(380) ); + state_next(117) <= (not reset) and ( state_cur(345) ); + state_next(118) <= (not reset) and ( state_cur(347) ); + state_next(119) <= (not reset) and ( state_cur(337) ); + state_next(120) <= (not reset) and ( state_cur(180) ); + state_next(121) <= (not reset) and ( state_cur(321) or state_cur(223) ); + state_next(122) <= (not reset) and ( state_cur(183) ); + state_next(123) <= (not reset) and ( ( state_cur(80) and to_stdl(funccall2 = 1) ) or ( state_cur(79) and to_stdl(funccall2 = 1) ) ); + state_next(124) <= (not reset) and ( state_cur(354) ); + state_next(125) <= (not reset) and ( ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and not ( in28 ) and in27 ) ); + state_next(126) <= (not reset) and ( state_cur(129) or state_cur(128) ); + state_next(127) <= (not reset) and ( state_cur(171) ); + state_next(128) <= (not reset) and ( state_cur(245) ); + state_next(129) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 1) ) ); + state_next(130) <= (not reset) and ( state_cur(234) or ( state_cur(179) and not ( in40 ) ) or ( state_cur(148) and not ( in36 ) ) or state_cur(134) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and not ( in28 ) and not ( in27 ) ) or state_cur(125) ); + state_next(131) <= (not reset) and ( state_cur(273) ); + state_next(132) <= (not reset) and ( ( state_cur(157) and in37 ) ); + state_next(133) <= (not reset) and ( ( state_cur(453) and to_stdl(funccall4 = 0) ) or ( state_cur(131) and to_stdl(funccall4 = 0) ) or ( state_cur(70) and to_stdl(funccall4 = 0) ) ); + state_next(134) <= (not reset) and ( ( state_cur(423) and not ( in66 ) ) ); + state_next(135) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 18) ) ); + state_next(136) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 6) ) ); + state_next(137) <= (not reset) and ( ( state_cur(138) and in35 ) ); + state_next(138) <= (not reset) and ( state_cur(161) or state_cur(139) ); + state_next(139) <= (not reset) and ( state_cur(136) or state_cur(135) ); + state_next(140) <= (not reset) and ( state_cur(21) ); + state_next(141) <= (not reset) and ( state_cur(331) ); + state_next(142) <= (not reset) and ( state_cur(332) ); + state_next(143) <= (not reset) and ( state_cur(463) ); + state_next(144) <= (not reset) and ( state_cur(9) ); + state_next(145) <= (not reset) and ( state_cur(110) ); + state_next(146) <= (not reset) and ( state_cur(465) ); + state_next(147) <= (not reset) and ( state_cur(10) ); + state_next(148) <= (not reset) and ( state_cur(214) or state_cur(152) ); + state_next(149) <= (not reset) and ( state_cur(319) ); + state_next(150) <= (not reset) and ( state_cur(119) ); + state_next(151) <= (not reset) and ( state_cur(166) ); + state_next(152) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 5) ) ); + state_next(153) <= (not reset) and ( state_cur(151) ); + state_next(154) <= (not reset) and ( ( state_cur(160) and not ( in38 ) ) ); + state_next(155) <= (not reset) and ( state_cur(341) ); + state_next(156) <= (not reset) and ( state_cur(335) ); + state_next(157) <= (not reset) and ( state_cur(133) ); + state_next(158) <= (not reset) and ( state_cur(186) or ( state_cur(126) and in32 ) ); + state_next(159) <= (not reset) and ( state_cur(167) ); + state_next(160) <= (not reset) and ( state_cur(163) or state_cur(11) ); + state_next(161) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 17) ) ); + state_next(162) <= (not reset) and ( state_cur(156) ); + state_next(163) <= (not reset) and ( ( state_cur(170) and not ( in39 ) ) ); + state_next(164) <= (not reset) and ( ( state_cur(439) and in71 ) ); + state_next(165) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) ); + state_next(166) <= (not reset) and ( state_cur(361) ); + state_next(167) <= (not reset) and ( ( state_cur(24) and in5 ) ); + state_next(168) <= (not reset) and ( ( state_cur(29) and in7 ) ); + state_next(169) <= (not reset) and ( state_cur(190) or state_cur(187) ); + state_next(170) <= (not reset) and ( state_cur(255) or state_cur(12) ); + state_next(171) <= (not reset) and ( state_cur(87) ); + state_next(172) <= (not reset) and ( state_cur(322) ); + state_next(173) <= (not reset) and ( state_cur(168) ); + state_next(174) <= (not reset) and ( ( state_cur(433) and in70 ) or ( state_cur(59) and not ( in16 ) ) ); + state_next(175) <= (not reset) and ( state_cur(456) ); + state_next(176) <= (not reset) and ( state_cur(348) ); + state_next(177) <= (not reset) and ( state_cur(192) ); + state_next(178) <= (not reset) and ( state_cur(384) ); + state_next(179) <= (not reset) and ( state_cur(184) or state_cur(154) ); + state_next(180) <= (not reset) and ( state_cur(88) ); + state_next(181) <= (not reset) and ( state_cur(455) ); + state_next(182) <= (not reset) and ( state_cur(336) ); + state_next(183) <= (not reset) and ( state_cur(124) ); + state_next(184) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 4) ) ); + state_next(185) <= (not reset) and ( state_cur(194) ); + state_next(186) <= (not reset) and ( ( state_cur(338) and not ( in52 ) ) ); + state_next(187) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 13) ) ); + state_next(188) <= (not reset) and ( state_cur(426) ); + state_next(189) <= (not reset) and ( state_cur(343) ); + state_next(190) <= (not reset) and ( ( state_cur(212) and not ( in43 ) ) ); + state_next(191) <= (not reset) and ( ( state_cur(252) and in49 ) ); + state_next(192) <= (not reset) and ( state_cur(473) ); + state_next(193) <= (not reset) and ( state_cur(362) ); + state_next(194) <= (not reset) and ( state_cur(176) ); + state_next(195) <= (not reset) and ( state_cur(360) ); + state_next(196) <= (not reset) and ( state_cur(86) ); + state_next(197) <= (not reset) and ( state_cur(55) ); + state_next(198) <= (not reset) and ( state_cur(371) ); + state_next(199) <= (not reset) and ( state_cur(118) ); + state_next(200) <= (not reset) and ( state_cur(376) ); + state_next(201) <= (not reset) and ( state_cur(204) ); + state_next(202) <= (not reset) and ( state_cur(191) ); + state_next(203) <= (not reset) and ( state_cur(359) ); + state_next(204) <= (not reset) and ( state_cur(182) ); + state_next(205) <= (not reset) and ( ( state_cur(210) and not ( in42 ) ) ); + state_next(206) <= (not reset) and ( ( state_cur(210) and in42 ) or ( state_cur(209) and not ( in41 ) ) ); + state_next(207) <= (not reset) and ( state_cur(365) ); + state_next(208) <= (not reset) and ( state_cur(344) ); + state_next(209) <= (not reset) and ( state_cur(213) or state_cur(205) ); + state_next(210) <= (not reset) and ( ( state_cur(209) and in41 ) ); + state_next(211) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 11) ) ); + state_next(212) <= (not reset) and ( state_cur(229) or state_cur(206) ); + state_next(213) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 12) ) ); + state_next(214) <= (not reset) and ( state_cur(353) ); + state_next(215) <= (not reset) and ( state_cur(62) ); + state_next(216) <= (not reset) and ( state_cur(178) ); + state_next(217) <= (not reset) and ( state_cur(389) ); + state_next(218) <= (not reset) and ( state_cur(373) ); + state_next(219) <= (not reset) and ( state_cur(340) ); + state_next(220) <= (not reset) and ( state_cur(374) ); + state_next(221) <= (not reset) and ( state_cur(346) ); + state_next(222) <= (not reset) and ( state_cur(370) ); + state_next(223) <= (not reset) and ( state_cur(367) ); + state_next(224) <= (not reset) and ( state_cur(185) ); + state_next(225) <= (not reset) and ( state_cur(226) ); + state_next(226) <= (not reset) and ( state_cur(227) ); + state_next(227) <= (not reset) and ( state_cur(218) ); + state_next(228) <= (not reset) and ( state_cur(230) ); + state_next(229) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 10) ) ); + state_next(230) <= (not reset) and ( state_cur(225) ); + state_next(231) <= (not reset) and ( state_cur(233) ); + state_next(232) <= (not reset) and ( state_cur(280) ); + state_next(233) <= (not reset) and ( state_cur(232) ); + state_next(234) <= (not reset) and ( ( state_cur(241) and not ( in45 ) ) ); + state_next(235) <= (not reset) and ( state_cur(164) ); + state_next(236) <= (not reset) and ( state_cur(165) ); + state_next(237) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 8) ) ); + state_next(238) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 7) ) ); + state_next(239) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 9) ) ); + state_next(240) <= (not reset) and ( state_cur(20) ); + state_next(241) <= (not reset) and ( state_cur(247) or state_cur(239) ); + state_next(242) <= (not reset) and ( ( state_cur(241) and in45 ) ); + state_next(243) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 2) ) ); + state_next(244) <= (not reset) and ( ( state_cur(207) and to_stdl(funccall1 = 1) ) ); + state_next(245) <= (not reset) and ( ( state_cur(246) and in46 ) ); + state_next(246) <= (not reset) and ( ( state_cur(251) and not ( in48 ) ) ); + state_next(247) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 6) ) ); + state_next(248) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 3) ) ); + state_next(249) <= (not reset) and ( state_cur(250) or state_cur(248) ); + state_next(250) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 2) ) ); + state_next(251) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 4) ) ); + state_next(252) <= (not reset) and ( state_cur(253) ); + state_next(253) <= (not reset) and ( ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) ); + state_next(254) <= (not reset) and ( ( state_cur(23) and in4 ) ); + state_next(255) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 14) ) ); + state_next(256) <= (not reset) and ( ( state_cur(460) and not ( in78 ) ) ); + state_next(257) <= (not reset) and ( ( state_cur(399) and in56 ) ); + state_next(258) <= (not reset) and ( ( state_cur(35) and to_stdl(funccall6 = 0) ) ); + state_next(259) <= (not reset) and ( ( state_cur(35) and to_stdl(funccall6 = 1) ) ); + state_next(260) <= (not reset) and ( ( state_cur(51) and to_stdl(funccall5 = 0) ) ); + state_next(261) <= (not reset) and ( ( state_cur(51) and to_stdl(funccall5 = 1) ) ); + state_next(262) <= (not reset) and ( state_cur(391) or ( state_cur(262) and not (in50) ) ); + state_next(263) <= (not reset) and ( ( state_cur(392) and not ( in55 ) ) or ( state_cur(263) and not (in50) ) ); + state_next(264) <= (not reset) and ( state_cur(386) or ( state_cur(264) and not (in50) ) ); + state_next(265) <= (not reset) and ( ( state_cur(423) and in66 ) or state_cur(397) or ( state_cur(265) and not (in51) ) ); + state_next(266) <= (not reset) and ( state_cur(85) ); + state_next(267) <= (not reset) and ( state_cur(58) ); + state_next(268) <= (not reset) and ( state_cur(267) ); + state_next(269) <= (not reset) and ( state_cur(268) ); + state_next(270) <= (not reset) and ( state_cur(61) ); + state_next(271) <= (not reset) and ( ( state_cur(256) ) or ( state_cur(254) ) ); + state_next(272) <= (not reset) and ( state_cur(198) ); + state_next(273) <= (not reset) and ( ( state_cur(69) and not ( in19 ) ) ); + state_next(274) <= (not reset) and ( state_cur(272) ); + state_next(275) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) ); + state_next(276) <= (not reset) and ( state_cur(275) ); + state_next(277) <= (not reset) and ( state_cur(269) ); + state_next(278) <= (not reset) and ( state_cur(277) ); + state_next(279) <= (not reset) and ( state_cur(274) ); + state_next(280) <= (not reset) and ( state_cur(279) ); + state_next(281) <= (not reset) and ( state_cur(84) ); + state_next(282) <= (not reset) and ( state_cur(281) ); + state_next(283) <= (not reset) and ( state_cur(92) ); + state_next(284) <= (not reset) and ( state_cur(90) ); + state_next(285) <= (not reset) and ( state_cur(284) ); + state_next(286) <= (not reset) and ( state_cur(285) ); + state_next(287) <= (not reset) and ( state_cur(286) ); + state_next(288) <= (not reset) and ( state_cur(287) ); + state_next(289) <= (not reset) and ( state_cur(288) ); + state_next(290) <= (not reset) and ( state_cur(289) ); + state_next(291) <= (not reset) and ( state_cur(91) ); + state_next(292) <= (not reset) and ( state_cur(291) ); + state_next(293) <= (not reset) and ( state_cur(94) ); + state_next(294) <= (not reset) and ( state_cur(293) ); + state_next(295) <= (not reset) and ( state_cur(294) ); + state_next(296) <= (not reset) and ( state_cur(97) ); + state_next(297) <= (not reset) and ( state_cur(100) ); + state_next(298) <= (not reset) and ( state_cur(297) ); + state_next(299) <= (not reset) and ( state_cur(298) ); + state_next(300) <= (not reset) and ( state_cur(101) ); + state_next(301) <= (not reset) and ( state_cur(103) ); + state_next(302) <= (not reset) and ( state_cur(301) ); + state_next(303) <= (not reset) and ( state_cur(357) ); + state_next(304) <= (not reset) and ( state_cur(434) ); + state_next(305) <= (not reset) and ( state_cur(425) ); + state_next(306) <= (not reset) and ( state_cur(305) ); + state_next(307) <= (not reset) and ( state_cur(304) ); + state_next(308) <= (not reset) and ( state_cur(108) ); + state_next(309) <= (not reset) and ( state_cur(308) ); + state_next(310) <= (not reset) and ( state_cur(95) ); + state_next(311) <= (not reset) and ( state_cur(310) ); + state_next(312) <= (not reset) and ( state_cur(311) ); + state_next(313) <= (not reset) and ( state_cur(309) ); + state_next(314) <= (not reset) and ( state_cur(313) ); + state_next(315) <= (not reset) and ( state_cur(114) ); + state_next(316) <= (not reset) and ( state_cur(318) ); + state_next(317) <= (not reset) and ( state_cur(312) ); + state_next(318) <= (not reset) and ( state_cur(329) ); + state_next(319) <= (not reset) and ( state_cur(316) ); + state_next(320) <= (not reset) and ( state_cur(326) ); + state_next(321) <= (not reset) and ( state_cur(115) ); + state_next(322) <= (not reset) and ( state_cur(320) ); + state_next(323) <= (not reset) and ( state_cur(330) ); + state_next(324) <= (not reset) and ( ( state_cur(78) and in23 ) or ( state_cur(73) and not ( in20 ) ) or ( state_cur(72) ) ); + state_next(325) <= (not reset) and ( state_cur(323) ); + state_next(326) <= (not reset) and ( state_cur(325) ); + state_next(327) <= (not reset) and ( state_cur(155) ); + state_next(328) <= (not reset) and ( state_cur(145) ); + state_next(329) <= (not reset) and ( state_cur(141) ); + state_next(330) <= (not reset) and ( state_cur(142) ); + state_next(331) <= (not reset) and ( state_cur(113) ); + state_next(332) <= (not reset) and ( state_cur(438) ); + state_next(333) <= (not reset) and ( state_cur(158) ); + state_next(334) <= (not reset) and ( state_cur(197) ); + state_next(335) <= (not reset) and ( state_cur(189) ); + state_next(336) <= (not reset) and ( state_cur(203) ); + state_next(337) <= (not reset) and ( state_cur(358) ); + state_next(338) <= (not reset) and ( state_cur(169) ); + state_next(339) <= (not reset) and ( state_cur(349) ); + state_next(340) <= (not reset) and ( state_cur(177) ); + state_next(341) <= (not reset) and ( state_cur(339) ); + state_next(342) <= (not reset) and ( state_cur(382) ); + state_next(343) <= (not reset) and ( state_cur(150) ); + state_next(344) <= (not reset) and ( state_cur(442) ); + state_next(345) <= (not reset) and ( state_cur(400) ); + state_next(346) <= (not reset) and ( state_cur(200) ); + state_next(347) <= (not reset) and ( state_cur(162) ); + state_next(348) <= (not reset) and ( state_cur(193) ); + state_next(349) <= (not reset) and ( state_cur(219) ); + state_next(350) <= (not reset) and ( state_cur(37) ); + state_next(351) <= (not reset) and ( state_cur(404) ); + state_next(352) <= (not reset) and ( state_cur(1) ); + state_next(353) <= (not reset) and ( ( state_cur(138) and not ( in35 ) ) ); + state_next(354) <= (not reset) and ( ( state_cur(105) and in25 ) ); + state_next(355) <= (not reset) and ( state_cur(175) ); + state_next(356) <= (not reset) and ( state_cur(4) ); + state_next(357) <= (not reset) and ( ( state_cur(82) and not ( in24 ) ) ); + state_next(358) <= (not reset) and ( state_cur(117) ); + state_next(359) <= (not reset) and ( state_cur(352) ); + state_next(360) <= (not reset) and ( state_cur(368) ); + state_next(361) <= (not reset) and ( state_cur(33) ); + state_next(362) <= (not reset) and ( state_cur(356) ); + state_next(363) <= (not reset) and ( ( state_cur(451) and in74 ) ); + state_next(364) <= (not reset) and ( state_cur(228) ); + state_next(365) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 5) ) or ( state_cur(244) ) or ( state_cur(137) and in34 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) or ( state_cur(126) and not ( in32 ) and in31 ) ); + state_next(366) <= (not reset) and ( state_cur(441) ); + state_next(367) <= (not reset) and ( state_cur(201) ); + state_next(368) <= (not reset) and ( state_cur(221) ); + state_next(369) <= (not reset) and ( state_cur(231) ); + state_next(370) <= (not reset) and ( state_cur(394) ); + state_next(371) <= (not reset) and ( ( state_cur(2) and not ( in0 ) ) ); + state_next(372) <= (not reset) and ( state_cur(375) ); + state_next(373) <= (not reset) and ( state_cur(215) ); + state_next(374) <= (not reset) and ( state_cur(217) ); + state_next(375) <= (not reset) and ( state_cur(355) ); + state_next(376) <= (not reset) and ( state_cur(381) ); + state_next(377) <= (not reset) and ( state_cur(127) ); + state_next(378) <= (not reset) and ( ( state_cur(428) and in69 ) or ( state_cur(43) and not ( in11 ) ) ); + state_next(379) <= (not reset) and ( ( state_cur(47) and not ( in13 ) ) ); + state_next(380) <= (not reset) and ( state_cur(351) ); + state_next(381) <= (not reset) and ( state_cur(216) ); + state_next(382) <= (not reset) and ( state_cur(195) ); + state_next(383) <= (not reset) and ( ( state_cur(469) ) or ( state_cur(462) ) or ( state_cur(461) ) or ( state_cur(445) ) or ( state_cur(257) ) ); + state_next(384) <= (not reset) and ( state_cur(196) ); + state_next(385) <= (not reset) and ( state_cur(120) ); + state_next(386) <= (not reset) and ( ( state_cur(263) and not ( not (in50) ) ) ); + state_next(387) <= (not reset) and ( state_cur(342) ); + state_next(388) <= (not reset) and ( state_cur(60) ); + state_next(389) <= (not reset) and ( state_cur(235) ); + state_next(390) <= (not reset) and ( ( state_cur(262) and not ( not (in50) ) ) ); + state_next(391) <= (not reset) and ( state_cur(393) or ( state_cur(390) and in54 ) ); + state_next(392) <= (not reset) and ( ( state_cur(390) and not ( in54 ) ) ); + state_next(393) <= (not reset) and ( state_cur(395) or ( state_cur(392) and in55 ) ); + state_next(394) <= (not reset) and ( state_cur(364) ); + state_next(395) <= (not reset) and ( ( state_cur(416) and not ( in62 ) ) or ( state_cur(409) and not ( in59 ) ) ); + state_next(396) <= (not reset) and ( ( state_cur(396) and to_stdl(funccall0 = 0) ) or ( state_cur(338) and in52 ) or ( state_cur(251) and in48 ) or ( state_cur(249) and not ( in47 ) ) or ( state_cur(249) and in47 ) or ( state_cur(246) and not ( in46 ) ) or ( state_cur(243) ) or ( state_cur(242) ) or ( state_cur(238) ) or ( state_cur(237) ) or ( state_cur(212) and in43 ) or ( state_cur(211) ) or ( state_cur(207) and to_stdl(funccall1 = 0) ) or ( state_cur(207) and to_stdl(funccall1 = 3) ) or ( state_cur(179) and in40 ) or ( state_cur(170) and in39 ) or ( state_cur(160) and in38 ) or ( state_cur(148) and in36 ) or ( state_cur(137) and not ( in34 ) ) or ( state_cur(130) and not ( in33 ) ) or ( state_cur(130) and in33 ) ); + state_next(397) <= (not reset) and ( ( state_cur(457) and not ( not (in77) ) ) or ( state_cur(264) and not ( not (in50) ) ) ); + state_next(398) <= (not reset) and ( ( state_cur(399) and not ( in56 ) ) ); + state_next(399) <= (not reset) and ( state_cur(401) or state_cur(276) ); + state_next(400) <= (not reset) and ( state_cur(109) ); + state_next(401) <= (not reset) and ( ( state_cur(403) and not ( in57 ) ) ); + state_next(402) <= (not reset) and ( ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 1) ) ); + state_next(403) <= (not reset) and ( state_cur(405) or state_cur(402) ); + state_next(404) <= (not reset) and ( state_cur(387) ); + state_next(405) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 3) ) ); + state_next(406) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 1) ) ); + state_next(407) <= (not reset) and ( state_cur(408) or state_cur(406) ); + state_next(408) <= (not reset) and ( ( state_cur(409) and in59 ) ); + state_next(409) <= (not reset) and ( ( state_cur(417) and not ( in63 ) ) or state_cur(398) ); + state_next(410) <= (not reset) and ( ( state_cur(411) and not ( in60 ) ) ); + state_next(411) <= (not reset) and ( state_cur(412) or state_cur(236) ); + state_next(412) <= (not reset) and ( ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 0) ) ); + state_next(413) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 0) ) ); + state_next(414) <= (not reset) and ( state_cur(415) or state_cur(413) ); + state_next(415) <= (not reset) and ( ( state_cur(416) and in62 ) ); + state_next(416) <= (not reset) and ( ( state_cur(417) and in63 ) or state_cur(410) ); + state_next(417) <= (not reset) and ( ( state_cur(419) and not ( in64 ) ) ); + state_next(418) <= (not reset) and ( ( state_cur(414) and in61 ) ); + state_next(419) <= (not reset) and ( state_cur(421) or state_cur(420) ); + state_next(420) <= (not reset) and ( ( state_cur(419) and in64 ) ); + state_next(421) <= (not reset) and ( ( state_cur(422) and not ( in65 ) ) ); + state_next(422) <= (not reset) and ( state_cur(261) or state_cur(0) ); + state_next(423) <= (not reset) and ( ( state_cur(265) and not ( not (in51) ) ) ); + state_next(424) <= (not reset) and ( state_cur(435) ); + state_next(425) <= (not reset) and ( state_cur(146) ); + state_next(426) <= (not reset) and ( ( state_cur(39) and not ( in9 ) ) ); + state_next(427) <= (not reset) and ( state_cur(429) ); + state_next(428) <= (not reset) and ( state_cur(378) ); + state_next(429) <= (not reset) and ( state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) ); + state_next(430) <= (not reset) and ( state_cur(41) ); + state_next(431) <= (not reset) and ( state_cur(379) ); + state_next(432) <= (not reset) and ( state_cur(271) ); + state_next(433) <= (not reset) and ( state_cur(174) ); + state_next(434) <= (not reset) and ( state_cur(143) ); + state_next(435) <= (not reset) and ( state_cur(173) or state_cur(27) ); + state_next(436) <= (not reset) and ( state_cur(181) ); + state_next(437) <= (not reset) and ( state_cur(443) or ( state_cur(157) and not ( in37 ) ) ); + state_next(438) <= (not reset) and ( state_cur(334) ); + state_next(439) <= (not reset) and ( state_cur(440) or state_cur(220) ); + state_next(440) <= (not reset) and ( ( state_cur(472) ) or ( state_cur(468) ) ); + state_next(441) <= (not reset) and ( ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) ); + state_next(442) <= (not reset) and ( state_cur(153) ); + state_next(443) <= (not reset) and ( state_cur(132) ); + state_next(444) <= (not reset) and ( ( state_cur(66) and not ( in18 ) ) ); + state_next(445) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) ) ); + state_next(446) <= (not reset) and ( ( state_cur(449) and not ( in73 ) ) or ( state_cur(448) and not ( in72 ) ) ); + state_next(447) <= (not reset) and ( state_cur(450) ); + state_next(448) <= (not reset) and ( ( state_cur(449) and in73 ) ); + state_next(449) <= (not reset) and ( state_cur(447) or state_cur(363) ); + state_next(450) <= (not reset) and ( ( state_cur(448) and in72 ) ); + state_next(451) <= (not reset) and ( ( state_cur(452) and in75 ) ); + state_next(452) <= (not reset) and ( state_cur(446) or state_cur(383) ); + state_next(453) <= (not reset) and ( state_cur(123) ); + state_next(454) <= (not reset) and ( state_cur(324) ); + state_next(455) <= (not reset) and ( state_cur(222) ); + state_next(456) <= (not reset) and ( state_cur(149) ); + state_next(457) <= reset or ( ( state_cur(457) and not (in77) ) ); + state_next(458) <= (not reset) and ( ( state_cur(407) and in58 ) ); + state_next(459) <= (not reset) and ( ( state_cur(424) and in67 ) ); + state_next(460) <= (not reset) and ( state_cur(459) ); + state_next(461) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) ); + state_next(462) <= (not reset) and ( ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) ); + state_next(463) <= (not reset) and ( state_cur(464) ); + state_next(464) <= (not reset) and ( state_cur(144) ); + state_next(465) <= (not reset) and ( state_cur(467) ); + state_next(466) <= (not reset) and ( state_cur(437) ); + state_next(467) <= (not reset) and ( state_cur(147) ); + state_next(468) <= (not reset) and ( ( state_cur(414) and not ( in61 ) ) ); + state_next(469) <= (not reset) and ( ( state_cur(411) and in60 ) ); + state_next(470) <= (not reset) and ( ( state_cur(407) and not ( in58 ) ) ); + state_next(471) <= (not reset) and ( ( state_cur(278) and to_stdl(funccall9 = 2) ) ); + state_next(472) <= (not reset) and ( ( state_cur(403) and in57 ) ); + state_next(473) <= (not reset) and ( state_cur(116) ); + + -- Assignment of buffers for buffered outputs + + out1057_bufn <= state_cur(127) or state_cur(425); + out59_bufn <= state_cur(305) or state_cur(377); + out447_bufn <= state_cur(382) or state_cur(111); + out157_bufn <= state_cur(28) or state_cur(26) or ( state_cur(25) and not ( in6 ) ); + out450_bufn <= state_cur(194) or state_cur(96); + out1012_bufn <= state_cur(221) or state_cur(291); + out1072_bufn <= state_cur(351) or state_cur(308); + out999_bufn <= state_cur(196) or state_cur(286); + out437_bufn <= state_cur(94) or state_cur(172); + out415_bufn <= state_cur(330) or state_cur(98); + out426_bufn <= state_cur(321) or state_cur(223) or state_cur(224) or state_cur(107); + out375_bufn <= state_cur(360) or state_cur(315); + out704_bufn <= state_cur(356) or state_cur(193) or state_cur(311) or state_cur(310) or state_cur(95) or state_cur(362); + out973_bufn <= state_cur(275) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ); + out11_bufn <= state_cur(222) or state_cur(153) or state_cur(181) or state_cur(109) or state_cur(364) or state_cur(120) or state_cur(215) or state_cur(394) or state_cur(231) or state_cur(201) or state_cur(228) or state_cur(33) or state_cur(352) or state_cur(117) or state_cur(1) or state_cur(162) or state_cur(400) or state_cur(442) or state_cur(150) or state_cur(358) or state_cur(203) or state_cur(189) or state_cur(279) or state_cur(274) or state_cur(272) or state_cur(198) or state_cur(232) or state_cur(280) or state_cur(233) or state_cur(225) or state_cur(230) or state_cur(218) or state_cur(227) or state_cur(226) or state_cur(367) or state_cur(370) or state_cur(373) or state_cur(62) or state_cur(344) or state_cur(182) or state_cur(359) or state_cur(204) or state_cur(118) or state_cur(371) or state_cur(343) or state_cur(336) or state_cur(455) or state_cur(88) or state_cur(361) or state_cur(156) or state_cur(335) or state_cur(151) or state_cur(166) or state_cur(119) or state_cur(180) or state_cur(337) or state_cur(347) or state_cur(345) or state_cur(199) or state_cur(436) or state_cur(112) or state_cur(208) or state_cur(369) or state_cur(385); + out549_bufn <= state_cur(87) or state_cur(465); + out453_bufn <= state_cur(304) or state_cur(380); + out1231_bufn <= state_cur(261) or state_cur(0) or state_cur(421) or state_cur(420) or state_cur(415) or state_cur(413) or state_cur(412) or state_cur(236) or state_cur(408) or state_cur(406) or state_cur(405) or state_cur(402) or state_cur(401) or state_cur(276); + out87_bufn <= state_cur(147) or state_cur(467) or state_cur(312) or state_cur(10) or state_cur(465) or state_cur(21) or state_cur(96) or state_cur(317) or state_cur(140); + out401_bufn <= state_cur(4) or state_cur(306); + out990_bufn <= state_cur(316) or state_cur(281); + out378_bufn <= state_cur(376) or state_cur(292); + out1302_bufn <= state_cur(132) or state_cur(443) or ( state_cur(157) and not ( in37 ) ); + out27_bufn <= ( state_cur(448) and in72 ) or ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or state_cur(193) or state_cur(311) or state_cur(310) or state_cur(95) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or state_cur(362) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) or state_cur(186) or ( state_cur(126) and in32 ) or state_cur(136) or state_cur(135) or ( state_cur(64) and in17 ) or ( state_cur(45) and in12 ) or ( state_cur(77) and to_stdl(funccall3 = 1) ) or ( state_cur(75) and to_stdl(funccall3 = 1) ) or ( state_cur(77) and to_stdl(funccall3 = 3) ) or ( state_cur(75) and to_stdl(funccall3 = 3) ) or ( state_cur(2) and in0 ); + out569_bufn <= ( state_cur(138) and not ( in35 ) ) or ( state_cur(207) and to_stdl(funccall1 = 5) ); + out1030_bufn <= state_cur(438) or state_cur(101); + out537_bufn <= state_cur(293) or state_cur(110); + out77_bufn <= state_cur(144) or state_cur(464) or state_cur(143) or state_cur(155) or state_cur(114) or state_cur(313) or state_cur(309) or state_cur(308) or state_cur(108) or state_cur(304) or state_cur(434) or state_cur(301) or state_cur(103) or state_cur(101) or state_cur(298) or state_cur(297) or state_cur(100) or state_cur(97) or state_cur(294) or state_cur(293) or state_cur(94) or state_cur(291) or state_cur(91) or state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(90) or state_cur(92) or state_cur(281) or state_cur(84) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(58) or state_cur(85) or state_cur(9) or state_cur(463) or state_cur(111) or state_cur(314) or state_cur(307) or state_cur(104) or state_cur(300) or state_cur(102) or state_cur(106) or state_cur(299) or state_cur(98) or state_cur(290) or state_cur(296) or state_cur(295) or state_cur(93) or state_cur(99) or state_cur(292) or state_cur(315) or state_cur(89) or state_cur(283) or state_cur(282) or state_cur(302) or state_cur(56) or state_cur(266) or state_cur(327); + out1318_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) ); + out533_bufn <= state_cur(219) or state_cur(9); + out32_bufn <= state_cur(305) or state_cur(176) or state_cur(317) or state_cur(377); + out1027_bufn <= state_cur(142) or state_cur(298); + out599_bufn <= ( state_cur(35) and to_stdl(funccall6 = 0) ) or state_cur(186) or ( state_cur(126) and in32 ); + out668_bufn <= state_cur(84) or state_cur(456); + out568_bufn <= state_cur(261) or state_cur(0) or state_cur(421) or state_cur(420) or state_cur(415) or state_cur(413) or state_cur(412) or state_cur(236) or state_cur(401) or state_cur(276) or ( state_cur(207) and to_stdl(funccall1 = 4) ) or ( state_cur(207) and to_stdl(funccall1 = 5) ); + out225_bufn <= ( state_cur(39) and not ( in9 ) ) or ( state_cur(53) and not ( in14 ) ); + out700_bufn <= state_cur(143) or state_cur(473); + out638_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ); + out670_bufn <= state_cur(312) or state_cur(348); + out433_bufn <= state_cur(116) or state_cur(307); + out896_bufn <= ( state_cur(411) and in60 ) or ( state_cur(399) and in56 ); + out575_bufn <= state_cur(163) or state_cur(11) or ( state_cur(160) and not ( in38 ) ); + out428_bufn <= state_cur(197) or state_cur(104); + out72_bufn <= state_cur(144) or state_cur(464) or state_cur(143) or state_cur(155) or state_cur(114) or state_cur(313) or state_cur(309) or state_cur(308) or state_cur(108) or state_cur(304) or state_cur(434) or state_cur(301) or state_cur(103) or state_cur(101) or state_cur(298) or state_cur(297) or state_cur(100) or state_cur(97) or state_cur(294) or state_cur(293) or state_cur(94) or state_cur(291) or state_cur(91) or state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(90) or state_cur(92) or state_cur(281) or state_cur(84) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(58) or state_cur(85) or state_cur(9) or state_cur(463) or state_cur(111) or state_cur(314) or state_cur(307) or state_cur(104) or state_cur(300) or state_cur(102) or state_cur(106) or state_cur(299) or state_cur(98) or state_cur(290) or state_cur(296) or state_cur(295) or state_cur(93) or state_cur(99) or state_cur(292) or state_cur(315) or state_cur(89) or state_cur(283) or state_cur(282) or state_cur(302) or state_cur(56) or state_cur(266) or ( state_cur(82) and in24 ) or state_cur(327); + out404_bufn <= state_cur(115) or state_cur(312) or state_cur(185) or state_cur(176) or state_cur(194) or state_cur(348) or state_cur(96) or state_cur(317); + out98_bufn <= ( state_cur(396) and to_stdl(funccall0 = 15) ) or ( state_cur(396) and to_stdl(funccall0 = 16) ); + out67_bufn <= ( state_cur(424) and in67 ) or ( state_cur(252) and not ( in49 ) ) or state_cur(202); + out635_bufn <= state_cur(165) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ); + out381_bufn <= state_cur(145) or state_cur(99); + out222_bufn <= ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(41) or ( state_cur(64) and in17 ) or ( state_cur(53) and not ( in14 ) ); + out339_bufn <= state_cur(273) or ( state_cur(76) and in22 ) or ( state_cur(76) and not ( in22 ) ); + out268_bufn <= state_cur(41) or ( state_cur(53) and in14 ); + out419_bufn <= state_cur(375) or state_cur(106); + out559_bufn <= ( state_cur(138) and not ( in35 ) ) or state_cur(353) or state_cur(214) or state_cur(152); + out1002_bufn <= state_cur(60) or state_cur(287); + out1006_bufn <= state_cur(37) or state_cur(289); + out276_bufn <= state_cur(318) or state_cur(266); + out205_bufn <= state_cur(116) or state_cur(149) or state_cur(334) or state_cur(387) or state_cur(60) or state_cur(342) or state_cur(196) or state_cur(195) or state_cur(216) or state_cur(351) or state_cur(381) or state_cur(355) or state_cur(375) or state_cur(221) or state_cur(368) or ( state_cur(82) and not ( in24 ) ) or state_cur(175) or state_cur(404) or state_cur(37) or state_cur(219) or state_cur(200) or state_cur(382) or state_cur(339) or state_cur(177) or state_cur(349) or state_cur(197) or state_cur(438) or state_cur(113) or state_cur(142) or state_cur(141) or state_cur(145) or state_cur(325) or state_cur(323) or state_cur(330) or state_cur(320) or state_cur(326) or state_cur(316) or state_cur(329) or state_cur(318) or state_cur(357) or state_cur(346) or state_cur(340) or state_cur(178) or state_cur(376) or state_cur(55) or state_cur(86) or state_cur(360) or state_cur(473) or state_cur(384) or state_cur(192) or state_cur(456) or state_cur(322) or state_cur(341) or state_cur(319) or state_cur(110) or state_cur(332) or state_cur(331) or state_cur(380) or state_cur(303) or state_cur(172) or state_cur(388) or state_cur(350) or state_cur(372) or state_cur(328); + out943_bufn <= state_cur(329) or state_cur(85); + out1080_bufn <= state_cur(193) or state_cur(311); + out408_bufn <= state_cur(322) or state_cur(295); + out252_bufn <= state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or ( state_cur(39) and not ( in9 ) ) or state_cur(426) or ( state_cur(45) and in12 ); + out71_bufn <= state_cur(341) or state_cur(327); + out672_bufn <= state_cur(434) or state_cur(192); + out357_bufn <= state_cur(319) or state_cur(282); + out441_bufn <= state_cur(195) or state_cur(314); + out1084_bufn <= state_cur(387) or state_cur(313); + out144_bufn <= ( state_cur(78) and in23 ) or ( state_cur(73) and not ( in20 ) ) or ( state_cur(72) ) or ( state_cur(454) and in76 ); + out574_bufn <= state_cur(184) or state_cur(154) or ( state_cur(170) and not ( in39 ) ) or ( state_cur(160) and not ( in38 ) ); + out210_bufn <= ( state_cur(39) and not ( in9 ) ) or ( state_cur(40) and in10 ); + out128_bufn <= state_cur(306) or ( state_cur(82) and in24 ); + out360_bufn <= state_cur(288) or state_cur(388); + out948_bufn <= state_cur(141) or state_cur(58); + out506_bufn <= ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) or ( state_cur(453) and to_stdl(funccall4 = 0) ) or ( state_cur(131) and to_stdl(funccall4 = 0) ) or ( state_cur(70) and to_stdl(funccall4 = 0) ); + out207_bufn <= state_cur(93) or state_cur(328); + out1083_bufn <= state_cur(342) or state_cur(309); + out491_bufn <= state_cur(146) or state_cur(171); + out4_bufn <= state_cur(147) or state_cur(467) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) or state_cur(446) or state_cur(383) or state_cur(447) or state_cur(363) or state_cur(450) or ( state_cur(449) and not ( in73 ) ) or ( state_cur(448) and not ( in72 ) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) ) or state_cur(132) or ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(41) or state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or state_cur(146) or ( state_cur(265) and not ( not (in51) ) ) or ( state_cur(419) and in64 ) or ( state_cur(278) and to_stdl(funccall9 = 0) ) or ( state_cur(411) and not ( in60 ) ) or ( state_cur(278) and to_stdl(funccall9 = 1) ) or ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 1) ) or ( state_cur(399) and not ( in56 ) ) or ( state_cur(396) and to_stdl(funccall0 = 0) ) or ( state_cur(338) and in52 ) or ( state_cur(251) and in48 ) or ( state_cur(249) and not ( in47 ) ) or ( state_cur(249) and in47 ) or ( state_cur(246) and not ( in46 ) ) or ( state_cur(243) ) or ( state_cur(242) ) or ( state_cur(238) ) or ( state_cur(237) ) or ( state_cur(212) and in43 ) or ( state_cur(211) ) or ( state_cur(207) and to_stdl(funccall1 = 0) ) or ( state_cur(207) and to_stdl(funccall1 = 3) ) or ( state_cur(179) and in40 ) or ( state_cur(170) and in39 ) or ( state_cur(160) and in38 ) or ( state_cur(148) and in36 ) or ( state_cur(137) and not ( in34 ) ) or ( state_cur(130) and not ( in33 ) ) or ( state_cur(130) and in33 ) or ( state_cur(390) and not ( in54 ) ) or ( state_cur(262) and not ( not (in50) ) ) or ( state_cur(428) and in69 ) or ( state_cur(43) and not ( in11 ) ) or ( state_cur(2) and not ( in0 ) ) or ( state_cur(396) and to_stdl(funccall0 = 5) ) or ( state_cur(244) ) or ( state_cur(137) and in34 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) or ( state_cur(126) and not ( in32 ) and in31 ) or ( state_cur(105) and in25 ) or ( state_cur(78) and in23 ) or ( state_cur(73) and not ( in20 ) ) or ( state_cur(72) ) or state_cur(312) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or ( state_cur(396) and to_stdl(funccall0 = 9) ) or state_cur(164) or state_cur(374) or state_cur(365) or ( state_cur(210) and in42 ) or ( state_cur(209) and not ( in41 ) ) or ( state_cur(210) and not ( in42 ) ) or state_cur(191) or state_cur(176) or state_cur(426) or state_cur(194) or state_cur(124) or state_cur(348) or ( state_cur(433) and in70 ) or ( state_cur(59) and not ( in16 ) ) or state_cur(87) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) or state_cur(10) or state_cur(465) or state_cur(21) or state_cur(136) or state_cur(135) or state_cur(171) or state_cur(354) or state_cur(183) or state_cur(96) or state_cur(317) or state_cur(122) or ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) ) or ( state_cur(64) and in17 ) or ( state_cur(64) and not ( in17 ) ) or ( state_cur(54) and not ( in15 ) ) or state_cur(430) or state_cur(52) or ( state_cur(45) and in12 ) or ( state_cur(45) and not ( in12 ) ) or ( state_cur(40) and not ( in10 ) ) or state_cur(188) or state_cur(38) or ( state_cur(121) and in26 ) or ( state_cur(454) and in76 ) or ( state_cur(17) and in3 ) or ( state_cur(82) and in24 ) or ( state_cur(396) and to_stdl(funccall0 = 15) ) or ( state_cur(396) and to_stdl(funccall0 = 16) ) or state_cur(140) or ( state_cur(252) and not ( in49 ) ) or state_cur(202) or ( state_cur(6) and in1 ) or ( state_cur(2) and in0 ) or ( state_cur(422) and in65 ); + out784_bufn <= state_cur(115) or state_cur(185); + out3_bufn <= ( state_cur(419) and in64 ) or ( state_cur(278) and to_stdl(funccall9 = 0) ) or ( state_cur(278) and to_stdl(funccall9 = 1) ) or ( state_cur(439) and not ( in71 ) and to_stdl(funccall8 = 1) ) or ( state_cur(422) and in65 ); + out746_bufn <= state_cur(247) or state_cur(239) or state_cur(213) or state_cur(205); + out528_bufn <= state_cur(297) or state_cur(332); + out372_bufn <= state_cur(381) or state_cur(89); + out418_bufn <= state_cur(334) or state_cur(299); + out708_bufn <= state_cur(285) or state_cur(86); + out706_bufn <= state_cur(193) or state_cur(362); + out445_bufn <= state_cur(267) or state_cur(303); + out1021_bufn <= state_cur(323) or state_cur(100); + out405_bufn <= state_cur(193) or state_cur(115) or state_cur(312) or state_cur(311) or state_cur(310) or state_cur(95) or state_cur(185) or state_cur(176) or state_cur(362) or state_cur(194) or state_cur(348) or state_cur(96) or state_cur(317); + out764_bufn <= state_cur(284) or state_cur(178); + out581_bufn <= state_cur(253) or state_cur(133); + out776_bufn <= state_cur(91) or state_cur(346); + out213_bufn <= state_cur(184) or state_cur(154) or state_cur(255) or state_cur(12) or state_cur(68) or state_cur(63) or state_cur(57) or state_cur(50) or state_cur(49) or state_cur(44) or state_cur(42) or state_cur(34); + out674_bufn <= state_cur(90) or state_cur(384); + out1326_bufn <= state_cur(447) or state_cur(363) or ( state_cur(449) and in73 ); + out334_bufn <= ( state_cur(270) ) or ( state_cur(30) and in8 ) or ( state_cur(25) and in6 ) or ( state_cur(15) ) or ( state_cur(76) and in22 ) or ( state_cur(76) and not ( in22 ) ) or ( state_cur(74) and in21 ); + out843_bufn <= state_cur(275) or state_cur(165); + out175_bufn <= state_cur(32) or state_cur(31) or ( state_cur(30) and not ( in8 ) ); + out1036_bufn <= state_cur(355) or state_cur(301); + out1015_bufn <= state_cur(320) or state_cur(294); + out236_bufn <= state_cur(378) or state_cur(429) or ( state_cur(427) and not ( in68 ) ); + out395_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 4) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 4) ) or state_cur(164) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 0) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 0) ) or state_cur(306); + out1340_bufn <= state_cur(446) or state_cur(383) or ( state_cur(452) and in75 ); + out993_bufn <= state_cur(200) or state_cur(92); + out356_bufn <= state_cur(149) or state_cur(302); + out273_bufn <= state_cur(102) or state_cur(372); + out403_bufn <= state_cur(176) or state_cur(317); + out286_bufn <= state_cur(290) or state_cur(350); + out364_bufn <= state_cur(176) or state_cur(194) or state_cur(124) or state_cur(348) or state_cur(87) or state_cur(354) or state_cur(183) or state_cur(122); + out697_bufn <= state_cur(253) or state_cur(191) or ( state_cur(252) and in49 ); + out283_bufn <= state_cur(174) or state_cur(441) or ( state_cur(366) and not ( in53 ) ); + out282_bufn <= state_cur(331) or state_cur(56); + out1319_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 3) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 3) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) or ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 1) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 1) ); + out409_bufn <= state_cur(326) or state_cur(296); + out1092_bufn <= state_cur(339) or state_cur(155); + out1075_bufn <= state_cur(356) or state_cur(95); + out925_bufn <= ( state_cur(51) and to_stdl(funccall5 = 0) ) or ( state_cur(35) and to_stdl(funccall6 = 1) ); + out78_bufn <= state_cur(144) or state_cur(464) or state_cur(143) or state_cur(235) or state_cur(155) or state_cur(114) or state_cur(313) or state_cur(309) or state_cur(308) or state_cur(108) or state_cur(304) or state_cur(434) or state_cur(301) or state_cur(103) or state_cur(101) or state_cur(298) or state_cur(297) or state_cur(100) or state_cur(97) or state_cur(294) or state_cur(293) or state_cur(94) or state_cur(291) or state_cur(91) or state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(90) or state_cur(92) or state_cur(281) or state_cur(84) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(58) or state_cur(85) or state_cur(9) or state_cur(463) or state_cur(111) or state_cur(314) or state_cur(307) or state_cur(104) or state_cur(300) or state_cur(102) or state_cur(106) or state_cur(299) or state_cur(98) or state_cur(290) or state_cur(296) or state_cur(295) or state_cur(93) or state_cur(99) or state_cur(292) or state_cur(315) or state_cur(89) or state_cur(283) or state_cur(282) or state_cur(302) or state_cur(56) or state_cur(266) or state_cur(327); + out1089_bufn <= state_cur(368) or state_cur(114); + out362_bufn <= state_cur(124) or state_cur(87) or state_cur(171) or state_cur(354) or state_cur(183) or state_cur(122); + out982_bufn <= state_cur(357) or state_cur(277); + out979_bufn <= ( state_cur(82) and not ( in24 ) ) or state_cur(269); + out952_bufn <= state_cur(113) or state_cur(268); + out1109_bufn <= state_cur(464) or state_cur(177); + out16_bufn <= state_cur(459) or state_cur(440) or state_cur(220) or state_cur(161) or state_cur(139) or state_cur(83) or state_cur(16) or state_cur(19) or state_cur(18) or state_cur(14) or state_cur(7) or state_cur(5) or state_cur(8) or state_cur(3); + out703_bufn <= state_cur(310) or state_cur(362); + out371_bufn <= state_cur(216) or state_cur(283); + out956_bufn <= state_cur(271) or ( state_cur(256) ) or ( state_cur(254) ); + out1107_bufn <= state_cur(144) or state_cur(349); + out1033_bufn <= state_cur(175) or state_cur(103); + out148_bufn <= state_cur(146) or ( state_cur(121) and in26 ); + out351_bufn <= state_cur(321) or state_cur(223) or state_cur(224) or state_cur(107) or state_cur(83) or state_cur(16); + out740_bufn <= ( state_cur(396) and to_stdl(funccall0 = 0) ) or ( state_cur(338) and in52 ) or ( state_cur(251) and in48 ) or ( state_cur(249) and not ( in47 ) ) or ( state_cur(249) and in47 ) or ( state_cur(246) and not ( in46 ) ) or ( state_cur(243) ) or ( state_cur(242) ) or ( state_cur(238) ) or ( state_cur(237) ) or ( state_cur(212) and in43 ) or ( state_cur(211) ) or ( state_cur(207) and to_stdl(funccall1 = 0) ) or ( state_cur(207) and to_stdl(funccall1 = 3) ) or ( state_cur(179) and in40 ) or ( state_cur(170) and in39 ) or ( state_cur(160) and in38 ) or ( state_cur(148) and in36 ) or ( state_cur(137) and not ( in34 ) ) or ( state_cur(130) and not ( in33 ) ) or ( state_cur(130) and in33 ) or ( state_cur(396) and to_stdl(funccall0 = 5) ) or ( state_cur(244) ) or ( state_cur(137) and in34 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and not ( in29 ) and in28 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and not ( in30 ) and in29 ) or ( state_cur(126) and not ( in32 ) and not ( in31 ) and in30 ) or ( state_cur(126) and not ( in32 ) and in31 ) or state_cur(365); + out391_bufn <= state_cur(127) or state_cur(4) or state_cur(425) or state_cur(306); + out129_bufn <= state_cur(356) or ( state_cur(82) and in24 ); + out338_bufn <= ( state_cur(256) ) or ( state_cur(254) ) or ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) or state_cur(190) or state_cur(187) or state_cur(186) or ( state_cur(126) and in32 ) or ( state_cur(453) and to_stdl(funccall4 = 0) ) or ( state_cur(131) and to_stdl(funccall4 = 0) ) or ( state_cur(70) and to_stdl(funccall4 = 0) ) or state_cur(273) or ( state_cur(76) and in22 ) or ( state_cur(76) and not ( in22 ) ); + out425_bufn <= state_cur(55) or state_cur(300); + out1078_bufn <= state_cur(311) or state_cur(310) or state_cur(95); + out349_bufn <= ( state_cur(80) and to_stdl(funccall2 = 1) ) or ( state_cur(79) and to_stdl(funccall2 = 1) ) or ( state_cur(80) and to_stdl(funccall2 = 0) ) or ( state_cur(79) and to_stdl(funccall2 = 0) ); + out590_bufn <= state_cur(165) or state_cur(186) or ( state_cur(126) and in32 ); + out325_bufn <= state_cur(273) or state_cur(432) or state_cur(71) or ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) ); + out112_bufn <= state_cur(459) or state_cur(14) or state_cur(7) or state_cur(5); + out224_bufn <= ( state_cur(54) and in15 ) or ( state_cur(53) and not ( in14 ) ); + out1220_bufn <= ( state_cur(265) and not ( not (in51) ) ) or ( state_cur(390) and not ( in54 ) ); + out1250_bufn <= ( state_cur(407) and in58 ) or ( state_cur(414) and in61 ); + out365_bufn <= ( state_cur(105) and in25 ) or state_cur(176) or state_cur(194) or state_cur(124) or state_cur(348) or state_cur(87) or state_cur(171) or state_cur(354) or state_cur(183) or state_cur(122); + out699_bufn <= ( state_cur(453) and to_stdl(funccall4 = 1) ) or ( state_cur(131) and to_stdl(funccall4 = 1) ) or ( state_cur(70) and to_stdl(funccall4 = 1) ) or state_cur(191) or ( state_cur(252) and in49 ); + out488_bufn <= ( state_cur(105) and in25 ) or state_cur(171); + out1069_bufn <= state_cur(404) or state_cur(108); + out530_bufn <= state_cur(340) or state_cur(463); + out326_bufn <= ( state_cur(452) and not ( in75 ) and to_stdl(funccall7 = 2) ) or ( state_cur(451) and not ( in74 ) and to_stdl(funccall7 = 2) ) or ( state_cur(80) and to_stdl(funccall2 = 2) ) or ( state_cur(79) and to_stdl(funccall2 = 2) ); + out602_bufn <= state_cur(255) or state_cur(12) or state_cur(163) or state_cur(11); + out83_bufn <= state_cur(147) or state_cur(467) or state_cur(146) or state_cur(10) or state_cur(465) or state_cur(21) or state_cur(140); + out311_bufn <= ( state_cur(433) and not ( in70 ) ) or ( state_cur(366) and in53 ) or state_cur(36) or state_cur(41) or ( state_cur(64) and in17 ); + out253_bufn <= state_cur(431) or ( state_cur(428) and not ( in69 ) ) or ( state_cur(427) and in68 ) or state_cur(426) or ( state_cur(45) and in12 ); + out209_bufn <= state_cur(426) or ( state_cur(39) and in9 ); + out1240_bufn <= ( state_cur(417) and in63 ) or state_cur(410) or ( state_cur(417) and not ( in63 ) ) or state_cur(398); + out1018_bufn <= state_cur(325) or state_cur(97); + out1152_bufn <= state_cur(429) or state_cur(441); + out1236_bufn <= state_cur(408) or state_cur(406) or state_cur(405) or state_cur(402); + out130_bufn <= state_cur(356) or state_cur(186) or ( state_cur(126) and in32 ) or ( state_cur(82) and in24 ); + out567_bufn <= ( state_cur(207) and to_stdl(funccall1 = 4) ) or ( state_cur(207) and to_stdl(funccall1 = 5) ); + out646_bufn <= ( state_cur(29) and in7 ) or ( state_cur(24) and in5 ); + + -- Assignment of non-buffered outputs + + out26 <= + state_cur(3); + out2 <= + state_cur(466) or state_cur(253) or state_cur(202) or state_cur(191) or state_cur(19) or state_cur(0); + out931 <= + state_cur(261); + out715 <= + state_cur(201); + out410 <= + state_cur(98); + out628 <= + state_cur(165); + out734 <= + state_cur(229) or state_cur(206); + out942 <= + state_cur(265); + out122 <= + state_cur(16); + out892 <= + state_cur(255); + out601 <= + state_cur(159); + out809 <= + state_cur(232); + out376 <= + state_cur(91); + out241 <= + state_cur(45); + out986 <= + state_cur(280); + out1323 <= + state_cur(446); + out455 <= + state_cur(117); + out53 <= + state_cur(377) or state_cur(354) or state_cur(306) or state_cur(305) or state_cur(140) or state_cur(4); + out733 <= + state_cur(206); + out229 <= + state_cur(41); + out901 <= + state_cur(469) or state_cur(462) or state_cur(461) or state_cur(445) or state_cur(257); + out60 <= + state_cur(425) or state_cur(377) or state_cur(306) or state_cur(305) or state_cur(127) or state_cur(4); + out228 <= + state_cur(444) or state_cur(441) or state_cur(430) or state_cur(68) or state_cur(67) or state_cur(57) or state_cur(41); + out160 <= + state_cur(25); + out561 <= + state_cur(150); + out743 <= + state_cur(208); + out921 <= + state_cur(259); + out382 <= + state_cur(93); + out566 <= + state_cur(151); + out99 <= + state_cur(255) or state_cur(163) or state_cur(12) or state_cur(11); + out765 <= + state_cur(217); + out366 <= + state_cur(88); + out1005 <= + state_cur(289); + out1119 <= + state_cur(345); + out1356 <= + state_cur(461); + out25 <= + state_cur(8) or state_cur(3); + out802 <= + state_cur(230); + out918 <= + state_cur(259) or state_cur(258); + out258 <= + state_cur(50); + out640 <= + state_cur(166); + out710 <= + state_cur(198); + out1014 <= + state_cur(294); + out505 <= + state_cur(443) or state_cur(437) or state_cur(133) or state_cur(132); + out1303 <= + state_cur(439); + out424 <= + state_cur(104); + out920 <= + state_cur(258); + out180 <= + state_cur(31); + out974 <= + state_cur(276); + out1339 <= + state_cur(450); + out300 <= + state_cur(64); + out472 <= + state_cur(123); + out143 <= + state_cur(324) or state_cur(20); + out1301 <= + state_cur(437); + out479 <= + state_cur(125); + out464 <= + state_cur(120); + out643 <= + state_cur(167); + out636 <= + state_cur(420) or state_cur(276) or state_cur(275) or state_cur(236) or state_cur(165); + out1022 <= + state_cur(297); + out153 <= + state_cur(23); + out263 <= + state_cur(51); + out690 <= + state_cur(213) or state_cur(187); + out712 <= + state_cur(199); + out828 <= + state_cur(235); + out772 <= + state_cur(220); + out342 <= + state_cur(76); + out40 <= + state_cur(465) or state_cur(425) or state_cur(306) or state_cur(127) or state_cur(87) or state_cur(4); + out1223 <= + state_cur(394); + out443 <= + state_cur(112); + out679 <= + state_cur(180); + out1073 <= + state_cur(309); + out150 <= + state_cur(21); + out299 <= + state_cur(68) or state_cur(63); + out1349 <= + state_cur(455); + out1383 <= + state_cur(471); + out572 <= + state_cur(153); + out1298 <= + state_cur(436); + out1311 <= + state_cur(442); + out607 <= + state_cur(161); + out737 <= + state_cur(207); + out510 <= + state_cur(396) or state_cur(365) or state_cur(207) or state_cur(134); + out165 <= + state_cur(28) or state_cur(26); + out462 <= + state_cur(119); + out514 <= + state_cur(136) or state_cur(135); + out531 <= + state_cur(143); + out872 <= + state_cur(243); + out791 <= + state_cur(226); + out417 <= + state_cur(101); + out297 <= + state_cur(63); + out1121 <= + state_cur(347); + out614 <= + state_cur(164); + out64 <= + state_cur(5); + out589 <= + state_cur(158); + out231 <= + state_cur(42); + out888 <= + state_cur(271) or state_cur(256) or state_cur(254); + out1324 <= + state_cur(447); + out1150 <= + state_cur(364); + out1295 <= + state_cur(435); + out152 <= + state_cur(159) or state_cur(22); + out310 <= + state_cur(444) or state_cur(67); + out694 <= + state_cur(189); + out718 <= + state_cur(202); + out759 <= + state_cur(214); + out722 <= + state_cur(203); + out1387 <= + state_cur(472); + out82 <= + state_cur(473) or state_cur(464) or state_cur(463) or state_cur(456) or state_cur(438) or state_cur(434) or state_cur(404) or state_cur(388) or + state_cur(387) or state_cur(384) or state_cur(382) or state_cur(381) or state_cur(380) or state_cur(376) or state_cur(375) or state_cur(372) or + state_cur(368) or state_cur(362) or state_cur(360) or state_cur(357) or state_cur(356) or state_cur(355) or state_cur(351) or state_cur(350) or + state_cur(349) or state_cur(348) or state_cur(346) or state_cur(342) or state_cur(341) or state_cur(340) or state_cur(339) or state_cur(334) or + state_cur(332) or state_cur(331) or state_cur(330) or state_cur(329) or state_cur(328) or state_cur(327) or state_cur(326) or state_cur(325) or + state_cur(323) or state_cur(322) or state_cur(321) or state_cur(320) or state_cur(319) or state_cur(318) or state_cur(317) or state_cur(316) or + state_cur(315) or state_cur(314) or state_cur(313) or state_cur(312) or state_cur(311) or state_cur(310) or state_cur(309) or state_cur(308) or + state_cur(307) or state_cur(304) or state_cur(303) or state_cur(302) or state_cur(301) or state_cur(300) or state_cur(299) or state_cur(298) or + state_cur(297) or state_cur(296) or state_cur(295) or state_cur(294) or state_cur(293) or state_cur(292) or state_cur(291) or state_cur(290) or + state_cur(289) or state_cur(288) or state_cur(287) or state_cur(286) or state_cur(285) or state_cur(284) or state_cur(283) or state_cur(282) or + state_cur(281) or state_cur(278) or state_cur(277) or state_cur(269) or state_cur(268) or state_cur(267) or state_cur(266) or state_cur(224) or + state_cur(221) or state_cur(219) or state_cur(216) or state_cur(200) or state_cur(197) or state_cur(196) or state_cur(195) or state_cur(194) or + state_cur(193) or state_cur(192) or state_cur(185) or state_cur(178) or state_cur(177) or state_cur(176) or state_cur(175) or state_cur(172) or + state_cur(155) or state_cur(149) or state_cur(145) or state_cur(144) or state_cur(143) or state_cur(142) or state_cur(141) or state_cur(116) or + state_cur(115) or state_cur(114) or state_cur(113) or state_cur(111) or state_cur(110) or state_cur(108) or state_cur(106) or state_cur(104) or + state_cur(103) or state_cur(102) or state_cur(101) or state_cur(100) or state_cur(99) or state_cur(98) or state_cur(97) or state_cur(96) or + state_cur(95) or state_cur(94) or state_cur(93) or state_cur(92) or state_cur(91) or state_cur(90) or state_cur(89) or state_cur(86) or + state_cur(85) or state_cur(84) or state_cur(60) or state_cur(58) or state_cur(56) or state_cur(55) or state_cur(37) or state_cur(16) or + state_cur(9); + out1139 <= + state_cur(361); + out558 <= + state_cur(147); + out696 <= + state_cur(190); + out1381 <= + state_cur(470); + out1293 <= + state_cur(435); + out519 <= + state_cur(139); + out1292 <= + state_cur(434); + out895 <= + state_cur(256); + out1176 <= + state_cur(429) or state_cur(379) or state_cur(378); + out170 <= + state_cur(173) or state_cur(27); + out434 <= + state_cur(109); + out341 <= + state_cur(77) or state_cur(75); + out1007 <= + state_cur(290); + out595 <= + state_cur(158); + out874 <= + state_cur(244); + out1364 <= + state_cur(464); + out621 <= + state_cur(164); + out962 <= + state_cur(273); + out767 <= + state_cur(374) or state_cur(220) or state_cur(217); + out523 <= + state_cur(139); + out350 <= + state_cur(81); + out745 <= + state_cur(209); + out863 <= + state_cur(241); + out958 <= + state_cur(272); + out1182 <= + state_cur(446) or state_cur(383); + out13 <= + state_cur(1); + out1 <= + state_cur(0); + out1101 <= + state_cur(336); + out1344 <= + state_cur(452); + out749 <= + state_cur(210); + out972 <= + state_cur(275); + out289 <= + state_cur(61); + out1290 <= + state_cur(432); + out985 <= + state_cur(279); + out279 <= + state_cur(57); + out517 <= + state_cur(138); + out1035 <= + state_cur(302); + out1000 <= + state_cur(287); + out1085 <= + state_cur(314); + out1289 <= + state_cur(431); + out85 <= + state_cur(377) or state_cur(305) or state_cur(124) or state_cur(10); + out35 <= + state_cur(306) or state_cur(183) or state_cur(171) or state_cur(147) or state_cur(146) or state_cur(4); + out304 <= + state_cur(65); + out347 <= + state_cur(80) or state_cur(79); + out1190 <= + state_cur(389); + out649 <= + state_cur(167); + out156 <= + state_cur(24); + out1228 <= + state_cur(396); + out266 <= + state_cur(51); + out651 <= + state_cur(168); + out866 <= + state_cur(242); + out508 <= + state_cur(133); + out1114 <= + state_cur(344); + out245 <= + state_cur(46); + out44 <= + state_cur(354) or state_cur(306) or state_cur(21) or state_cur(4); + out1174 <= + state_cur(431) or state_cur(378); + out80 <= + state_cur(9); + out134 <= + state_cur(17); + out1187 <= + state_cur(391) or state_cur(386); + out1032 <= + state_cur(301); + out1287 <= + state_cur(430); + out989 <= + state_cur(281); + out538 <= + state_cur(146); + out1104 <= + state_cur(337); + out981 <= + state_cur(278); + out1286 <= + state_cur(429); + out724 <= + state_cur(204); + out487 <= + state_cur(127); + out658 <= + state_cur(169); + out1215 <= + state_cur(393) or state_cur(390); + out407 <= + state_cur(97); + out534 <= + state_cur(144); + out1175 <= + state_cur(378); + out858 <= + state_cur(239); + out1284 <= + state_cur(429); + out402 <= + state_cur(356) or state_cur(171) or state_cur(146) or state_cur(95); + out755 <= + state_cur(212); + out255 <= + state_cur(48); + out93 <= + state_cur(11); + out467 <= + state_cur(122); + out379 <= + state_cur(92); + out664 <= + state_cur(174); + out429 <= + state_cur(106); + out322 <= + state_cur(123) or state_cur(81) or state_cur(71); + out949 <= + state_cur(268); + out826 <= + state_cur(389) or state_cur(235); + out681 <= + state_cur(181); + out905 <= + state_cur(462) or state_cur(461) or state_cur(445) or state_cur(257); + out15 <= + state_cur(2); + out794 <= + state_cur(227); + out795 <= + state_cur(228); + out139 <= + state_cur(19); + out193 <= + state_cur(35); + out1019 <= + state_cur(296); + out171 <= + state_cur(28); + out173 <= + state_cur(29); + out610 <= + state_cur(162); + out1279 <= + state_cur(427); + out440 <= + state_cur(111); + out480 <= + state_cur(134) or state_cur(125); + out860 <= + state_cur(239); + out1158 <= + state_cur(369); + out189 <= + state_cur(33); + out902 <= + state_cur(257); + out1134 <= + state_cur(358); + out799 <= + state_cur(229); + out955 <= + state_cur(270); + out1278 <= + state_cur(426); + out1098 <= + state_cur(335); + out963 <= + state_cur(274); + out373 <= + state_cur(90); + out728 <= + state_cur(213) or state_cur(205); + out1160 <= + state_cur(370); + out570 <= + state_cur(353) or state_cur(214) or state_cur(152); + out937 <= + state_cur(262); + out1275 <= + state_cur(426); + out114 <= + state_cur(14); + out812 <= + state_cur(233); + out787 <= + state_cur(225); + out7 <= + state_cur(421) or state_cur(420) or state_cur(415) or state_cur(413) or state_cur(412) or state_cur(408) or state_cur(406) or state_cur(405) or + state_cur(402) or state_cur(401) or state_cur(275) or state_cur(261) or state_cur(165) or state_cur(0); + out396 <= + state_cur(95); + out762 <= + state_cur(215); + out978 <= + state_cur(277); + out933 <= + state_cur(410) or state_cur(398) or state_cur(261); + out938 <= + state_cur(263); + out313 <= + state_cur(67); + out1131 <= + state_cur(356); + out778 <= + state_cur(222); + out848 <= + state_cur(236); + out882 <= + state_cur(251) or state_cur(250) or state_cur(248); + out1229 <= + state_cur(398); + out1180 <= + state_cur(450) or state_cur(383); + out1155 <= + state_cur(367); + out947 <= + state_cur(267); + out232 <= + state_cur(426) or state_cur(258) or state_cur(158) or state_cur(42); + out201 <= + state_cur(36); + out783 <= + state_cur(223); + out996 <= + state_cur(284); + out1094 <= + state_cur(333); + out420 <= + state_cur(102); + out107 <= + state_cur(12); + out1269 <= + state_cur(425); + out414 <= + state_cur(100); + out1011 <= + state_cur(292); + out333 <= + state_cur(123) or state_cur(72); + out296 <= + state_cur(62); + out335 <= + state_cur(73); + out726 <= + state_cur(205); + out1151 <= + state_cur(366); + out256 <= + state_cur(49); + out111 <= + state_cur(255) or state_cur(12); + out1068 <= + state_cur(307); + out202 <= + state_cur(174) or state_cur(36); + out1368 <= + state_cur(467); + out1181 <= + state_cur(383); + out1137 <= + state_cur(359); + out1308 <= + state_cur(441); + out768 <= + state_cur(218); + out500 <= + state_cur(131); + out14 <= + state_cur(455) or state_cur(442) or state_cur(436) or state_cur(400) or state_cur(394) or state_cur(385) or state_cur(373) or state_cur(370) or + state_cur(369) or state_cur(367) or state_cur(364) or state_cur(361) or state_cur(359) or state_cur(358) or state_cur(352) or state_cur(347) or + state_cur(345) or state_cur(344) or state_cur(343) or state_cur(337) or state_cur(336) or state_cur(335) or state_cur(280) or state_cur(279) or + state_cur(274) or state_cur(272) or state_cur(233) or state_cur(232) or state_cur(231) or state_cur(230) or state_cur(228) or state_cur(227) or + state_cur(226) or state_cur(225) or state_cur(223) or state_cur(222) or state_cur(218) or state_cur(215) or state_cur(208) or state_cur(204) or + state_cur(203) or state_cur(201) or state_cur(199) or state_cur(198) or state_cur(189) or state_cur(182) or state_cur(181) or state_cur(180) or + state_cur(166) or state_cur(162) or state_cur(156) or state_cur(153) or state_cur(151) or state_cur(150) or state_cur(120) or state_cur(119) or + state_cur(118) or state_cur(117) or state_cur(112) or state_cur(109) or state_cur(88) or state_cur(62) or state_cur(33) or state_cur(3) or + state_cur(1); + out1164 <= + state_cur(371); + out1125 <= + state_cur(352); + out1016 <= + state_cur(295); + out688 <= + state_cur(186); + out1026 <= + state_cur(299); + out1329 <= + state_cur(449); + out191 <= + state_cur(34); + out855 <= + state_cur(238); + out597 <= + state_cur(258) or state_cur(158); + out184 <= + state_cur(32) or state_cur(31); + out162 <= + state_cur(26); + out422 <= + state_cur(103); + out197 <= + state_cur(188) or state_cur(38) or state_cur(35); + out104 <= + state_cur(12); + out1266 <= + state_cur(423); + out117 <= + state_cur(15); + out1024 <= + state_cur(298); + out221 <= + state_cur(41); + out1088 <= + state_cur(315); + out1128 <= + state_cur(354); + out923 <= + state_cur(260) or state_cur(259); + out1029 <= + state_cur(300); + out137 <= + state_cur(19) or state_cur(18); + out515 <= + state_cur(136); + out991 <= + state_cur(282); + out1375 <= + state_cur(468); + out957 <= + state_cur(271); + out264 <= + state_cur(430) or state_cur(52) or state_cur(51); + out1262 <= + state_cur(421); + out663 <= + state_cur(173); + out1111 <= + state_cur(343); + out119 <= + state_cur(15); + out998 <= + state_cur(286); + out731 <= + state_cur(206); + out1366 <= + state_cur(466); + out320 <= + state_cur(453) or state_cur(131) or state_cur(70); + out208 <= + state_cur(38); + out994 <= + state_cur(283); + out136 <= + state_cur(18); + out1145 <= + state_cur(363); + out1126 <= + state_cur(353); + out478 <= + state_cur(124); + out753 <= + state_cur(211); + out1141 <= + state_cur(362); + out951 <= + state_cur(269); + out370 <= + state_cur(89); + out259 <= + state_cur(57) or state_cur(50); + out332 <= + state_cur(72); + out1370 <= + state_cur(472) or state_cur(468); + out281 <= + state_cur(58); + out234 <= + state_cur(429) or state_cur(426) or state_cur(379) or state_cur(188) or state_cur(49) or state_cur(48) or state_cur(42); + out314 <= + state_cur(68); + out1185 <= + state_cur(385); + out1353 <= + state_cur(459); + out907 <= + state_cur(257); + out1258 <= + state_cur(420); + out698 <= + state_cur(191); + out212 <= + state_cur(40); + out468 <= + state_cur(467) or state_cur(377) or state_cur(305) or state_cur(122); + out876 <= + state_cur(245); + out498 <= + state_cur(129); + out251 <= + state_cur(379) or state_cur(48); + out1009 <= + state_cur(291); + out656 <= + state_cur(168); + out612 <= + state_cur(163); + out177 <= + state_cur(30); + out944 <= + state_cur(266); + out894 <= + state_cur(255); + out928 <= + state_cur(261) or state_cur(260); + out267 <= + state_cur(52); + out384 <= + state_cur(94); + out1171 <= + state_cur(374); + out815 <= + state_cur(234); + out230 <= + state_cur(260) or state_cur(259) or state_cur(57) or state_cur(41); + out739 <= + state_cur(365) or state_cur(207); + out88 <= + state_cur(467) or state_cur(465) or state_cur(425) or state_cur(354) or state_cur(348) or state_cur(317) or state_cur(312) or state_cur(311) or + state_cur(310) or state_cur(194) or state_cur(193) or state_cur(185) or state_cur(183) or state_cur(176) or state_cur(171) or state_cur(147) or + state_cur(146) or state_cur(140) or state_cur(127) or state_cur(124) or state_cur(122) or state_cur(115) or state_cur(96) or state_cur(87) or + state_cur(21) or state_cur(10); + out997 <= + state_cur(285); + out1362 <= + state_cur(462); + out806 <= + state_cur(231); + out1037 <= + state_cur(304); + out1147 <= + state_cur(447) or state_cur(363); + out1253 <= + state_cur(471) or state_cur(470) or state_cur(458) or state_cur(418); + out1169 <= + state_cur(373); + out316 <= + state_cur(70); + out317 <= + state_cur(131) or state_cur(123) or state_cur(81) or state_cur(77) or state_cur(75) or state_cur(71) or state_cur(70); + out133 <= + state_cur(371) or state_cur(362) or state_cur(107) or state_cur(95) or state_cur(83) or state_cur(16); + out1252 <= + state_cur(418); + out1096 <= + state_cur(333); + out186 <= + state_cur(32); + out1346 <= + state_cur(453); + out1146 <= + state_cur(363); + out363 <= + state_cur(87); + out887 <= + state_cur(254); + out659 <= + state_cur(190) or state_cur(169); + out661 <= + state_cur(171); + out346 <= + state_cur(79); + out270 <= + state_cur(54); + out1363 <= + state_cur(463); + out886 <= + state_cur(253); + out1341 <= + state_cur(451); + out92 <= + state_cur(11); + out1213 <= + state_cur(390); + out324 <= + state_cur(71); + out578 <= + state_cur(156); + out344 <= + state_cur(77); + out929 <= + state_cur(260); + out355 <= + state_cur(84); + out953 <= + state_cur(270); + out146 <= + state_cur(324) or state_cur(261) or state_cur(20); + out1365 <= + state_cur(465); + out348 <= + state_cur(80); + out358 <= + state_cur(85); + out513 <= + state_cur(135); + out1217 <= + state_cur(391); + out305 <= + state_cur(67) or state_cur(65); + out903 <= + state_cur(461) or state_cur(257); + out239 <= + state_cur(44); + out497 <= + state_cur(134) or state_cur(129) or state_cur(128); + out1337 <= + state_cur(450); + out861 <= + state_cur(247) or state_cur(239); + out448 <= + state_cur(114); + out1070 <= + state_cur(308); + out527 <= + state_cur(140); + out247 <= + state_cur(47); + out1091 <= + state_cur(327); + out496 <= + state_cur(128); + out328 <= + state_cur(432) or state_cur(273) or state_cur(71); + out1186 <= + state_cur(386); + out1309 <= + state_cur(441); + out526 <= + state_cur(161) or state_cur(139); + out199 <= + state_cur(35); + out154 <= + state_cur(435) or state_cur(253) or state_cur(133) or state_cur(23); + out1243 <= + state_cur(410); + out55 <= + state_cur(377) or state_cur(306) or state_cur(305) or state_cur(4); + out1082 <= + state_cur(313); + out240 <= + state_cur(49) or state_cur(44); + out1320 <= + state_cur(445); + out458 <= + state_cur(118); + out879 <= + state_cur(247); + out936 <= + state_cur(264) or state_cur(263) or state_cur(262); + out84 <= + state_cur(10); + out1221 <= + state_cur(423) or state_cur(397) or state_cur(395) or state_cur(392); + out1003 <= + state_cur(288); + out192 <= + state_cur(42) or state_cur(34); + out692 <= + state_cur(188); + out852 <= + state_cur(237); + out275 <= + state_cur(56); + out775 <= + state_cur(440) or state_cur(220); + out412 <= + state_cur(99); + out306 <= + state_cur(66); + out1013 <= + state_cur(293); + out1235 <= + state_cur(400); + out577 <= + state_cur(184) or state_cur(163) or state_cur(154); + out1166 <= + state_cur(371); + out432 <= + state_cur(108); + out1327 <= + state_cur(448); + out1378 <= + state_cur(469); + out49 <= + state_cur(306) or state_cur(171) or state_cur(146) or state_cur(4); + out65 <= + state_cur(459) or state_cur(14) or state_cur(7) or state_cur(5); + out246 <= + state_cur(48) or state_cur(46); + out939 <= + state_cur(264); + out504 <= + state_cur(132); + out667 <= + state_cur(444) or state_cur(441) or state_cur(174); + out683 <= + state_cur(182); + out686 <= + state_cur(183); + + -- Assignment of buffered outputs + + out1057 <= out1057_buf; + out59 <= out59_buf; + out447 <= out447_buf; + out157 <= out157_buf; + out450 <= out450_buf; + out1012 <= out1012_buf; + out1072 <= out1072_buf; + out999 <= out999_buf; + out437 <= out437_buf; + out415 <= out415_buf; + out426 <= out426_buf; + out375 <= out375_buf; + out704 <= out704_buf; + out973 <= out973_buf; + out11 <= out11_buf; + out549 <= out549_buf; + out453 <= out453_buf; + out1231 <= out1231_buf; + out87 <= out87_buf; + out401 <= out401_buf; + out990 <= out990_buf; + out378 <= out378_buf; + out1302 <= out1302_buf; + out27 <= out27_buf; + out569 <= out569_buf; + out1030 <= out1030_buf; + out537 <= out537_buf; + out77 <= out77_buf; + out1318 <= out1318_buf; + out533 <= out533_buf; + out32 <= out32_buf; + out1027 <= out1027_buf; + out599 <= out599_buf; + out668 <= out668_buf; + out568 <= out568_buf; + out225 <= out225_buf; + out700 <= out700_buf; + out638 <= out638_buf; + out670 <= out670_buf; + out433 <= out433_buf; + out896 <= out896_buf; + out575 <= out575_buf; + out428 <= out428_buf; + out72 <= out72_buf; + out404 <= out404_buf; + out98 <= out98_buf; + out67 <= out67_buf; + out635 <= out635_buf; + out381 <= out381_buf; + out222 <= out222_buf; + out339 <= out339_buf; + out268 <= out268_buf; + out419 <= out419_buf; + out559 <= out559_buf; + out1002 <= out1002_buf; + out1006 <= out1006_buf; + out276 <= out276_buf; + out205 <= out205_buf; + out943 <= out943_buf; + out1080 <= out1080_buf; + out408 <= out408_buf; + out252 <= out252_buf; + out71 <= out71_buf; + out672 <= out672_buf; + out357 <= out357_buf; + out441 <= out441_buf; + out1084 <= out1084_buf; + out144 <= out144_buf; + out574 <= out574_buf; + out210 <= out210_buf; + out128 <= out128_buf; + out360 <= out360_buf; + out948 <= out948_buf; + out506 <= out506_buf; + out207 <= out207_buf; + out1083 <= out1083_buf; + out491 <= out491_buf; + out4 <= out4_buf; + out784 <= out784_buf; + out3 <= out3_buf; + out746 <= out746_buf; + out528 <= out528_buf; + out372 <= out372_buf; + out418 <= out418_buf; + out708 <= out708_buf; + out706 <= out706_buf; + out445 <= out445_buf; + out1021 <= out1021_buf; + out405 <= out405_buf; + out764 <= out764_buf; + out581 <= out581_buf; + out776 <= out776_buf; + out213 <= out213_buf; + out674 <= out674_buf; + out1326 <= out1326_buf; + out334 <= out334_buf; + out843 <= out843_buf; + out175 <= out175_buf; + out1036 <= out1036_buf; + out1015 <= out1015_buf; + out236 <= out236_buf; + out395 <= out395_buf; + out1340 <= out1340_buf; + out993 <= out993_buf; + out356 <= out356_buf; + out273 <= out273_buf; + out403 <= out403_buf; + out286 <= out286_buf; + out364 <= out364_buf; + out697 <= out697_buf; + out283 <= out283_buf; + out282 <= out282_buf; + out1319 <= out1319_buf; + out409 <= out409_buf; + out1092 <= out1092_buf; + out1075 <= out1075_buf; + out925 <= out925_buf; + out78 <= out78_buf; + out1089 <= out1089_buf; + out362 <= out362_buf; + out982 <= out982_buf; + out979 <= out979_buf; + out952 <= out952_buf; + out1109 <= out1109_buf; + out16 <= out16_buf; + out703 <= out703_buf; + out371 <= out371_buf; + out956 <= out956_buf; + out1107 <= out1107_buf; + out1033 <= out1033_buf; + out148 <= out148_buf; + out351 <= out351_buf; + out740 <= out740_buf; + out391 <= out391_buf; + out129 <= out129_buf; + out338 <= out338_buf; + out425 <= out425_buf; + out1078 <= out1078_buf; + out349 <= out349_buf; + out590 <= out590_buf; + out325 <= out325_buf; + out112 <= out112_buf; + out224 <= out224_buf; + out1220 <= out1220_buf; + out1250 <= out1250_buf; + out365 <= out365_buf; + out699 <= out699_buf; + out488 <= out488_buf; + out1069 <= out1069_buf; + out530 <= out530_buf; + out326 <= out326_buf; + out602 <= out602_buf; + out83 <= out83_buf; + out311 <= out311_buf; + out253 <= out253_buf; + out209 <= out209_buf; + out1240 <= out1240_buf; + out1018 <= out1018_buf; + out1152 <= out1152_buf; + out1236 <= out1236_buf; + out130 <= out130_buf; + out567 <= out567_buf; + out646 <= out646_buf; + +end architecture; + diff --git a/testsuite/gna/bug040/huff_make_dhuff_tb_ac_huffcode.vhd b/testsuite/gna/bug040/huff_make_dhuff_tb_ac_huffcode.vhd new file mode 100644 index 000000000..ba5b0ae6d --- /dev/null +++ b/testsuite/gna/bug040/huff_make_dhuff_tb_ac_huffcode.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity huff_make_dhuff_tb_ac_huffcode is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(8 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(8 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end huff_make_dhuff_tb_ac_huffcode; +architecture augh of huff_make_dhuff_tb_ac_huffcode is + + -- Embedded RAM + + type ram_type is array (0 to 256) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/huff_make_dhuff_tb_ac_huffsize.vhd b/testsuite/gna/bug040/huff_make_dhuff_tb_ac_huffsize.vhd new file mode 100644 index 000000000..383a69fc3 --- /dev/null +++ b/testsuite/gna/bug040/huff_make_dhuff_tb_ac_huffsize.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity huff_make_dhuff_tb_ac_huffsize is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(8 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(8 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end huff_make_dhuff_tb_ac_huffsize; +architecture augh of huff_make_dhuff_tb_ac_huffsize is + + -- Embedded RAM + + type ram_type is array (0 to 256) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/huff_make_dhuff_tb_dc_huffcode.vhd b/testsuite/gna/bug040/huff_make_dhuff_tb_dc_huffcode.vhd new file mode 100644 index 000000000..bbeba08fc --- /dev/null +++ b/testsuite/gna/bug040/huff_make_dhuff_tb_dc_huffcode.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity huff_make_dhuff_tb_dc_huffcode is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(8 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(8 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end huff_make_dhuff_tb_dc_huffcode; +architecture augh of huff_make_dhuff_tb_dc_huffcode is + + -- Embedded RAM + + type ram_type is array (0 to 256) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/huff_make_dhuff_tb_dc_huffsize.vhd b/testsuite/gna/bug040/huff_make_dhuff_tb_dc_huffsize.vhd new file mode 100644 index 000000000..8c71b13b5 --- /dev/null +++ b/testsuite/gna/bug040/huff_make_dhuff_tb_dc_huffsize.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity huff_make_dhuff_tb_dc_huffsize is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(8 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(8 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end huff_make_dhuff_tb_dc_huffsize; +architecture augh of huff_make_dhuff_tb_dc_huffsize is + + -- Embedded RAM + + type ram_type is array (0 to 256) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/huffbuff.vhd b/testsuite/gna/bug040/huffbuff.vhd new file mode 100644 index 000000000..e7af50e4c --- /dev/null +++ b/testsuite/gna/bug040/huffbuff.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity huffbuff is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(7 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(7 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end huffbuff; +architecture augh of huffbuff is + + -- Embedded RAM + + type ram_type is array (0 to 191) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 192 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/idctbuff.vhd b/testsuite/gna/bug040/idctbuff.vhd new file mode 100644 index 000000000..07fb427cd --- /dev/null +++ b/testsuite/gna/bug040/idctbuff.vhd @@ -0,0 +1,71 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity idctbuff is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(8 downto 0); + clk : in std_logic; + ra2_data : out std_logic_vector(31 downto 0); + ra2_addr : in std_logic_vector(8 downto 0); + ra1_data : out std_logic_vector(31 downto 0); + ra1_addr : in std_logic_vector(8 downto 0); + ra0_addr : in std_logic_vector(8 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end idctbuff; +architecture augh of idctbuff is + + -- Embedded RAM + + type ram_type is array (0 to 383) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra1_data <= ram( to_integer(ra1_addr) ) when to_integer(ra1_addr) < 384 else (others => '-'); + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 384 else (others => '-'); + ra2_data <= ram( to_integer(ra2_addr) ) when to_integer(ra2_addr) < 384 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/izigzag_index.vhd b/testsuite/gna/bug040/izigzag_index.vhd new file mode 100644 index 000000000..ba0fb3feb --- /dev/null +++ b/testsuite/gna/bug040/izigzag_index.vhd @@ -0,0 +1,55 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity izigzag_index is + port ( + clk : in std_logic; + ra0_addr : in std_logic_vector(5 downto 0); + ra0_data : out std_logic_vector(5 downto 0) + ); +end izigzag_index; +architecture augh of izigzag_index is + + -- Embedded RAM + + type ram_type is array (0 to 63) of std_logic_vector(5 downto 0); + signal ram : ram_type := ( + "000000", "000001", "001000", "010000", "001001", "000010", "000011", "001010", "010001", "011000", "100000", "011001", + "010010", "001011", "000100", "000101", "001100", "010011", "011010", "100001", "101000", "110000", "101001", "100010", + "011011", "010100", "001101", "000110", "000111", "001110", "010101", "011100", "100011", "101010", "110001", "111000", + "111001", "110010", "101011", "100100", "011101", "010110", "001111", "010111", "011110", "100101", "101100", "110011", + "111010", "111011", "110100", "101101", "100110", "011111", "100111", "101110", "110101", "111100", "111101", "110110", + "101111", "110111", "111110", "111111" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- The component is a ROM. + -- There is no Write side. + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/jpegfilebuf.vhd b/testsuite/gna/bug040/jpegfilebuf.vhd new file mode 100644 index 000000000..e41837f68 --- /dev/null +++ b/testsuite/gna/bug040/jpegfilebuf.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity jpegfilebuf is + port ( + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic_vector(12 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(12 downto 0); + ra0_data : out std_logic_vector(7 downto 0); + wa0_en : in std_logic + ); +end jpegfilebuf; +architecture augh of jpegfilebuf is + + -- Embedded RAM + + type ram_type is array (0 to 5309) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 5310 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/lmask.vhd b/testsuite/gna/bug040/lmask.vhd new file mode 100644 index 000000000..b12bb1b02 --- /dev/null +++ b/testsuite/gna/bug040/lmask.vhd @@ -0,0 +1,60 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity lmask is + port ( + clk : in std_logic; + ra0_addr : in std_logic_vector(4 downto 0); + ra0_data : out std_logic_vector(31 downto 0) + ); +end lmask; +architecture augh of lmask is + + -- Embedded RAM + + type ram_type is array (0 to 31) of std_logic_vector(31 downto 0); + signal ram : ram_type := ( + "00000000000000000000000000000001", "00000000000000000000000000000011", "00000000000000000000000000000111", + "00000000000000000000000000001111", "00000000000000000000000000011111", "00000000000000000000000000111111", + "00000000000000000000000001111111", "00000000000000000000000011111111", "00000000000000000000000111111111", + "00000000000000000000001111111111", "00000000000000000000011111111111", "00000000000000000000111111111111", + "00000000000000000001111111111111", "00000000000000000011111111111111", "00000000000000000111111111111111", + "00000000000000001111111111111111", "00000000000000011111111111111111", "00000000000000111111111111111111", + "00000000000001111111111111111111", "00000000000011111111111111111111", "00000000000111111111111111111111", + "00000000001111111111111111111111", "00000000011111111111111111111111", "00000000111111111111111111111111", + "00000001111111111111111111111111", "00000011111111111111111111111111", "00000111111111111111111111111111", + "00001111111111111111111111111111", "00011111111111111111111111111111", "00111111111111111111111111111111", + "01111111111111111111111111111111", "11111111111111111111111111111111" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- The component is a ROM. + -- There is no Write side. + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/mul_209.vhd b/testsuite/gna/bug040/mul_209.vhd new file mode 100644 index 000000000..f3c162063 --- /dev/null +++ b/testsuite/gna/bug040/mul_209.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity mul_209 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); +end mul_209; + +architecture augh of mul_209 is + + signal tmp_res : signed(63 downto 0); + +begin + + -- The actual multiplication + tmp_res <= signed(in_a) * signed(in_b); + + -- Set the output + output <= std_logic_vector(tmp_res(40 downto 0)); + +end architecture; diff --git a/testsuite/gna/bug040/mul_210.vhd b/testsuite/gna/bug040/mul_210.vhd new file mode 100644 index 000000000..5fe047052 --- /dev/null +++ b/testsuite/gna/bug040/mul_210.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity mul_210 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); +end mul_210; + +architecture augh of mul_210 is + + signal tmp_res : signed(63 downto 0); + +begin + + -- The actual multiplication + tmp_res <= signed(in_a) * signed(in_b); + + -- Set the output + output <= std_logic_vector(tmp_res(40 downto 0)); + +end architecture; diff --git a/testsuite/gna/bug040/mul_213.vhd b/testsuite/gna/bug040/mul_213.vhd new file mode 100644 index 000000000..7eccb59e1 --- /dev/null +++ b/testsuite/gna/bug040/mul_213.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity mul_213 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); +end mul_213; + +architecture augh of mul_213 is + + signal tmp_res : signed(63 downto 0); + +begin + + -- The actual multiplication + tmp_res <= signed(in_a) * signed(in_b); + + -- Set the output + output <= std_logic_vector(tmp_res(40 downto 0)); + +end architecture; diff --git a/testsuite/gna/bug040/mul_214.vhd b/testsuite/gna/bug040/mul_214.vhd new file mode 100644 index 000000000..9de730133 --- /dev/null +++ b/testsuite/gna/bug040/mul_214.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity mul_214 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); +end mul_214; + +architecture augh of mul_214 is + + signal tmp_res : signed(63 downto 0); + +begin + + -- The actual multiplication + tmp_res <= signed(in_a) * signed(in_b); + + -- Set the output + output <= std_logic_vector(tmp_res(40 downto 0)); + +end architecture; diff --git a/testsuite/gna/bug040/mul_215.vhd b/testsuite/gna/bug040/mul_215.vhd new file mode 100644 index 000000000..cd241e4f0 --- /dev/null +++ b/testsuite/gna/bug040/mul_215.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity mul_215 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); +end mul_215; + +architecture augh of mul_215 is + + signal tmp_res : signed(63 downto 0); + +begin + + -- The actual multiplication + tmp_res <= signed(in_a) * signed(in_b); + + -- Set the output + output <= std_logic_vector(tmp_res(40 downto 0)); + +end architecture; diff --git a/testsuite/gna/bug040/mul_216.vhd b/testsuite/gna/bug040/mul_216.vhd new file mode 100644 index 000000000..e9ad0d7eb --- /dev/null +++ b/testsuite/gna/bug040/mul_216.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity mul_216 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); +end mul_216; + +architecture augh of mul_216 is + + signal tmp_res : signed(63 downto 0); + +begin + + -- The actual multiplication + tmp_res <= signed(in_a) * signed(in_b); + + -- Set the output + output <= std_logic_vector(tmp_res(40 downto 0)); + +end architecture; diff --git a/testsuite/gna/bug040/mul_222.vhd b/testsuite/gna/bug040/mul_222.vhd new file mode 100644 index 000000000..d96c64c9a --- /dev/null +++ b/testsuite/gna/bug040/mul_222.vhd @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity mul_222 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); +end mul_222; + +architecture augh of mul_222 is + + signal tmp_res : signed(63 downto 0); + +begin + + -- The actual multiplication + tmp_res <= signed(in_a) * signed(in_b); + + -- Set the output + output <= std_logic_vector(tmp_res(40 downto 0)); + +end architecture; diff --git a/testsuite/gna/bug040/muxb_784.vhd b/testsuite/gna/bug040/muxb_784.vhd new file mode 100644 index 000000000..02ee063d1 --- /dev/null +++ b/testsuite/gna/bug040/muxb_784.vhd @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity muxb_784 is + port ( + in_sel : in std_logic; + out_data : out std_logic_vector(31 downto 0); + in_data0 : in std_logic_vector(31 downto 0); + in_data1 : in std_logic_vector(31 downto 0) + ); +end muxb_784; + +architecture augh of muxb_784 is +begin + + out_data <= in_data0 when in_sel = '0' else in_data1; + +end architecture; + diff --git a/testsuite/gna/bug040/outdata_comp_buf.vhd b/testsuite/gna/bug040/outdata_comp_buf.vhd new file mode 100644 index 000000000..7d9531a8c --- /dev/null +++ b/testsuite/gna/bug040/outdata_comp_buf.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity outdata_comp_buf is + port ( + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic_vector(14 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(14 downto 0); + ra0_data : out std_logic_vector(7 downto 0); + wa0_en : in std_logic + ); +end outdata_comp_buf; +architecture augh of outdata_comp_buf is + + -- Embedded RAM + + type ram_type is array (0 to 24575) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 24576 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/outdata_comp_hpos.vhd b/testsuite/gna/bug040/outdata_comp_hpos.vhd new file mode 100644 index 000000000..6d5f9dda5 --- /dev/null +++ b/testsuite/gna/bug040/outdata_comp_hpos.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity outdata_comp_hpos is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end outdata_comp_hpos; +architecture augh of outdata_comp_hpos is + + -- Embedded RAM + + type ram_type is array (0 to 2) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/outdata_comp_vpos.vhd b/testsuite/gna/bug040/outdata_comp_vpos.vhd new file mode 100644 index 000000000..24dc93183 --- /dev/null +++ b/testsuite/gna/bug040/outdata_comp_vpos.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity outdata_comp_vpos is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end outdata_comp_vpos; +architecture augh of outdata_comp_vpos is + + -- Embedded RAM + + type ram_type is array (0 to 2) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_maxcode.vhd b/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_maxcode.vhd new file mode 100644 index 000000000..2b3c32b34 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_maxcode.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_ac_dhuff_tbl_maxcode is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_ac_dhuff_tbl_maxcode; +architecture augh of p_jinfo_ac_dhuff_tbl_maxcode is + + -- Embedded RAM + + type ram_type is array (0 to 127) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_mincode.vhd b/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_mincode.vhd new file mode 100644 index 000000000..ed5265173 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_mincode.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_ac_dhuff_tbl_mincode is + port ( + wa0_data : in std_logic_vector(8 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(8 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_ac_dhuff_tbl_mincode; +architecture augh of p_jinfo_ac_dhuff_tbl_mincode is + + -- Embedded RAM + + type ram_type is array (0 to 127) of std_logic_vector(8 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_ml.vhd b/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_ml.vhd new file mode 100644 index 000000000..719975054 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_ml.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_ac_dhuff_tbl_ml is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic; + clk : in std_logic; + ra0_addr : in std_logic; + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_ac_dhuff_tbl_ml; +architecture augh of p_jinfo_ac_dhuff_tbl_ml is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_valptr.vhd b/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_valptr.vhd new file mode 100644 index 000000000..67847cb73 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_valptr.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_ac_dhuff_tbl_valptr is + port ( + wa0_data : in std_logic_vector(8 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(8 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_ac_dhuff_tbl_valptr; +architecture augh of p_jinfo_ac_dhuff_tbl_valptr is + + -- Embedded RAM + + type ram_type is array (0 to 127) of std_logic_vector(8 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_ac_xhuff_tbl_bits.vhd b/testsuite/gna/bug040/p_jinfo_ac_xhuff_tbl_bits.vhd new file mode 100644 index 000000000..6b88ef8b6 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_ac_xhuff_tbl_bits.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_ac_xhuff_tbl_bits is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_ac_xhuff_tbl_bits; +architecture augh of p_jinfo_ac_xhuff_tbl_bits is + + -- Embedded RAM + + type ram_type is array (0 to 127) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_ac_xhuff_tbl_huffval.vhd b/testsuite/gna/bug040/p_jinfo_ac_xhuff_tbl_huffval.vhd new file mode 100644 index 000000000..2af663c9b --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_ac_xhuff_tbl_huffval.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_ac_xhuff_tbl_huffval is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(9 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(9 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_ac_xhuff_tbl_huffval; +architecture augh of p_jinfo_ac_xhuff_tbl_huffval is + + -- Embedded RAM + + type ram_type is array (0 to 1023) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_comps_info_dc_tbl_no.vhd b/testsuite/gna/bug040/p_jinfo_comps_info_dc_tbl_no.vhd new file mode 100644 index 000000000..3330573c2 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_comps_info_dc_tbl_no.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_comps_info_dc_tbl_no is + port ( + wa0_data : in std_logic; + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic; + wa0_en : in std_logic + ); +end p_jinfo_comps_info_dc_tbl_no; +architecture augh of p_jinfo_comps_info_dc_tbl_no is + + -- Embedded RAM + + type ram_type is array (0 to 2) of std_logic; + signal ram : ram_type := (others => '0'); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else '-'; + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_comps_info_h_samp_factor.vhd b/testsuite/gna/bug040/p_jinfo_comps_info_h_samp_factor.vhd new file mode 100644 index 000000000..1abd186e9 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_comps_info_h_samp_factor.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_comps_info_h_samp_factor is + port ( + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic_vector(7 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_comps_info_h_samp_factor; +architecture augh of p_jinfo_comps_info_h_samp_factor is + + -- Embedded RAM + + type ram_type is array (0 to 2) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_comps_info_id.vhd b/testsuite/gna/bug040/p_jinfo_comps_info_id.vhd new file mode 100644 index 000000000..f192f6116 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_comps_info_id.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_comps_info_id is + port ( + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic_vector(7 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_comps_info_id; +architecture augh of p_jinfo_comps_info_id is + + -- Embedded RAM + + type ram_type is array (0 to 2) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_comps_info_quant_tbl_no.vhd b/testsuite/gna/bug040/p_jinfo_comps_info_quant_tbl_no.vhd new file mode 100644 index 000000000..1977e9cab --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_comps_info_quant_tbl_no.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_comps_info_quant_tbl_no is + port ( + wa0_data : in std_logic_vector(1 downto 0); + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic_vector(1 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_comps_info_quant_tbl_no; +architecture augh of p_jinfo_comps_info_quant_tbl_no is + + -- Embedded RAM + + type ram_type is array (0 to 2) of std_logic_vector(1 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-'); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_maxcode.vhd b/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_maxcode.vhd new file mode 100644 index 000000000..738d83674 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_maxcode.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_dc_dhuff_tbl_maxcode is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_dc_dhuff_tbl_maxcode; +architecture augh of p_jinfo_dc_dhuff_tbl_maxcode is + + -- Embedded RAM + + type ram_type is array (0 to 127) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_mincode.vhd b/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_mincode.vhd new file mode 100644 index 000000000..4dc780de3 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_mincode.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_dc_dhuff_tbl_mincode is + port ( + wa0_data : in std_logic_vector(8 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(8 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_dc_dhuff_tbl_mincode; +architecture augh of p_jinfo_dc_dhuff_tbl_mincode is + + -- Embedded RAM + + type ram_type is array (0 to 127) of std_logic_vector(8 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_ml.vhd b/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_ml.vhd new file mode 100644 index 000000000..c3c2bae87 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_ml.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_dc_dhuff_tbl_ml is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic; + clk : in std_logic; + ra0_addr : in std_logic; + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_dc_dhuff_tbl_ml; +architecture augh of p_jinfo_dc_dhuff_tbl_ml is + + -- Embedded RAM + + type ram_type is array (0 to 1) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_valptr.vhd b/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_valptr.vhd new file mode 100644 index 000000000..39a3fbccc --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_valptr.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_dc_dhuff_tbl_valptr is + port ( + wa0_data : in std_logic_vector(8 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(8 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_dc_dhuff_tbl_valptr; +architecture augh of p_jinfo_dc_dhuff_tbl_valptr is + + -- Embedded RAM + + type ram_type is array (0 to 127) of std_logic_vector(8 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_dc_xhuff_tbl_bits.vhd b/testsuite/gna/bug040/p_jinfo_dc_xhuff_tbl_bits.vhd new file mode 100644 index 000000000..17ad2dce0 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_dc_xhuff_tbl_bits.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_dc_xhuff_tbl_bits is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_dc_xhuff_tbl_bits; +architecture augh of p_jinfo_dc_xhuff_tbl_bits is + + -- Embedded RAM + + type ram_type is array (0 to 127) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_dc_xhuff_tbl_huffval.vhd b/testsuite/gna/bug040/p_jinfo_dc_xhuff_tbl_huffval.vhd new file mode 100644 index 000000000..8f78cbe84 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_dc_xhuff_tbl_huffval.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_dc_xhuff_tbl_huffval is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(9 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(9 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_dc_xhuff_tbl_huffval; +architecture augh of p_jinfo_dc_xhuff_tbl_huffval is + + -- Embedded RAM + + type ram_type is array (0 to 1023) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/p_jinfo_quant_tbl_quantval.vhd b/testsuite/gna/bug040/p_jinfo_quant_tbl_quantval.vhd new file mode 100644 index 000000000..bba5f00d9 --- /dev/null +++ b/testsuite/gna/bug040/p_jinfo_quant_tbl_quantval.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity p_jinfo_quant_tbl_quantval is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(7 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(7 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end p_jinfo_quant_tbl_quantval; +architecture augh of p_jinfo_quant_tbl_quantval is + + -- Embedded RAM + + type ram_type is array (0 to 255) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/quantbuff.vhd b/testsuite/gna/bug040/quantbuff.vhd new file mode 100644 index 000000000..ce7cfa594 --- /dev/null +++ b/testsuite/gna/bug040/quantbuff.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity quantbuff is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(5 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(5 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); +end quantbuff; +architecture augh of quantbuff is + + -- Embedded RAM + + type ram_type is array (0 to 63) of std_logic_vector(31 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/rgb_buf.vhd b/testsuite/gna/bug040/rgb_buf.vhd new file mode 100644 index 000000000..0dbe0fbb5 --- /dev/null +++ b/testsuite/gna/bug040/rgb_buf.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity rgb_buf is + port ( + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic_vector(9 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(9 downto 0); + ra0_data : out std_logic_vector(7 downto 0); + wa0_en : in std_logic + ); +end rgb_buf; +architecture augh of rgb_buf is + + -- Embedded RAM + + type ram_type is array (0 to 1023) of std_logic_vector(7 downto 0); + signal ram : ram_type := (others => (others => '0')); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Sequential process + -- It handles the Writes + + process (clk) + begin + if rising_edge(clk) then + + -- Write to the RAM + -- Note: there should be only one port. + + if wa0_en = '1' then + ram( to_integer(wa0_addr) ) <= wa0_data; + end if; + + end if; + end process; + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; diff --git a/testsuite/gna/bug040/shl_211.vhd b/testsuite/gna/bug040/shl_211.vhd new file mode 100644 index 000000000..b675a6df2 --- /dev/null +++ b/testsuite/gna/bug040/shl_211.vhd @@ -0,0 +1,46 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity shl_211 is + port ( + output : out std_logic_vector(31 downto 0); + input : in std_logic_vector(31 downto 0); + shift : in std_logic_vector(5 downto 0); + padding : in std_logic + ); +end shl_211; + +architecture augh of shl_211 is + + signal tmp_padding : std_logic; + signal tmp_result : std_logic_vector(32 downto 0); + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Temporary signals + tmp_padding <= padding; + tmp_result <= std_logic_vector(shift_left( unsigned(input & padding), to_integer(shift) )); + + -- The output + output <= tmp_result(32 downto 1); + +end architecture; diff --git a/testsuite/gna/bug040/shr_212.vhd b/testsuite/gna/bug040/shr_212.vhd new file mode 100644 index 000000000..f18b92bf1 --- /dev/null +++ b/testsuite/gna/bug040/shr_212.vhd @@ -0,0 +1,46 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity shr_212 is + port ( + output : out std_logic_vector(31 downto 0); + input : in std_logic_vector(31 downto 0); + shift : in std_logic_vector(5 downto 0); + padding : in std_logic + ); +end shr_212; + +architecture augh of shr_212 is + + signal tmp_padding : std_logic; + signal tmp_result : std_logic_vector(32 downto 0); + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- Temporary signals + tmp_padding <= padding; + tmp_result <= std_logic_vector(shift_right( unsigned(padding & input), to_integer(shift) )); + + -- The output + output <= tmp_result(31 downto 0); + +end architecture; diff --git a/testsuite/gna/bug040/sub_205.vhd b/testsuite/gna/bug040/sub_205.vhd new file mode 100644 index 000000000..e219f407e --- /dev/null +++ b/testsuite/gna/bug040/sub_205.vhd @@ -0,0 +1,70 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_205 is + port ( + gt : out std_logic; + ge : out std_logic; + lt : out std_logic; + le : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); +end sub_205; + +architecture augh of sub_205 is + + signal carry_inA : std_logic_vector(42 downto 0); + signal carry_inB : std_logic_vector(42 downto 0); + signal carry_res : std_logic_vector(42 downto 0); + + -- Signals to generate the comparison outputs + signal msb_abr : std_logic_vector(2 downto 0); + signal tmp_sign : std_logic; + signal tmp_eq : std_logic; + signal tmp_le : std_logic; + signal tmp_ge : std_logic; + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(41 downto 1); + + -- Other comparison outputs + + -- Temporary signals + msb_abr <= in_a(40) & in_b(40) & carry_res(41); + tmp_sign <= sign; + tmp_eq <= '1' when in_a = in_b else '0'; + + tmp_le <= + tmp_eq when msb_abr = "000" or msb_abr = "110" else + '1' when msb_abr = "001" or msb_abr = "111" else + '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else + '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else + '0'; + + tmp_ge <= + '1' when msb_abr = "000" or msb_abr = "110" else + '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else + '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else + '0'; + + gt <= not(tmp_le); + ge <= tmp_ge; + lt <= not(tmp_ge); + le <= tmp_le; + +end architecture; diff --git a/testsuite/gna/bug040/sub_206.vhd b/testsuite/gna/bug040/sub_206.vhd new file mode 100644 index 000000000..01549ed0e --- /dev/null +++ b/testsuite/gna/bug040/sub_206.vhd @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_206 is + port ( + gt : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); +end sub_206; + +architecture augh of sub_206 is + + signal carry_inA : std_logic_vector(42 downto 0); + signal carry_inB : std_logic_vector(42 downto 0); + signal carry_res : std_logic_vector(42 downto 0); + + -- Signals to generate the comparison outputs + signal msb_abr : std_logic_vector(2 downto 0); + signal tmp_sign : std_logic; + signal tmp_eq : std_logic; + signal tmp_le : std_logic; + signal tmp_ge : std_logic; + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(41 downto 1); + + -- Other comparison outputs + + -- Temporary signals + msb_abr <= in_a(40) & in_b(40) & carry_res(41); + tmp_sign <= sign; + tmp_eq <= '1' when in_a = in_b else '0'; + + tmp_le <= + tmp_eq when msb_abr = "000" or msb_abr = "110" else + '1' when msb_abr = "001" or msb_abr = "111" else + '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else + '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else + '0'; + + tmp_ge <= + '1' when msb_abr = "000" or msb_abr = "110" else + '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else + '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else + '0'; + + gt <= not(tmp_le); + +end architecture; diff --git a/testsuite/gna/bug040/sub_207.vhd b/testsuite/gna/bug040/sub_207.vhd new file mode 100644 index 000000000..fd695500b --- /dev/null +++ b/testsuite/gna/bug040/sub_207.vhd @@ -0,0 +1,66 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_207 is + port ( + ge : out std_logic; + le : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); +end sub_207; + +architecture augh of sub_207 is + + signal carry_inA : std_logic_vector(42 downto 0); + signal carry_inB : std_logic_vector(42 downto 0); + signal carry_res : std_logic_vector(42 downto 0); + + -- Signals to generate the comparison outputs + signal msb_abr : std_logic_vector(2 downto 0); + signal tmp_sign : std_logic; + signal tmp_eq : std_logic; + signal tmp_le : std_logic; + signal tmp_ge : std_logic; + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(41 downto 1); + + -- Other comparison outputs + + -- Temporary signals + msb_abr <= in_a(40) & in_b(40) & carry_res(41); + tmp_sign <= sign; + tmp_eq <= '1' when in_a = in_b else '0'; + + tmp_le <= + tmp_eq when msb_abr = "000" or msb_abr = "110" else + '1' when msb_abr = "001" or msb_abr = "111" else + '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else + '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else + '0'; + + tmp_ge <= + '1' when msb_abr = "000" or msb_abr = "110" else + '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else + '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else + '0'; + + ge <= tmp_ge; + le <= tmp_le; + +end architecture; diff --git a/testsuite/gna/bug040/sub_208.vhd b/testsuite/gna/bug040/sub_208.vhd new file mode 100644 index 000000000..bb32c85fe --- /dev/null +++ b/testsuite/gna/bug040/sub_208.vhd @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_208 is + port ( + ge : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); +end sub_208; + +architecture augh of sub_208 is + + signal carry_inA : std_logic_vector(42 downto 0); + signal carry_inB : std_logic_vector(42 downto 0); + signal carry_res : std_logic_vector(42 downto 0); + + -- Signals to generate the comparison outputs + signal msb_abr : std_logic_vector(2 downto 0); + signal tmp_sign : std_logic; + signal tmp_eq : std_logic; + signal tmp_le : std_logic; + signal tmp_ge : std_logic; + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(41 downto 1); + + -- Other comparison outputs + + -- Temporary signals + msb_abr <= in_a(40) & in_b(40) & carry_res(41); + tmp_sign <= sign; + tmp_eq <= '1' when in_a = in_b else '0'; + + tmp_le <= + tmp_eq when msb_abr = "000" or msb_abr = "110" else + '1' when msb_abr = "001" or msb_abr = "111" else + '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else + '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else + '0'; + + tmp_ge <= + '1' when msb_abr = "000" or msb_abr = "110" else + '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else + '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else + '0'; + + ge <= tmp_ge; + +end architecture; diff --git a/testsuite/gna/bug040/sub_217.vhd b/testsuite/gna/bug040/sub_217.vhd new file mode 100644 index 000000000..d9e52e6d3 --- /dev/null +++ b/testsuite/gna/bug040/sub_217.vhd @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_217 is + port ( + ge : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); +end sub_217; + +architecture augh of sub_217 is + + signal carry_inA : std_logic_vector(42 downto 0); + signal carry_inB : std_logic_vector(42 downto 0); + signal carry_res : std_logic_vector(42 downto 0); + + -- Signals to generate the comparison outputs + signal msb_abr : std_logic_vector(2 downto 0); + signal tmp_sign : std_logic; + signal tmp_eq : std_logic; + signal tmp_le : std_logic; + signal tmp_ge : std_logic; + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(41 downto 1); + + -- Other comparison outputs + + -- Temporary signals + msb_abr <= in_a(40) & in_b(40) & carry_res(41); + tmp_sign <= sign; + tmp_eq <= '1' when in_a = in_b else '0'; + + tmp_le <= + tmp_eq when msb_abr = "000" or msb_abr = "110" else + '1' when msb_abr = "001" or msb_abr = "111" else + '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else + '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else + '0'; + + tmp_ge <= + '1' when msb_abr = "000" or msb_abr = "110" else + '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else + '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else + '0'; + + ge <= tmp_ge; + +end architecture; diff --git a/testsuite/gna/bug040/sub_218.vhd b/testsuite/gna/bug040/sub_218.vhd new file mode 100644 index 000000000..e920cc952 --- /dev/null +++ b/testsuite/gna/bug040/sub_218.vhd @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_218 is + port ( + le : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); +end sub_218; + +architecture augh of sub_218 is + + signal carry_inA : std_logic_vector(42 downto 0); + signal carry_inB : std_logic_vector(42 downto 0); + signal carry_res : std_logic_vector(42 downto 0); + + -- Signals to generate the comparison outputs + signal msb_abr : std_logic_vector(2 downto 0); + signal tmp_sign : std_logic; + signal tmp_eq : std_logic; + signal tmp_le : std_logic; + signal tmp_ge : std_logic; + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(41 downto 1); + + -- Other comparison outputs + + -- Temporary signals + msb_abr <= in_a(40) & in_b(40) & carry_res(41); + tmp_sign <= sign; + tmp_eq <= '1' when in_a = in_b else '0'; + + tmp_le <= + tmp_eq when msb_abr = "000" or msb_abr = "110" else + '1' when msb_abr = "001" or msb_abr = "111" else + '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else + '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else + '0'; + + tmp_ge <= + '1' when msb_abr = "000" or msb_abr = "110" else + '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else + '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else + '0'; + + le <= tmp_le; + +end architecture; diff --git a/testsuite/gna/bug040/sub_219.vhd b/testsuite/gna/bug040/sub_219.vhd new file mode 100644 index 000000000..df2cd7df4 --- /dev/null +++ b/testsuite/gna/bug040/sub_219.vhd @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_219 is + port ( + le : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); +end sub_219; + +architecture augh of sub_219 is + + signal carry_inA : std_logic_vector(42 downto 0); + signal carry_inB : std_logic_vector(42 downto 0); + signal carry_res : std_logic_vector(42 downto 0); + + -- Signals to generate the comparison outputs + signal msb_abr : std_logic_vector(2 downto 0); + signal tmp_sign : std_logic; + signal tmp_eq : std_logic; + signal tmp_le : std_logic; + signal tmp_ge : std_logic; + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(41 downto 1); + + -- Other comparison outputs + + -- Temporary signals + msb_abr <= in_a(40) & in_b(40) & carry_res(41); + tmp_sign <= sign; + tmp_eq <= '1' when in_a = in_b else '0'; + + tmp_le <= + tmp_eq when msb_abr = "000" or msb_abr = "110" else + '1' when msb_abr = "001" or msb_abr = "111" else + '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else + '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else + '0'; + + tmp_ge <= + '1' when msb_abr = "000" or msb_abr = "110" else + '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else + '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else + '0'; + + le <= tmp_le; + +end architecture; diff --git a/testsuite/gna/bug040/sub_220.vhd b/testsuite/gna/bug040/sub_220.vhd new file mode 100644 index 000000000..fc084f2e4 --- /dev/null +++ b/testsuite/gna/bug040/sub_220.vhd @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_220 is + port ( + gt : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); +end sub_220; + +architecture augh of sub_220 is + + signal carry_inA : std_logic_vector(42 downto 0); + signal carry_inB : std_logic_vector(42 downto 0); + signal carry_res : std_logic_vector(42 downto 0); + + -- Signals to generate the comparison outputs + signal msb_abr : std_logic_vector(2 downto 0); + signal tmp_sign : std_logic; + signal tmp_eq : std_logic; + signal tmp_le : std_logic; + signal tmp_ge : std_logic; + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(41 downto 1); + + -- Other comparison outputs + + -- Temporary signals + msb_abr <= in_a(40) & in_b(40) & carry_res(41); + tmp_sign <= sign; + tmp_eq <= '1' when in_a = in_b else '0'; + + tmp_le <= + tmp_eq when msb_abr = "000" or msb_abr = "110" else + '1' when msb_abr = "001" or msb_abr = "111" else + '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else + '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else + '0'; + + tmp_ge <= + '1' when msb_abr = "000" or msb_abr = "110" else + '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else + '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else + '0'; + + gt <= not(tmp_le); + +end architecture; diff --git a/testsuite/gna/bug040/sub_221.vhd b/testsuite/gna/bug040/sub_221.vhd new file mode 100644 index 000000000..35b461cbd --- /dev/null +++ b/testsuite/gna/bug040/sub_221.vhd @@ -0,0 +1,64 @@ +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.numeric_std.all; + +entity sub_221 is + port ( + gt : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); +end sub_221; + +architecture augh of sub_221 is + + signal carry_inA : std_logic_vector(42 downto 0); + signal carry_inB : std_logic_vector(42 downto 0); + signal carry_res : std_logic_vector(42 downto 0); + + -- Signals to generate the comparison outputs + signal msb_abr : std_logic_vector(2 downto 0); + signal tmp_sign : std_logic; + signal tmp_eq : std_logic; + signal tmp_le : std_logic; + signal tmp_ge : std_logic; + +begin + + -- To handle the CI input, the operation is '0' - CI + -- If CI is not present, the operation is '0' - '0' + carry_inA <= '0' & in_a & '0'; + carry_inB <= '0' & in_b & '0'; + -- Compute the result + carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB)); + + -- Set the outputs + output <= carry_res(41 downto 1); + + -- Other comparison outputs + + -- Temporary signals + msb_abr <= in_a(40) & in_b(40) & carry_res(41); + tmp_sign <= sign; + tmp_eq <= '1' when in_a = in_b else '0'; + + tmp_le <= + tmp_eq when msb_abr = "000" or msb_abr = "110" else + '1' when msb_abr = "001" or msb_abr = "111" else + '1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else + '1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else + '0'; + + tmp_ge <= + '1' when msb_abr = "000" or msb_abr = "110" else + '1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else + '1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else + '0'; + + gt <= not(tmp_le); + +end architecture; diff --git a/testsuite/gna/bug040/tb.vhd b/testsuite/gna/bug040/tb.vhd new file mode 100644 index 000000000..542858637 --- /dev/null +++ b/testsuite/gna/bug040/tb.vhd @@ -0,0 +1,1712 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library std; +use std.textio.all; + +entity tb is +end tb; + +architecture augh of tb is + + constant simu_max_cycles : natural := 1000000; + constant simu_disp_cycles : std_logic := '0'; + constant simu_err_end_in : std_logic := '0'; + constant reset_cycles : natural := 4; + + component top is + port ( + clock : in std_logic; + reset : in std_logic; + start : in std_logic; + stdout_rdy : out std_logic; + stdout_ack : in std_logic; + stdin_ack : in std_logic; + stdout_data : out std_logic_vector(7 downto 0); + stdin_data : in std_logic_vector(7 downto 0); + stdin_rdy : out std_logic + ); + end component; + + signal clock : std_logic := '0'; + signal reset : std_logic := '0'; + signal start : std_logic := '0'; + + signal clock_next : std_logic := '0'; + + -- Access 'clock' model 'clock' + + -- Access 'reset' model 'reset' + + -- Access 'start' model 'start' + + -- Access 'stdin' model 'fifo_in' + signal stdin_data : std_logic_vector(7 downto 0) := (others => '0'); + signal stdin_rdy : std_logic := '0'; + signal stdin_ack : std_logic := '0'; + signal stdin_vector_idx : natural := 0; + signal stdin_vector : std_logic_vector(7 downto 0) := (others => '0'); + -- Test vectors + constant stdin_vectors_nb : natural := 5207; + type stdin_vec_type is array (0 to stdin_vectors_nb-1) of std_logic_vector(7 downto 0); + constant stdin_vectors : stdin_vec_type := ( + X"ff", X"d8", X"ff", X"e0", X"00", X"10", X"4a", X"46", X"49", X"46", X"00", X"01", X"01", X"00", X"00", + X"01", X"00", X"01", X"00", X"00", X"ff", X"db", X"00", X"43", X"00", X"03", X"02", X"02", X"02", X"02", + X"02", X"03", X"02", X"02", X"02", X"03", X"03", X"03", X"03", X"04", X"06", X"04", X"04", X"04", X"04", + X"04", X"08", X"06", X"06", X"05", X"06", X"09", X"08", X"0a", X"0a", X"09", X"08", X"09", X"09", X"0a", + X"0c", X"0f", X"0c", X"0a", X"0b", X"0e", X"0b", X"09", X"09", X"0d", X"11", X"0d", X"0e", X"0f", X"10", + X"10", X"11", X"10", X"0a", X"0c", X"12", X"13", X"12", X"10", X"13", X"0f", X"10", X"10", X"10", X"ff", + X"db", X"00", X"43", X"01", X"03", X"03", X"03", X"04", X"03", X"04", X"08", X"04", X"04", X"08", X"10", + X"0b", X"09", X"0b", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", + X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", + X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", + X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"10", X"ff", X"c0", X"00", X"11", X"08", X"00", X"3b", + X"00", X"5a", X"03", X"01", X"22", X"00", X"02", X"11", X"01", X"03", X"11", X"01", X"ff", X"c4", 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X"4a", X"2d", X"fb", X"b7", X"d8", X"f9", + X"cb", X"45", X"d6", X"fe", X"23", X"7c", X"24", X"f1", X"b7", X"8b", X"7e", X"28", X"7c", X"3d", X"f8", + X"71", X"69", X"37", X"87", X"64", X"b0", X"d5", X"af", X"f4", X"6d", X"2a", X"eb", X"51", X"8a", X"58", + X"f4", X"dd", X"08", X"24", X"91", X"a3", X"c3", X"e5", X"b1", X"77", X"8e", X"19", X"64", X"59", X"66", + X"b6", X"8f", X"27", X"6d", X"bb", X"45", X"21", X"1e", X"5a", X"c8", X"bc", X"b7", X"ec", X"e7", X"f1", + X"c3", X"c4", X"b6", X"9e", X"39", X"4f", X"16", X"fc", X"4b", X"8e", X"4d", X"6b", X"45", X"d5", X"64", + X"6b", X"4b", X"61", X"2d", X"9d", X"b4", X"70", X"c7", X"2a", X"5c", X"5b", X"4c", X"d3", X"c4", X"1b", + X"08", X"b2", X"a9", X"b5", X"85", X"9a", X"73", X"ca", X"3c", X"30", X"b1", X"93", X"78", X"dd", X"5f", + X"a1", X"ba", X"bf", X"86", X"b4", X"2b", X"4f", X"8c", X"56", X"da", X"ad", X"be", X"9b", X"12", X"5c", + X"e9", X"de", X"0d", X"d4", X"2d", X"6d", X"9b", X"92", X"ab", X"14", X"77", X"5a", X"64", X"88", X"85", + X"4f", X"ca", X"c1", X"5d", X"98", X"8d", X"c0", X"e3", X"73", X"0e", X"84", X"8a", X"f8", X"03", X"fe", + X"0a", X"0f", X"69", X"6b", X"63", X"fb", X"54", X"6a", X"90", X"58", X"c0", X"96", X"c9", X"a8", X"59", + X"69", X"33", X"5c", X"88", X"46", X"cf", X"32", X"47", X"0f", X"0b", X"b1", X"c7", X"73", X"1c", X"31", + X"a9", X"3d", X"4e", X"df", X"52", X"49", X"bc", X"6d", X"39", X"65", X"eb", X"da", X"d2", X"77", X"8a", + X"96", X"cf", X"d3", X"ca", X"dd", X"cc", X"b9", X"a4", X"9d", X"ae", X"56", X"f1", X"2f", X"c4", X"2d", + X"2f", X"5b", X"f0", X"dd", X"f7", X"89", X"a5", X"bc", X"36", X"de", X"22", X"d5", X"24", X"7d", X"43", + X"52", X"98", X"ee", X"9e", X"df", X"4d", X"69", X"54", X"ec", X"58", X"d5", X"db", X"6a", X"dd", X"4a", + X"c0", X"05", X"6e", X"91", X"a8", X"df", X"21", X"dd", X"b1", X"59", X"3e", X"1d", X"7c", X"7e", X"f8", + X"a1", X"a3", X"f8", X"07", X"c3", X"7e", X"1f", X"f0", X"d4", X"5e", X"1a", X"b7", X"f0", X"7f", X"84", + X"6f", X"ae", X"be", X"dd", X"1d", X"fc", X"b6", X"b6", X"f6", X"ba", X"a4", X"57", X"1b", X"d9", X"ac", + X"24", X"86", X"77", X"df", X"75", X"0e", X"c9", X"6e", X"01", X"11", X"24", X"b2", X"37", X"da", X"30", + X"e1", X"d9", X"93", X"77", X"85", X"f8", X"8f", X"52", X"d4", X"34", X"2d", X"5a", X"da", X"1d", X"1e", + X"fa", X"e2", X"ce", X"38", X"d4", X"00", X"b0", X"c8", X"54", X"73", X"c9", X"27", X"d4", X"9c", X"9c", + X"93", X"c9", X"ef", X"57", X"ee", X"2f", X"26", X"d7", X"74", X"3d", X"6b", X"52", X"d4", X"84", X"6f", + X"75", X"61", X"30", X"48", X"25", X"8e", X"25", X"84", X"80", X"66", X"2a", X"77", X"6c", X"03", X"7f", + X"03", X"f8", X"b3", X"dc", X"f5", X"26", X"be", X"52", X"38", X"ba", X"91", X"93", X"c4", X"c5", X"d9", + X"cf", X"7b", X"69", X"be", X"bf", X"99", X"97", X"33", X"56", X"48", X"b5", X"e2", X"1b", X"9f", X"09", + X"3d", X"ed", X"cd", X"8f", X"86", X"74", X"d3", X"a5", X"e8", X"e6", X"f1", X"ee", X"ed", X"ac", X"2d", + X"e7", X"33", X"2d", X"b9", X"6e", X"06", X"e7", X"20", X"09", X"25", X"55", X"c2", X"b1", X"8c", X"79", + X"65", X"95", X"ca", X"6e", X"52", X"09", X"f5", X"1b", X"1f", X"da", X"3f", X"c4", X"96", X"56", X"56", + X"f6", X"76", X"ff", X"00", X"0d", X"b4", X"c6", X"8a", X"08", X"92", X"24", X"3b", X"e3", X"5c", X"aa", + X"80", X"07", X"1b", X"b8", X"e0", X"74", X"ae", X"37", X"e2", X"2f", X"86", X"74", X"1d", X"1f", X"41", + X"b4", X"9b", X"4c", X"d3", X"22", X"b7", X"70", X"96", X"e8", X"59", X"33", X"96", X"04", X"39", X"cb", + X"73", X"f3", X"1c", X"a8", X"e4", X"e4", X"f5", X"e7", X"93", X"5e", X"cd", X"e1", X"8f", X"02", X"78", + X"5a", X"f3", X"c3", X"7a", X"4d", X"dd", X"ce", X"9a", X"ef", X"34", X"f6", X"30", X"49", X"23", X"7d", + X"a6", X"51", X"b9", X"9a", X"35", X"24", X"e0", X"36", X"3a", X"9a", X"f0", X"31", X"52", X"85", X"47", + X"cd", X"35", X"7d", X"5e", X"f7", X"fd", X"19", X"dd", X"4a", X"b5", X"58", X"d4", X"92", X"52", X"3f", + X"ff", X"d9" + ); + + -- Access 'stdout' model 'fifo_out' + signal stdout_data : std_logic_vector(7 downto 0) := (others => '0'); + signal stdout_rdy : std_logic := '0'; + signal stdout_ack : std_logic := '0'; + signal stdout_vector_idx : natural := 0; + signal stdout_vector : std_logic_vector(7 downto 0) := (others => '0'); + -- Test vectors + constant stdout_vectors_nb : natural := 15932; + type stdout_vec_type is array (0 to stdout_vectors_nb-1) of std_logic_vector(7 downto 0); + constant stdout_vectors : stdout_vec_type := ( + X"bc", X"d1", X"be", X"99", X"8f", X"67", X"95", X"c0", X"ac", X"9d", X"bd", X"c0", X"a4", X"c3", X"bc", + X"b5", X"c1", X"a7", X"bc", X"d2", X"b1", X"8e", X"25", X"0a", X"1f", X"28", X"27", X"34", X"20", X"1d", + X"22", X"0e", X"0a", X"12", X"0e", X"1a", X"07", X"6c", X"b5", X"be", X"b5", X"7f", X"5b", X"63", X"49", + X"24", X"0b", X"24", X"42", X"5d", X"5a", X"41", X"33", X"20", X"24", X"23", X"26", X"35", X"38", X"23", + X"19", X"19", X"20", X"31", X"29", X"36", X"20", X"1f", X"1f", X"22", X"18", X"19", X"26", X"2b", X"20", + X"0b", X"09", X"0d", X"14", X"19", X"17", X"11", X"10", X"12", X"1e", X"19", X"21", X"2d", X"24", X"1d", + X"a6", X"c1", X"65", X"5a", X"aa", X"81", X"92", X"d5", X"a9", X"58", X"91", X"c7", X"cf", X"a5", X"89", + X"71", X"c9", X"9b", X"8b", X"d1", X"bf", X"c9", X"ab", X"67", X"33", X"1d", X"11", X"09", X"1d", X"2b", + X"21", X"24", X"18", X"0e", X"18", X"18", X"04", X"6c", X"b9", X"b4", X"ba", X"bc", X"b7", X"c3", X"c0", + X"6c", X"30", X"4b", X"67", X"55", X"45", X"31", X"2e", X"37", X"2c", X"2a", X"32", X"33", X"29", X"1e", + X"12", X"0e", X"1e", X"30", X"30", X"36", X"22", X"28", X"26", X"24", X"1f", X"1c", X"34", X"37", X"2d", + X"0f", X"0e", X"10", X"17", X"15", X"0f", X"0b", X"11", X"19", X"1f", X"1a", X"2c", X"49", X"22", X"27", + X"91", X"84", X"2e", X"b5", X"cd", X"d1", X"bb", X"aa", X"8c", X"38", X"34", X"8e", X"7a", X"b0", X"c6", + X"53", X"9a", X"d7", X"c8", X"d1", X"b8", X"a4", X"c4", X"ae", X"80", X"37", X"59", X"4c", X"1c", X"26", + X"2f", X"2e", X"23", X"1b", X"27", X"1f", X"10", X"3a", X"74", X"89", X"a9", X"b8", X"b4", X"af", X"a6", + X"78", X"49", X"5b", X"61", X"54", X"20", X"24", X"3e", X"3a", X"28", X"29", X"30", X"2d", X"20", X"14", + X"0f", X"10", X"0c", X"1b", X"18", X"24", X"28", X"10", X"22", X"18", X"16", X"21", X"3d", X"41", X"37", + X"12", X"15", X"16", X"1d", X"13", X"12", X"0f", X"15", X"1c", X"21", X"1d", X"30", X"4b", X"24", X"26", + X"6f", X"0f", X"3e", X"e2", X"cf", X"bb", X"cd", X"bc", X"3d", X"02", X"0d", X"1f", X"09", X"69", X"8c", + X"31", X"18", X"bf", X"d1", X"c6", X"ba", X"b8", X"93", X"75", X"59", X"3a", X"8a", X"b3", X"87", X"3e", + X"34", X"33", X"17", X"14", X"22", X"1c", X"1a", X"0a", X"2a", X"70", X"97", X"9d", X"8b", X"7a", X"71", + X"36", X"4f", X"54", X"60", X"2e", X"13", X"20", X"35", X"3a", X"28", X"28", X"27", X"26", X"15", X"15", + X"11", X"17", X"06", X"6e", X"65", X"0e", X"12", X"07", X"0f", X"1b", X"07", X"1b", X"40", X"46", X"3f", + X"16", X"1e", X"20", X"26", X"16", X"08", X"0a", X"12", X"14", X"1a", X"1b", X"2b", X"3a", X"2c", X"28", + X"8b", X"8c", X"81", X"9c", X"71", X"b1", X"d7", X"ae", X"6f", X"65", X"24", X"0e", X"14", X"8b", X"62", + X"6a", X"51", X"25", X"61", X"df", X"c8", X"d9", X"95", X"99", X"94", X"83", X"46", X"92", X"b2", X"ac", + X"83", X"50", X"0d", X"11", X"2b", X"10", X"12", X"14", X"18", X"62", X"82", X"a3", X"90", X"55", X"47", + X"51", X"4e", X"58", X"44", X"1d", X"27", X"38", X"3b", X"31", X"28", X"29", X"27", X"14", X"0b", X"3f", + X"50", X"01", X"59", X"b3", X"ba", X"60", X"00", X"25", X"0f", X"15", X"14", X"1b", X"40", X"4c", X"49", + X"1d", X"1f", X"21", X"2b", X"22", X"0d", X"0c", X"13", X"10", X"10", X"0e", X"1c", X"26", X"3c", X"32", + X"b3", X"c4", X"d9", X"84", X"37", X"79", X"d5", X"b4", X"b1", X"b7", X"ae", X"66", X"a1", X"b6", X"8c", + X"93", X"c5", X"ce", X"a4", X"d6", X"d9", X"af", X"28", X"8d", X"ae", X"b7", X"7b", X"44", X"61", X"77", + X"7b", X"7e", X"31", X"15", X"27", X"11", X"17", X"1c", X"0e", X"7b", X"95", X"c2", X"c1", X"5f", X"4b", + X"49", X"46", X"3f", X"3b", X"32", X"30", X"37", X"3a", X"2a", X"30", X"36", X"20", X"24", X"0c", X"55", + X"9f", X"6e", X"7d", X"b1", X"bb", X"89", X"19", X"36", X"3a", X"37", X"12", X"13", X"3b", X"4d", X"4c", + X"22", X"1e", X"20", X"30", X"2f", X"22", X"12", X"0d", X"0d", X"0c", X"05", X"0c", X"12", X"34", X"39", + X"88", X"86", X"af", X"d6", X"86", X"a1", X"be", X"8d", X"b1", X"bd", X"8d", X"a4", X"cb", X"b3", X"b9", + X"90", X"49", X"8d", X"ce", X"94", X"b5", X"c0", X"71", X"45", X"95", X"b0", X"8d", X"74", X"53", X"2e", + X"65", X"70", X"4f", X"1f", X"19", X"28", X"1e", X"1a", X"0c", X"62", X"a2", X"c3", X"d7", X"7a", X"37", + X"41", X"3d", X"44", X"40", X"2e", X"44", X"41", X"43", X"50", X"38", X"24", X"2c", X"2f", X"1b", X"37", + X"b1", X"c8", X"af", X"a9", X"b2", X"9c", X"72", X"7e", X"6b", X"3d", X"2e", X"32", X"3c", X"4e", X"4c", + X"2e", X"2a", X"30", X"3b", X"3a", X"2d", X"19", X"14", X"16", X"1a", X"13", X"13", X"0f", X"38", X"3a", + X"29", X"72", X"c4", X"c3", X"d0", X"c5", X"ba", X"b0", X"ae", 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X"67", + X"17", X"0e", X"05", X"06", X"01", X"48", X"03", X"0a", X"49", X"4e", X"61", X"8c", X"da", X"e0", X"60", + X"6b", X"53", X"00", X"00", X"04", X"00", X"13", X"13", X"0e", X"0e", X"05", X"00", X"35", X"00", X"0b", + X"27", X"0b", X"20", X"0b", X"40", X"ac", X"5d", X"2c", X"10", X"73", X"cb", X"b3", X"3e", X"13", X"b9", + X"a2", X"d1", X"ff", X"7e", X"da", X"8f", X"86", X"8c", X"e0", X"4e", X"00", X"33", X"2e", X"1a", X"6a", + X"76", X"1a", X"27", X"80", X"00", X"45", X"46", X"00", X"54", X"28", X"09", X"20", X"00", X"00", X"00", + X"1f", X"c4", X"89", X"91", X"11", X"3b", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"5a", X"52", + X"15", X"0a", X"13", X"0e", X"08", X"2a", X"14", X"27", X"4b", X"4f", X"51", X"1f", X"5b", X"bf", X"7d", + X"76", X"10", X"0e", X"00", X"04", X"18", X"0c", X"00", X"19", X"00", X"70", X"b1", X"62", X"b0", X"1f", + X"0b", X"43", X"2c", X"18", X"00", X"55", X"29", X"ef", X"42", X"22", X"04", X"8c", X"93", X"a6", X"b5", + X"c3", X"b7", X"6f", X"78", X"60", X"dc", X"a8", X"55", X"92", X"c5", X"00", X"31", X"1f", X"5c", X"a8", + X"40", X"30", X"3f", X"21", X"05", X"23", X"04", X"1d", X"55", X"31", X"00", X"00", X"00", X"05", X"0c", + X"5d", X"39", X"0a", X"00", X"0f", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"50", X"55", + X"00", X"00", X"00", X"13", X"28", X"1d", X"2c", X"16", X"19", X"11", X"5b", X"4e", X"63", X"17", X"4f", + X"6c", X"62", X"00", X"06", X"00", X"00", X"40", X"11", X"13", X"14", X"b5", X"1e", X"c6", X"f4", X"ff", + X"00", X"1b", X"2b", X"1b", X"6a", X"10", X"21", X"d4", X"ff", X"3f", X"23", X"5d", X"e6", X"77", X"bc", + X"f0", X"b4", X"b6", X"85", X"c3", X"d6", X"5b", X"48", X"c1", X"b7", X"d4", X"ce", X"a5", X"0b", X"45", + X"44", X"1d", X"49", X"34", X"42", X"00", X"16", X"1b", X"28", X"61", X"6f", X"68", X"69", X"0f", X"15", + X"00", X"11", X"48", X"3b", X"35", X"16", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"33", X"27", + X"00", X"00", X"00", X"15", X"2e", X"0b", X"19", X"1f", X"12", X"08", X"9f", X"45", X"6f", X"3d", X"a4", + X"6c", X"00", X"00", X"02", X"0c", X"13", X"4f", X"00", X"09", X"2b", X"a9", X"c7", X"65", X"d4", X"ff", + X"ed", X"09", X"0f", X"67", X"54", X"0c", X"16", X"3a", X"b4", X"13", X"13", X"98", X"84", X"62", X"4e", + X"e4", X"cf", X"e0", X"bb", X"c8", X"d1", X"93", X"10", X"c2", X"bb", X"ff", X"df", X"f1", X"3b", X"2d", + X"2b", X"15", X"25", X"2a", X"38", X"30", X"2b", X"00", X"01", X"20", X"15", X"21", X"6e", X"56", X"3e", + X"39", X"09", X"1a", X"0d", X"10", X"00", X"26", X"25", X"10", X"00", X"00", X"00", X"00", X"22", X"23", + X"5a", X"00", X"00", X"00", X"1c", X"00", X"00", X"28", X"00", X"00", X"6d", X"59", X"24", X"00", X"00", + X"1f", X"00", X"00", X"00", X"12", X"4c", X"38", X"00", X"0a", X"17", X"17", X"f3", X"ef", X"bd", X"9e", + X"e6", X"e3", X"a5", X"e0", X"bf", X"04", X"4b", X"ac", X"10", X"26", X"8d", X"12", X"d2", X"ec", X"3b", + X"de", X"cf", X"b6", X"d7", X"d3", X"a1", X"bc", X"56", X"d9", X"e8", X"d7", X"e8", X"c8", X"74", X"00", + X"32", X"11", X"20", X"59", X"40", X"2a", X"17", X"00", X"00", X"00", X"01", X"01", X"36", X"00", X"0c", + X"0a", X"28", X"39", X"10", X"00", X"37", X"35", X"3d", X"36", X"38", X"12", X"0e", X"10", X"12", X"09", + X"5a", X"3b" + ); + + signal clock_counter : natural := 0; + signal clock_counter_stop : natural := 0; + + signal errors_nb : natural := 0; + + -- Defined in VHDL 2008, not handled by GHDL + function to_string(sv: std_logic_vector) return string is + variable bv: bit_vector(sv'range) := to_bitvector(sv); + variable lp: line; + begin + write(lp, bv); + return lp.all; + end; + +begin + + -- Instantiation of the main component + top_i : top port map ( + -- Access 'clock' model 'clock' + clock => clock, + -- Access 'reset' model 'reset' + reset => reset, + -- Access 'start' model 'start' + start => start, + -- Access 'stdin' model 'fifo_in' + stdin_data => stdin_data, + stdin_rdy => stdin_rdy, + stdin_ack => stdin_ack, + -- Access 'stdout' model 'fifo_out' + stdout_data => stdout_data, + stdout_rdy => stdout_rdy, + stdout_ack => stdout_ack + ); + + -- Functionality for top-level access 'clock' model 'clock' + -- Generation of clock: 100MHz (note: arbitrary value) + clock <= clock_next after 5 ns; + clock_next <= not clock when clock_counter_stop = 0 or clock_counter <= clock_counter_stop else '0'; + + -- Clock counter and global messages + process (clock) + -- To print simulation messages + variable l : line; + begin + + -- Increment clock counter + if rising_edge(clock) then + + clock_counter <= clock_counter + 1; + + if simu_disp_cycles = '1' then + -- Write simulation message + write(l, string'("INFO clock cycle ")); + write(l, clock_counter); + writeline(output, l); + end if; + + end if; + + -- Messages + if falling_edge(clock) then + + if clock_counter > simu_max_cycles then + report "ERROR Too many cycles simulated. Stopping simulation." severity failure; + end if; + + if clock_counter < reset_cycles then + report "INFO Reset" severity note; + end if; + + if clock_counter = reset_cycles then + report "INFO Start" severity note; + end if; + + end if; + + end process; + + -- Functionality for top-level access 'reset' model 'reset' + -- Generation of reset + reset <= '1' when clock_counter < reset_cycles else '0'; + + -- Functionality for top-level access 'start' model 'start' + -- Generation of start + start <= '1'; + + -- Functionality for top-level access 'stdin' model 'fifo_in' + -- FIFO stdin + -- Sending inputs + + stdin_vector <= stdin_vectors(stdin_vector_idx) when stdin_vector_idx < stdin_vectors_nb else (others => '0'); + stdin_data <= stdin_vector(7 downto 0); + + stdin_ack <= '1' when reset = '0' and stdin_vector_idx < stdin_vectors_nb else '0'; + + process (clock) + -- To print simulation messages + variable l : line; + begin + + if rising_edge(clock) then + + if stdin_vector_idx < stdin_vectors_nb then + + if stdin_rdy = '1' and stdin_ack = '1' and reset = '0' then + + -- Write simulation message + write(l, string'("INFO Input vector ")); + write(l, stdin_vector_idx); + write(l, string'(" at cycle ")); + write(l, clock_counter); + writeline(output, l); + + if stdin_vector_idx = 0 then + write(l, string'("INFO First input vector sent at clock cycle ")); + write(l, clock_counter); + writeline(output, l); + end if; + + if stdin_vector_idx = stdin_vectors_nb - 1 then + write(l, string'("INFO Last input vector sent at clock cycle ")); + write(l, clock_counter); + writeline(output, l); + end if; + + -- Increase vector index + stdin_vector_idx <= stdin_vector_idx + 1; + + end if; -- Handshake + + else + + if stdin_rdy = '1' and reset = '0' then + if simu_err_end_in = '1' then + report "ERROR Out of input vectors. Stopping simulation." severity failure; + end if; + end if; -- Handshake + + end if; + + end if; + + end process; + + -- Functionality for top-level access 'stdout' model 'fifo_out' + -- FIFO stdout + -- Checking outputs + + -- Always enable output FIFO + stdout_ack <= '1' when stdout_vector_idx < stdout_vectors_nb and reset = '0' else '0'; + + stdout_vector <= stdout_vectors(stdout_vector_idx) when stdout_vector_idx < stdout_vectors_nb else (others => '0'); + + -- Check outputs + process (clock) + variable l : line; + begin + + if rising_edge(clock) then + + if stdout_vector_idx < stdout_vectors_nb then + + if stdout_rdy = '1' and stdout_ack = '1' and reset = '0' then + + if stdout_data = stdout_vector(7 downto 0) then + -- The vector is verified + + write(l, string'("INFO Output nb ")); + write(l, stdout_vector_idx); + write(l, string'(" at cycle ")); + write(l, clock_counter); + write(l, string'(" (check OK)")); + write(l, string'(" Obtained ")); + write(l, to_string(stdout_data)); + writeline(output, l); + + else + -- An error is detected + + write(l, string'("ERROR Output nb ")); + write(l, stdout_vector_idx); + write(l, string'(" at cycle ")); + write(l, clock_counter); + writeline(output, l); + + write(l, string'(" Obtained ")); + write(l, to_string(stdout_data)); + writeline(output, l); + write(l, string'(" Expected ")); + write(l, to_string(stdout_vector(7 downto 0))); + writeline(output, l); + + errors_nb <= errors_nb + 1; + + --report "ERROR A simulation error was found." severity failure; + + end if; + + if stdout_vector_idx = stdout_vectors_nb - 1 then + + write(l, string'("INFO Last output vector read at cycle ")); + write(l, clock_counter); + writeline(output, l); + + report "INFO Stopping simulation." severity note; + + clock_counter_stop <= clock_counter + 3; + + end if; + + -- Increase vector index + stdout_vector_idx <= stdout_vector_idx + 1; + + end if; -- FIFO handshake + + else + -- All vectors have been read + + if errors_nb > 0 then + write(l, string'("ERROR Number of errors found : ")); + write(l, errors_nb); + writeline(output, l); + report "ERROR Simulation errors were found." severity failure; + end if; + + end if; -- Check all vectors read + + end if; -- Clock + + end process; + +end augh; + diff --git a/testsuite/gna/bug040/testsuite.sh b/testsuite/gna/bug040/testsuite.sh new file mode 100755 index 000000000..da0f172ab --- /dev/null +++ b/testsuite/gna/bug040/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze *.vhd +elab_simulate tb --stop-time=4us + +clean + +echo "Test successful" diff --git a/testsuite/gna/bug040/top.vhd b/testsuite/gna/bug040/top.vhd new file mode 100644 index 000000000..84d963db8 --- /dev/null +++ b/testsuite/gna/bug040/top.vhd @@ -0,0 +1,7027 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity top is + port ( + clock : in std_logic; + reset : in std_logic; + start : in std_logic; + stdout_rdy : out std_logic; + stdout_ack : in std_logic; + stdin_ack : in std_logic; + stdout_data : out std_logic_vector(7 downto 0); + stdin_data : in std_logic_vector(7 downto 0); + stdin_rdy : out std_logic + ); +end top; + +architecture augh of top is + + -- Declaration of components + + component cmp_869 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(7 downto 0); + in0 : in std_logic_vector(7 downto 0) + ); + end component; + + component cmp_978 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_979 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_847 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_855 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_852 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component mul_213 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); + end component; + + component mul_216 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); + end component; + + component mul_214 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_846 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_848 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_849 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component p_jinfo_comps_info_id is + port ( + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic_vector(7 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_comps_info_h_samp_factor is + port ( + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic_vector(7 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_comps_info_quant_tbl_no is + port ( + wa0_data : in std_logic_vector(1 downto 0); + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic_vector(1 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_comps_info_dc_tbl_no is + port ( + wa0_data : in std_logic; + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic; + wa0_en : in std_logic + ); + end component; + + component p_jinfo_quant_tbl_quantval is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(7 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(7 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_dc_xhuff_tbl_bits is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_dc_xhuff_tbl_huffval is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(9 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(9 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_ac_xhuff_tbl_bits is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_ac_xhuff_tbl_huffval is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(9 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(9 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_dc_dhuff_tbl_ml is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic; + clk : in std_logic; + ra0_addr : in std_logic; + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_dc_dhuff_tbl_maxcode is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_dc_dhuff_tbl_mincode is + port ( + wa0_data : in std_logic_vector(8 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(8 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_dc_dhuff_tbl_valptr is + port ( + wa0_data : in std_logic_vector(8 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(8 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_ac_dhuff_tbl_ml is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic; + clk : in std_logic; + ra0_addr : in std_logic; + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_ac_dhuff_tbl_maxcode is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_ac_dhuff_tbl_mincode is + port ( + wa0_data : in std_logic_vector(8 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(8 downto 0); + wa0_en : in std_logic + ); + end component; + + component p_jinfo_ac_dhuff_tbl_valptr is + port ( + wa0_data : in std_logic_vector(8 downto 0); + wa0_addr : in std_logic_vector(6 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(6 downto 0); + ra0_data : out std_logic_vector(8 downto 0); + wa0_en : in std_logic + ); + end component; + + component outdata_comp_vpos is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component outdata_comp_hpos is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(1 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(1 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component outdata_comp_buf is + port ( + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic_vector(14 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(14 downto 0); + ra0_data : out std_logic_vector(7 downto 0); + wa0_en : in std_logic + ); + end component; + + component izigzag_index is + port ( + clk : in std_logic; + ra0_addr : in std_logic_vector(5 downto 0); + ra0_data : out std_logic_vector(5 downto 0) + ); + end component; + + component jpegfilebuf is + port ( + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic_vector(12 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(12 downto 0); + ra0_data : out std_logic_vector(7 downto 0); + wa0_en : in std_logic + ); + end component; + + component huffbuff is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(7 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(7 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component idctbuff is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(8 downto 0); + clk : in std_logic; + ra2_data : out std_logic_vector(31 downto 0); + ra2_addr : in std_logic_vector(8 downto 0); + ra1_data : out std_logic_vector(31 downto 0); + ra1_addr : in std_logic_vector(8 downto 0); + ra0_addr : in std_logic_vector(8 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component quantbuff is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(5 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(5 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component extend_mask is + port ( + clk : in std_logic; + ra0_addr : in std_logic_vector(4 downto 0); + ra0_data : out std_logic_vector(20 downto 0) + ); + end component; + + component bit_set_mask is + port ( + clk : in std_logic; + ra0_addr : in std_logic_vector(4 downto 0); + ra0_data : out std_logic_vector(31 downto 0) + ); + end component; + + component lmask is + port ( + clk : in std_logic; + ra0_addr : in std_logic_vector(4 downto 0); + ra0_data : out std_logic_vector(31 downto 0) + ); + end component; + + component huff_make_dhuff_tb_ac_huffsize is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(8 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(8 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component huff_make_dhuff_tb_ac_huffcode is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(8 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(8 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component huff_make_dhuff_tb_dc_huffsize is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(8 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(8 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component huff_make_dhuff_tb_dc_huffcode is + port ( + wa0_data : in std_logic_vector(31 downto 0); + wa0_addr : in std_logic_vector(8 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(8 downto 0); + ra0_data : out std_logic_vector(31 downto 0); + wa0_en : in std_logic + ); + end component; + + component rgb_buf is + port ( + wa0_data : in std_logic_vector(7 downto 0); + wa0_addr : in std_logic_vector(9 downto 0); + clk : in std_logic; + ra0_addr : in std_logic_vector(9 downto 0); + ra0_data : out std_logic_vector(7 downto 0); + wa0_en : in std_logic + ); + end component; + + component zigzag_index is + port ( + clk : in std_logic; + ra0_addr : in std_logic_vector(5 downto 0); + ra0_data : out std_logic_vector(5 downto 0) + ); + end component; + + component shr_212 is + port ( + output : out std_logic_vector(31 downto 0); + input : in std_logic_vector(31 downto 0); + shift : in std_logic_vector(5 downto 0); + padding : in std_logic + ); + end component; + + component mul_209 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); + end component; + + component mul_210 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); + end component; + + component shl_211 is + port ( + output : out std_logic_vector(31 downto 0); + input : in std_logic_vector(31 downto 0); + shift : in std_logic_vector(5 downto 0); + padding : in std_logic + ); + end component; + + component sub_206 is + port ( + gt : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); + end component; + + component sub_207 is + port ( + ge : out std_logic; + le : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); + end component; + + component sub_208 is + port ( + ge : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); + end component; + + component sub_205 is + port ( + gt : out std_logic; + ge : out std_logic; + lt : out std_logic; + le : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); + end component; + + component add_202 is + port ( + output : out std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); + end component; + + component add_203 is + port ( + output : out std_logic_vector(38 downto 0); + in_b : in std_logic_vector(38 downto 0); + in_a : in std_logic_vector(38 downto 0) + ); + end component; + + component add_204 is + port ( + output : out std_logic_vector(24 downto 0); + in_b : in std_logic_vector(24 downto 0); + in_a : in std_logic_vector(24 downto 0) + ); + end component; + + component add_201 is + port ( + output : out std_logic_vector(38 downto 0); + in_b : in std_logic_vector(38 downto 0); + in_a : in std_logic_vector(38 downto 0) + ); + end component; + + component add_200 is + port ( + output : out std_logic_vector(38 downto 0); + in_b : in std_logic_vector(38 downto 0); + in_a : in std_logic_vector(38 downto 0) + ); + end component; + + component cmp_775 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_779 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_780 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_787 is + port ( + eq : out std_logic; + in1 : in std_logic; + in0 : in std_logic + ); + end component; + + component cmp_788 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(2 downto 0); + in0 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_790 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(3 downto 0); + in0 : in std_logic_vector(3 downto 0) + ); + end component; + + component cmp_792 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_793 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_794 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_791 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_804 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_800 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_799 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_865 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(2 downto 0); + in0 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_882 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_885 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_887 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component mul_215 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_850 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_851 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_861 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_871 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_873 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(7 downto 0); + in0 : in std_logic_vector(7 downto 0) + ); + end component; + + component cmp_879 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_880 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component sub_217 is + port ( + ge : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); + end component; + + component cmp_863 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(2 downto 0); + in0 : in std_logic_vector(2 downto 0) + ); + end component; + + component cmp_868 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(23 downto 0); + in0 : in std_logic_vector(23 downto 0) + ); + end component; + + component cmp_877 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_878 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component sub_218 is + port ( + le : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); + end component; + + component sub_220 is + port ( + gt : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); + end component; + + component sub_221 is + port ( + gt : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); + end component; + + component mul_222 is + port ( + output : out std_logic_vector(40 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_a : in std_logic_vector(31 downto 0) + ); + end component; + + component sub_219 is + port ( + le : out std_logic; + output : out std_logic_vector(40 downto 0); + sign : in std_logic; + in_b : in std_logic_vector(40 downto 0); + in_a : in std_logic_vector(40 downto 0) + ); + end component; + + component cmp_962 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_975 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component fsm_224 is + port ( + clock : in std_logic; + reset : in std_logic; + out40 : out std_logic; + in2 : in std_logic; + in11 : in std_logic; + out146 : out std_logic; + out148 : out std_logic; + out150 : out std_logic; + out152 : out std_logic; + in12 : in std_logic; + out153 : out std_logic; + out154 : out std_logic; + in13 : in std_logic; + out156 : out std_logic; + out157 : out std_logic; + out160 : out std_logic; + out162 : out std_logic; + out165 : out std_logic; + out170 : out std_logic; + out171 : out std_logic; + out173 : out std_logic; + out175 : out std_logic; + out177 : out std_logic; + out180 : out std_logic; + out184 : out std_logic; + in14 : in std_logic; + out186 : out std_logic; + out189 : out std_logic; + out191 : out std_logic; + out192 : out std_logic; + out193 : out std_logic; + out197 : out std_logic; + out199 : out std_logic; + out201 : out std_logic; + out202 : out std_logic; + out205 : out std_logic; + out207 : out std_logic; + out208 : out std_logic; + out209 : out std_logic; + out210 : out std_logic; + out212 : out std_logic; + out213 : out std_logic; + in15 : in std_logic; + out221 : out std_logic; + out222 : out std_logic; + out224 : out std_logic; + out225 : out std_logic; + out228 : out std_logic; + out229 : out std_logic; + out230 : out std_logic; + out231 : out std_logic; + out99 : out std_logic; + in6 : in std_logic; + out92 : out std_logic; + out232 : out std_logic; + in16 : in std_logic; + out234 : out std_logic; + out236 : out std_logic; + out239 : out std_logic; + out240 : out std_logic; + out241 : out std_logic; + out245 : out std_logic; + out246 : out std_logic; + out247 : out std_logic; + out251 : out std_logic; + out252 : out std_logic; + out253 : out std_logic; + out255 : out std_logic; + out256 : out std_logic; + out258 : out std_logic; + out259 : out std_logic; + in17 : in std_logic; + out263 : out std_logic; + out264 : out std_logic; + out266 : out std_logic; + in18 : in std_logic; + out267 : out std_logic; + out268 : out std_logic; + out270 : out std_logic; + out273 : out std_logic; + out275 : out std_logic; + out276 : out std_logic; + in19 : in std_logic; + out279 : out std_logic; + in20 : in std_logic; + out281 : out std_logic; + out282 : out std_logic; + in21 : in std_logic; + out283 : out std_logic; + out286 : out std_logic; + out289 : out std_logic; + out296 : out std_logic; + out297 : out std_logic; + out299 : out std_logic; + out300 : out std_logic; + out304 : out std_logic; + out305 : out std_logic; + in22 : in std_logic; + out306 : out std_logic; + out310 : out std_logic; + out311 : out std_logic; + out313 : out std_logic; + out314 : out std_logic; + in23 : in std_logic; + out316 : out std_logic; + out317 : out std_logic; + out320 : out std_logic; + out322 : out std_logic; + out324 : out std_logic; + out325 : out std_logic; + out326 : out std_logic; + out328 : out std_logic; + out332 : out std_logic; + out333 : out std_logic; + out334 : out std_logic; + out335 : out std_logic; + out338 : out std_logic; + out339 : out std_logic; + out341 : out std_logic; + out342 : out std_logic; + out344 : out std_logic; + out93 : out std_logic; + out98 : out std_logic; + out85 : out std_logic; + out87 : out std_logic; + out88 : out std_logic; + out80 : out std_logic; + out82 : out std_logic; + out83 : out std_logic; + out84 : out std_logic; + in5 : in std_logic; + out77 : out std_logic; + out78 : out std_logic; + out71 : out std_logic; + out72 : out std_logic; + in4 : in std_logic; + out65 : out std_logic; + out67 : out std_logic; + out60 : out std_logic; + out64 : out std_logic; + in3 : in std_logic; + out59 : out std_logic; + out53 : out std_logic; + out55 : out std_logic; + out49 : out std_logic; + out44 : out std_logic; + out104 : out std_logic; + out107 : out std_logic; + out111 : out std_logic; + out112 : out std_logic; + out114 : out std_logic; + in7 : in std_logic; + out117 : out std_logic; + out119 : out std_logic; + out122 : out std_logic; + in8 : in std_logic; + out128 : out std_logic; + in9 : in std_logic; + out129 : out std_logic; + out130 : out std_logic; + out133 : out std_logic; + out134 : out std_logic; + out136 : out std_logic; + out137 : out std_logic; + in10 : in std_logic; + out139 : out std_logic; + out143 : out std_logic; + out144 : out std_logic; + out32 : out std_logic; + out35 : out std_logic; + out27 : out std_logic; + out25 : out std_logic; + out26 : out std_logic; + in1 : in std_logic; + out15 : out std_logic; + out16 : out std_logic; + out11 : out std_logic; + out13 : out std_logic; + out14 : out std_logic; + out7 : out std_logic; + out1 : out std_logic; + out2 : out std_logic; + out3 : out std_logic; + out4 : out std_logic; + in0 : in std_logic; + in24 : in std_logic; + out346 : out std_logic; + out347 : out std_logic; + out348 : out std_logic; + out349 : out std_logic; + in25 : in std_logic; + out350 : out std_logic; + out351 : out std_logic; + out355 : out std_logic; + out356 : out std_logic; + out357 : out std_logic; + out358 : out std_logic; + out360 : out std_logic; + out362 : out std_logic; + out363 : out std_logic; + out364 : out std_logic; + out365 : out std_logic; + out366 : out std_logic; + out370 : out std_logic; + out371 : out std_logic; + out372 : out std_logic; + out373 : out std_logic; + out375 : out std_logic; + in26 : in std_logic; + out376 : out std_logic; + out378 : out std_logic; + out379 : out std_logic; + out381 : out std_logic; + out382 : out std_logic; + in27 : in std_logic; + out384 : out std_logic; + in28 : in std_logic; + out391 : out std_logic; + out395 : out std_logic; + out396 : out std_logic; + out401 : out std_logic; + out402 : out std_logic; + out403 : out std_logic; + out404 : out std_logic; + out405 : out std_logic; + out407 : out std_logic; + out408 : out std_logic; + out409 : out std_logic; + out410 : out std_logic; + in29 : in std_logic; + out412 : out std_logic; + out414 : out std_logic; + out415 : out std_logic; + out417 : out std_logic; + out418 : out std_logic; + out419 : out std_logic; + out420 : out std_logic; + out422 : out std_logic; + out424 : out std_logic; + out425 : out std_logic; + out426 : out std_logic; + in30 : in std_logic; + out428 : out std_logic; + out429 : out std_logic; + out432 : out std_logic; + out433 : out std_logic; + out434 : out std_logic; + out437 : out std_logic; + out440 : out std_logic; + out441 : out std_logic; + in31 : in std_logic; + out443 : out std_logic; + in32 : in std_logic; + out445 : out std_logic; + out447 : out std_logic; + out448 : out std_logic; + out450 : out std_logic; + in33 : in std_logic; + out453 : out std_logic; + out455 : out std_logic; + out458 : out std_logic; + in34 : in std_logic; + out462 : out std_logic; + out464 : out std_logic; + out467 : out std_logic; + out468 : out std_logic; + out472 : out std_logic; + in35 : in std_logic; + out478 : out std_logic; + out479 : out std_logic; + out480 : out std_logic; + out487 : out std_logic; + out488 : out std_logic; + in36 : in std_logic; + out491 : out std_logic; + out496 : out std_logic; + out497 : out std_logic; + out498 : out std_logic; + out500 : out std_logic; + out504 : out std_logic; + out505 : out std_logic; + in37 : in std_logic; + out506 : out std_logic; + out508 : out std_logic; + in38 : in std_logic; + out510 : out std_logic; + out513 : out std_logic; + out514 : out std_logic; + out515 : out std_logic; + out517 : out std_logic; + out519 : out std_logic; + in39 : in std_logic; + out523 : out std_logic; + out526 : out std_logic; + out527 : out std_logic; + out528 : out std_logic; + out530 : out std_logic; + out531 : out std_logic; + out533 : out std_logic; + out534 : out std_logic; + out537 : out std_logic; + out538 : out std_logic; + out549 : out std_logic; + out558 : out std_logic; + out559 : out std_logic; + out561 : out std_logic; + in40 : in std_logic; + out566 : out std_logic; + out567 : out std_logic; + out568 : out std_logic; + out569 : out std_logic; + out570 : out std_logic; + out572 : out std_logic; + out574 : out std_logic; + out575 : out std_logic; + out577 : out std_logic; + in41 : in std_logic; + out578 : out std_logic; + out581 : out std_logic; + out589 : out std_logic; + out590 : out std_logic; + out595 : out std_logic; + out597 : out std_logic; + out599 : out std_logic; + out601 : out std_logic; + out602 : out std_logic; + out607 : out std_logic; + out610 : out std_logic; + out612 : out std_logic; + in42 : in std_logic; + out614 : out std_logic; + out621 : out std_logic; + out628 : out std_logic; + out635 : out std_logic; + out636 : out std_logic; + out638 : out std_logic; + out640 : out std_logic; + out643 : out std_logic; + out646 : out std_logic; + out649 : out std_logic; + out651 : out std_logic; + out656 : out std_logic; + in43 : in std_logic; + out658 : out std_logic; + out659 : out std_logic; + out661 : out std_logic; + out663 : out std_logic; + out664 : out std_logic; + in44 : in std_logic; + out667 : out std_logic; + out668 : out std_logic; + out670 : out std_logic; + out672 : out std_logic; + out674 : out std_logic; + in45 : in std_logic; + out679 : out std_logic; + out681 : out std_logic; + out683 : out std_logic; + out686 : out std_logic; + out688 : out std_logic; + out690 : out std_logic; + out692 : out std_logic; + out694 : out std_logic; + out696 : out std_logic; + out697 : out std_logic; + out698 : out std_logic; + out699 : out std_logic; + out700 : out std_logic; + out703 : out std_logic; + out704 : out std_logic; + out706 : out std_logic; + out708 : out std_logic; + out710 : out std_logic; + out712 : out std_logic; + out715 : out std_logic; + out718 : out std_logic; + in46 : in std_logic; + out722 : out std_logic; + out724 : out std_logic; + out726 : out std_logic; + out728 : out std_logic; + out731 : out std_logic; + out733 : out std_logic; + out734 : out std_logic; + out737 : out std_logic; + out739 : out std_logic; + out740 : out std_logic; + out743 : out std_logic; + out745 : out std_logic; + out746 : out std_logic; + in47 : in std_logic; + out749 : out std_logic; + out753 : out std_logic; + out755 : out std_logic; + out759 : out std_logic; + in48 : in std_logic; + out762 : out std_logic; + out764 : out std_logic; + out765 : out std_logic; + out767 : out std_logic; + out768 : out std_logic; + in49 : in std_logic; + out772 : out std_logic; + in50 : in std_logic; + out775 : out std_logic; + out776 : out std_logic; + out778 : out std_logic; + out783 : out std_logic; + out784 : out std_logic; + out787 : out std_logic; + out791 : out std_logic; + in51 : in std_logic; + out794 : out std_logic; + out795 : out std_logic; + in52 : in std_logic; + out799 : out std_logic; + out802 : out std_logic; + out806 : out std_logic; + out809 : out std_logic; + out812 : out std_logic; + out815 : out std_logic; + out826 : out std_logic; + out828 : out std_logic; + in53 : in std_logic; + in54 : in std_logic; + out843 : out std_logic; + out848 : out std_logic; + out852 : out std_logic; + in55 : in std_logic; + out855 : out std_logic; + out858 : out std_logic; + in56 : in std_logic; + out860 : out std_logic; + out861 : out std_logic; + out863 : out std_logic; + out866 : out std_logic; + out872 : out std_logic; + in57 : in std_logic; + out874 : out std_logic; + out876 : out std_logic; + out879 : out std_logic; + out882 : out std_logic; + out886 : out std_logic; + out887 : out std_logic; + in58 : in std_logic; + out888 : out std_logic; + out892 : out std_logic; + out894 : out std_logic; + out895 : out std_logic; + out896 : out std_logic; + out901 : out std_logic; + out902 : out std_logic; + out903 : out std_logic; + out905 : out std_logic; + out907 : out std_logic; + out918 : out std_logic; + out920 : out std_logic; + out921 : out std_logic; + out923 : out std_logic; + out925 : out std_logic; + out928 : out std_logic; + out929 : out std_logic; + out931 : out std_logic; + out933 : out std_logic; + out936 : out std_logic; + out937 : out std_logic; + out938 : out std_logic; + out939 : out std_logic; + out942 : out std_logic; + out943 : out std_logic; + out944 : out std_logic; + out947 : out std_logic; + out948 : out std_logic; + out949 : out std_logic; + out951 : out std_logic; + in59 : in std_logic; + out952 : out std_logic; + out953 : out std_logic; + out955 : out std_logic; + out956 : out std_logic; + out957 : out std_logic; + out958 : out std_logic; + in60 : in std_logic; + in61 : in std_logic; + out962 : out std_logic; + out963 : out std_logic; + out972 : out std_logic; + out973 : out std_logic; + out974 : out std_logic; + in62 : in std_logic; + out978 : out std_logic; + out979 : out std_logic; + out981 : out std_logic; + out982 : out std_logic; + out985 : out std_logic; + out986 : out std_logic; + out989 : out std_logic; + in63 : in std_logic; + in64 : in std_logic; + in65 : in std_logic; + in66 : in std_logic; + in67 : in std_logic; + in68 : in std_logic; + in69 : in std_logic; + in70 : in std_logic; + in71 : in std_logic; + in72 : in std_logic; + in73 : in std_logic; + in74 : in std_logic; + in75 : in std_logic; + in76 : in std_logic; + in77 : in std_logic; + in78 : in std_logic; + out990 : out std_logic; + out991 : out std_logic; + out993 : out std_logic; + out994 : out std_logic; + out996 : out std_logic; + out997 : out std_logic; + out998 : out std_logic; + out999 : out std_logic; + out1000 : out std_logic; + out1002 : out std_logic; + out1003 : out std_logic; + out1005 : out std_logic; + out1006 : out std_logic; + out1007 : out std_logic; + out1009 : out std_logic; + out1011 : out std_logic; + out1012 : out std_logic; + out1013 : out std_logic; + out1014 : out std_logic; + out1015 : out std_logic; + out1016 : out std_logic; + out1018 : out std_logic; + out1019 : out std_logic; + out1021 : out std_logic; + out1022 : out std_logic; + out1024 : out std_logic; + out1026 : out std_logic; + out1027 : out std_logic; + out1029 : out std_logic; + out1030 : out std_logic; + out1032 : out std_logic; + out1033 : out std_logic; + out1035 : out std_logic; + out1036 : out std_logic; + out1037 : out std_logic; + out1057 : out std_logic; + out1068 : out std_logic; + out1069 : out std_logic; + out1070 : out std_logic; + out1072 : out std_logic; + out1073 : out std_logic; + out1075 : out std_logic; + out1078 : out std_logic; + out1080 : out std_logic; + out1082 : out std_logic; + out1083 : out std_logic; + out1084 : out std_logic; + out1085 : out std_logic; + out1088 : out std_logic; + out1089 : out std_logic; + out1091 : out std_logic; + out1092 : out std_logic; + out1094 : out std_logic; + out1096 : out std_logic; + out1098 : out std_logic; + out1101 : out std_logic; + out1104 : out std_logic; + out1107 : out std_logic; + out1109 : out std_logic; + out1111 : out std_logic; + out1114 : out std_logic; + out1119 : out std_logic; + out1121 : out std_logic; + out1125 : out std_logic; + out1126 : out std_logic; + out1128 : out std_logic; + out1131 : out std_logic; + out1134 : out std_logic; + out1137 : out std_logic; + out1139 : out std_logic; + out1141 : out std_logic; + out1145 : out std_logic; + out1146 : out std_logic; + out1147 : out std_logic; + out1150 : out std_logic; + out1151 : out std_logic; + out1152 : out std_logic; + out1155 : out std_logic; + out1158 : out std_logic; + out1160 : out std_logic; + out1164 : out std_logic; + out1166 : out std_logic; + out1169 : out std_logic; + out1171 : out std_logic; + out1174 : out std_logic; + out1175 : out std_logic; + out1176 : out std_logic; + out1180 : out std_logic; + out1181 : out std_logic; + out1182 : out std_logic; + out1185 : out std_logic; + out1186 : out std_logic; + out1187 : out std_logic; + out1190 : out std_logic; + out1213 : out std_logic; + out1215 : out std_logic; + out1217 : out std_logic; + out1220 : out std_logic; + out1221 : out std_logic; + out1223 : out std_logic; + out1228 : out std_logic; + out1229 : out std_logic; + out1231 : out std_logic; + out1235 : out std_logic; + out1236 : out std_logic; + out1240 : out std_logic; + out1243 : out std_logic; + out1250 : out std_logic; + out1252 : out std_logic; + out1253 : out std_logic; + out1258 : out std_logic; + out1262 : out std_logic; + out1266 : out std_logic; + out1269 : out std_logic; + out1275 : out std_logic; + out1278 : out std_logic; + out1279 : out std_logic; + out1284 : out std_logic; + out1286 : out std_logic; + out1287 : out std_logic; + out1289 : out std_logic; + out1290 : out std_logic; + out1292 : out std_logic; + out1293 : out std_logic; + out1295 : out std_logic; + out1298 : out std_logic; + out1301 : out std_logic; + out1302 : out std_logic; + out1303 : out std_logic; + out1308 : out std_logic; + out1309 : out std_logic; + out1311 : out std_logic; + out1318 : out std_logic; + out1319 : out std_logic; + out1320 : out std_logic; + out1323 : out std_logic; + out1324 : out std_logic; + out1326 : out std_logic; + out1327 : out std_logic; + out1329 : out std_logic; + out1337 : out std_logic; + out1339 : out std_logic; + out1340 : out std_logic; + out1341 : out std_logic; + out1344 : out std_logic; + out1346 : out std_logic; + out1349 : out std_logic; + out1353 : out std_logic; + out1356 : out std_logic; + out1362 : out std_logic; + out1363 : out std_logic; + out1364 : out std_logic; + out1365 : out std_logic; + out1366 : out std_logic; + out1368 : out std_logic; + out1370 : out std_logic; + out1375 : out std_logic; + out1378 : out std_logic; + out1381 : out std_logic; + out1383 : out std_logic; + out1387 : out std_logic + ); + end component; + + component muxb_784 is + port ( + in_sel : in std_logic; + out_data : out std_logic_vector(31 downto 0); + in_data0 : in std_logic_vector(31 downto 0); + in_data1 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_964 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_972 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_973 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_974 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_985 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_971 is + port ( + ne : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + component cmp_977 is + port ( + eq : out std_logic; + in1 : in std_logic_vector(31 downto 0); + in0 : in std_logic_vector(31 downto 0) + ); + end component; + + -- Declaration of signals + + signal sig_clock : std_logic; + signal sig_reset : std_logic; + signal augh_test_159 : std_logic; + signal augh_test_6 : std_logic; + signal augh_test_9 : std_logic; + signal augh_test_10 : std_logic; + signal augh_test_26 : std_logic; + signal augh_test_49 : std_logic; + signal augh_test_52 : std_logic; + signal augh_test_53 : std_logic; + signal augh_test_62 : std_logic; + signal augh_test_67 : std_logic; + signal augh_test_72 : std_logic; + signal augh_test_77 : std_logic; + signal augh_test_83 : std_logic; + signal augh_test_89 : std_logic; + signal augh_test_90 : std_logic; + signal augh_test_94 : std_logic; + signal augh_test_99 : std_logic; + signal augh_test_100 : std_logic; + signal augh_test_101 : std_logic; + signal augh_test_102 : std_logic; + signal augh_test_103 : std_logic; + signal augh_test_104 : std_logic; + signal augh_test_105 : std_logic; + signal augh_test_106 : std_logic; + signal augh_test_107 : std_logic; + signal augh_test_108 : std_logic; + signal augh_test_109 : std_logic; + signal augh_test_111 : std_logic; + signal augh_test_113 : std_logic; + signal augh_test_114 : std_logic; + signal augh_test_115 : std_logic; + signal augh_test_118 : std_logic; + signal augh_test_119 : std_logic; + signal augh_test_120 : std_logic; + signal augh_test_122 : std_logic; + signal augh_test_123 : std_logic; + signal augh_test_124 : std_logic; + signal augh_test_125 : std_logic; + signal augh_test_126 : std_logic; + signal augh_test_127 : std_logic; + signal augh_test_128 : std_logic; + signal augh_test_130 : std_logic; + signal augh_test_131 : std_logic; + signal augh_test_132 : std_logic; + signal augh_test_133 : std_logic; + signal augh_test_134 : std_logic; + signal augh_test_136 : std_logic; + signal augh_test_138 : std_logic; + signal augh_test_142 : std_logic; + signal augh_test_144 : std_logic; + signal augh_test_148 : std_logic; + signal augh_test_150 : std_logic; + signal augh_test_151 : std_logic; + signal augh_test_152 : std_logic; + signal augh_test_154 : std_logic; + signal augh_test_155 : std_logic; + signal augh_test_157 : std_logic; + signal augh_test_158 : std_logic; + signal augh_test_165 : std_logic; + signal augh_test_166 : std_logic; + signal augh_test_167 : std_logic; + signal augh_test_168 : std_logic; + signal sig_start : std_logic; + signal augh_test_171 : std_logic; + signal augh_test_178 : std_logic; + signal augh_test_179 : std_logic; + signal augh_test_180 : std_logic; + signal augh_test_182 : std_logic; + signal augh_test_183 : std_logic; + signal augh_test_184 : std_logic; + signal augh_test_186 : std_logic; + signal augh_test_187 : std_logic; + signal augh_test_188 : std_logic; + signal augh_test_189 : std_logic; + signal augh_test_194 : std_logic; + signal augh_test_196 : std_logic; + signal augh_test_197 : std_logic; + signal sig_990 : std_logic; + signal sig_991 : std_logic; + signal sig_992 : std_logic_vector(31 downto 0); + signal sig_993 : std_logic; + signal sig_994 : std_logic; + signal sig_995 : std_logic; + signal sig_996 : std_logic; + signal sig_997 : std_logic; + signal sig_998 : std_logic; + signal sig_999 : std_logic; + signal sig_1000 : std_logic; + signal sig_1001 : std_logic; + signal sig_1002 : std_logic; + signal sig_1003 : std_logic; + signal sig_1004 : std_logic; + signal sig_1005 : std_logic; + signal sig_1006 : std_logic; + signal sig_1007 : std_logic; + signal sig_1008 : std_logic; + signal sig_1009 : std_logic; + signal sig_1010 : std_logic; + signal sig_1011 : std_logic; + signal sig_1012 : std_logic; + signal sig_1013 : std_logic; + signal sig_1014 : std_logic; + signal sig_1015 : std_logic; + signal sig_1016 : std_logic; + signal sig_1017 : std_logic; + signal sig_1018 : std_logic; + signal sig_1019 : std_logic; + signal sig_1020 : std_logic; + signal sig_1021 : std_logic; + signal sig_1022 : std_logic; + signal sig_1023 : std_logic; + signal sig_1024 : std_logic; + signal sig_1025 : std_logic; + signal sig_1026 : std_logic; + signal sig_1027 : std_logic; + signal sig_1028 : std_logic; + signal sig_1029 : std_logic; + signal sig_1030 : std_logic; + signal sig_1031 : std_logic; + signal sig_1032 : std_logic; + signal sig_1033 : std_logic; + signal sig_1034 : std_logic; + signal sig_1035 : std_logic; + signal sig_1036 : std_logic; + signal sig_1037 : std_logic; + signal sig_1038 : std_logic; + signal sig_1039 : std_logic; + signal sig_1040 : std_logic; + signal sig_1041 : std_logic; + signal sig_1042 : std_logic; + signal sig_1043 : std_logic; + signal sig_1044 : std_logic; + signal sig_1045 : std_logic; + signal sig_1046 : std_logic; + signal sig_1047 : std_logic; + signal sig_1048 : std_logic; + signal sig_1049 : std_logic; + signal sig_1050 : std_logic; + signal sig_1051 : std_logic; + signal sig_1052 : std_logic; + signal sig_1053 : std_logic; + signal sig_1054 : std_logic; + signal sig_1055 : std_logic; + signal sig_1056 : std_logic; + signal sig_1057 : std_logic; + signal sig_1058 : std_logic; + signal sig_1059 : std_logic; + signal sig_1060 : std_logic; + signal sig_1061 : std_logic; + signal sig_1062 : std_logic; + signal sig_1063 : std_logic; + signal sig_1064 : std_logic; + signal sig_1065 : std_logic; + signal sig_1066 : std_logic; + signal sig_1067 : std_logic; + signal sig_1068 : std_logic; + signal sig_1069 : std_logic; + signal sig_1070 : std_logic; + signal sig_1071 : std_logic; + signal sig_1072 : std_logic; + signal sig_1073 : std_logic; + signal sig_1074 : std_logic; + signal sig_1075 : std_logic; + signal sig_1076 : std_logic; + signal sig_1077 : std_logic; + signal sig_1078 : std_logic; + signal sig_1079 : std_logic; + signal sig_1080 : std_logic; + signal sig_1081 : std_logic; + signal sig_1082 : std_logic; + signal sig_1083 : std_logic; + signal sig_1084 : std_logic; + signal sig_1085 : std_logic; + signal sig_1086 : std_logic; + signal sig_1087 : std_logic; + signal sig_1088 : std_logic; + signal sig_1089 : std_logic; + signal sig_1090 : std_logic; + signal sig_1091 : std_logic; + signal sig_1092 : std_logic; + signal sig_1093 : std_logic; + signal sig_1094 : std_logic; + signal sig_1095 : std_logic; + signal sig_1096 : std_logic; + signal sig_1097 : std_logic; + signal sig_1098 : std_logic; + signal sig_1099 : std_logic; + signal sig_1100 : std_logic; + signal sig_1101 : std_logic; + signal sig_1102 : std_logic; + signal sig_1103 : std_logic; + signal sig_1104 : std_logic; + signal sig_1105 : std_logic; + signal sig_1106 : std_logic; + signal sig_1107 : std_logic; + signal sig_1108 : std_logic; + signal sig_1109 : std_logic; + signal sig_1110 : std_logic; + signal sig_1111 : std_logic; + signal sig_1112 : std_logic; + signal sig_1113 : std_logic; + signal sig_1114 : std_logic; + signal sig_1115 : std_logic; + signal sig_1116 : std_logic; + signal sig_1117 : std_logic; + signal sig_1118 : std_logic; + signal sig_1119 : std_logic; + signal sig_1120 : std_logic; + signal sig_1121 : std_logic; + signal sig_1122 : std_logic; + signal sig_1123 : std_logic; + signal sig_1124 : std_logic; + signal sig_1125 : std_logic; + signal sig_1126 : std_logic; + signal sig_1127 : std_logic; + signal sig_1128 : std_logic; + signal sig_1129 : std_logic; + signal sig_1130 : std_logic; + signal sig_1131 : std_logic; + signal sig_1132 : std_logic; + signal sig_1133 : std_logic; + signal sig_1134 : std_logic; + signal sig_1135 : std_logic; + signal sig_1136 : std_logic; + signal sig_1137 : std_logic; + signal sig_1138 : std_logic; + signal sig_1139 : std_logic; + signal sig_1140 : std_logic; + signal sig_1141 : std_logic; + signal sig_1142 : std_logic; + signal sig_1143 : std_logic; + signal sig_1144 : std_logic; + signal sig_1145 : std_logic; + signal sig_1146 : std_logic; + signal sig_1147 : std_logic; + signal sig_1148 : std_logic; + signal sig_1149 : std_logic; + signal sig_1150 : std_logic; + signal sig_1151 : std_logic; + signal sig_1152 : std_logic; + signal sig_1153 : std_logic; + signal sig_1154 : std_logic; + signal sig_1155 : std_logic; + signal sig_1156 : std_logic; + signal sig_1157 : std_logic; + signal sig_1158 : std_logic; + signal sig_1159 : std_logic; + signal sig_1160 : std_logic; + signal sig_1161 : std_logic; + signal sig_1162 : std_logic; + signal sig_1163 : std_logic; + signal sig_1164 : std_logic; + signal sig_1165 : std_logic; + signal sig_1166 : std_logic; + signal sig_1167 : std_logic; + signal sig_1168 : std_logic; + signal sig_1169 : std_logic; + signal sig_1170 : std_logic; + signal sig_1171 : std_logic; + signal sig_1172 : std_logic; + signal sig_1173 : std_logic; + signal sig_1174 : std_logic; + signal sig_1175 : std_logic; + signal sig_1176 : std_logic; + signal sig_1177 : std_logic; + signal sig_1178 : std_logic; + signal sig_1179 : std_logic; + signal sig_1180 : std_logic; + signal sig_1181 : std_logic; + signal sig_1182 : std_logic; + signal sig_1183 : std_logic; + signal sig_1184 : std_logic; + signal sig_1185 : std_logic; + signal sig_1186 : std_logic; + signal sig_1187 : std_logic; + signal sig_1188 : std_logic; + signal sig_1189 : std_logic; + signal sig_1190 : std_logic; + signal sig_1191 : std_logic; + signal sig_1192 : std_logic; + signal sig_1193 : std_logic; + signal sig_1194 : std_logic; + signal sig_1195 : std_logic; + signal sig_1196 : std_logic; + signal sig_1197 : std_logic; + signal sig_1198 : std_logic; + signal sig_1199 : std_logic; + signal sig_1200 : std_logic; + signal sig_1201 : std_logic; + signal sig_1202 : std_logic; + signal sig_1203 : std_logic; + signal sig_1204 : std_logic; + signal sig_1205 : std_logic; + signal sig_1206 : std_logic; + signal sig_1207 : std_logic; + signal sig_1208 : std_logic; + signal sig_1209 : std_logic; + signal sig_1210 : std_logic; + signal sig_1211 : std_logic; + signal sig_1212 : std_logic; + signal sig_1213 : std_logic; + signal sig_1214 : std_logic; + signal sig_1215 : std_logic; + signal sig_1216 : std_logic; + signal sig_1217 : std_logic; + signal sig_1218 : std_logic; + signal sig_1219 : std_logic; + signal sig_1220 : std_logic; + signal sig_1221 : std_logic; + signal sig_1222 : std_logic; + signal sig_1223 : std_logic; + signal sig_1224 : std_logic; + signal sig_1225 : std_logic; + signal sig_1226 : std_logic; + signal sig_1227 : std_logic; + signal sig_1228 : std_logic; + signal sig_1229 : std_logic; + signal sig_1230 : std_logic; + signal sig_1231 : std_logic; + signal sig_1232 : std_logic; + signal sig_1233 : std_logic; + signal sig_1234 : std_logic; + signal sig_1235 : std_logic; + signal sig_1236 : std_logic; + signal sig_1237 : std_logic; + signal sig_1238 : std_logic; + signal sig_1239 : std_logic; + signal sig_1240 : std_logic; + signal sig_1241 : std_logic; + signal sig_1242 : std_logic; + signal sig_1243 : std_logic; + signal sig_1244 : std_logic; + signal sig_1245 : std_logic; + signal sig_1246 : std_logic; + signal sig_1247 : std_logic; + signal sig_1248 : std_logic; + signal sig_1249 : std_logic; + signal sig_1250 : std_logic; + signal sig_1251 : std_logic; + signal sig_1252 : std_logic; + signal sig_1253 : std_logic; + signal sig_1254 : std_logic; + signal sig_1255 : std_logic; + signal sig_1256 : std_logic; + signal sig_1257 : std_logic; + signal sig_1258 : std_logic; + signal sig_1259 : std_logic; + signal sig_1260 : std_logic; + signal sig_1261 : std_logic; + signal sig_1262 : std_logic; + signal sig_1263 : std_logic; + signal sig_1264 : std_logic; + signal sig_1265 : std_logic; + signal sig_1266 : std_logic; + signal sig_1267 : std_logic; + signal sig_1268 : std_logic; + signal sig_1269 : std_logic; + signal sig_1270 : std_logic; + signal sig_1271 : std_logic; + signal sig_1272 : std_logic; + signal sig_1273 : std_logic; + signal sig_1274 : std_logic; + signal sig_1275 : std_logic; + signal sig_1276 : std_logic; + signal sig_1277 : std_logic; + signal sig_1278 : std_logic; + signal sig_1279 : std_logic; + signal sig_1280 : std_logic; + signal sig_1281 : std_logic; + signal sig_1282 : std_logic; + signal sig_1283 : std_logic; + signal sig_1284 : std_logic; + signal sig_1285 : std_logic; + signal sig_1286 : std_logic; + signal sig_1287 : std_logic; + signal sig_1288 : std_logic; + signal sig_1289 : std_logic; + signal sig_1290 : std_logic; + signal sig_1291 : std_logic; + signal sig_1292 : std_logic; + signal sig_1293 : std_logic; + signal sig_1294 : std_logic; + signal sig_1295 : std_logic; + signal sig_1296 : std_logic; + signal sig_1297 : std_logic; + signal sig_1298 : std_logic; + signal sig_1299 : std_logic; + signal sig_1300 : std_logic; + signal sig_1301 : std_logic; + signal sig_1302 : std_logic; + signal sig_1303 : std_logic; + signal sig_1304 : std_logic; + signal sig_1305 : std_logic; + signal sig_1306 : std_logic; + signal sig_1307 : std_logic; + signal sig_1308 : std_logic; + signal sig_1309 : std_logic; + signal sig_1310 : std_logic; + signal sig_1311 : std_logic; + signal sig_1312 : std_logic; + signal sig_1313 : std_logic; + signal sig_1314 : std_logic; + signal sig_1315 : std_logic; + signal sig_1316 : std_logic; + signal sig_1317 : std_logic; + signal sig_1318 : std_logic; + signal sig_1319 : std_logic; + signal sig_1320 : std_logic; + signal sig_1321 : std_logic; + signal sig_1322 : std_logic; + signal sig_1323 : std_logic; + signal sig_1324 : std_logic; + signal sig_1325 : std_logic; + signal sig_1326 : std_logic; + signal sig_1327 : std_logic; + signal sig_1328 : std_logic; + signal sig_1329 : std_logic; + signal sig_1330 : std_logic; + signal sig_1331 : std_logic; + signal sig_1332 : std_logic; + signal sig_1333 : std_logic; + signal sig_1334 : std_logic; + signal sig_1335 : std_logic; + signal sig_1336 : std_logic; + signal sig_1337 : std_logic; + signal sig_1338 : std_logic; + signal sig_1339 : std_logic; + signal sig_1340 : std_logic; + signal sig_1341 : std_logic; + signal sig_1342 : std_logic; + signal sig_1343 : std_logic; + signal sig_1344 : std_logic; + signal sig_1345 : std_logic; + signal sig_1346 : std_logic; + signal sig_1347 : std_logic; + signal sig_1348 : std_logic; + signal sig_1349 : std_logic; + signal sig_1350 : std_logic; + signal sig_1351 : std_logic; + signal sig_1352 : std_logic; + signal sig_1353 : std_logic; + signal sig_1354 : std_logic; + signal sig_1355 : std_logic; + signal sig_1356 : std_logic; + signal sig_1357 : std_logic; + signal sig_1358 : std_logic; + signal sig_1359 : std_logic; + signal sig_1360 : std_logic; + signal sig_1361 : std_logic; + signal sig_1362 : std_logic; + signal sig_1363 : std_logic; + signal sig_1364 : std_logic; + signal sig_1365 : std_logic; + signal sig_1366 : std_logic; + signal sig_1367 : std_logic; + signal sig_1368 : std_logic; + signal sig_1369 : std_logic; + signal sig_1370 : std_logic; + signal sig_1371 : std_logic; + signal sig_1372 : std_logic; + signal sig_1373 : std_logic; + signal sig_1374 : std_logic; + signal sig_1375 : std_logic; + signal sig_1376 : std_logic; + signal sig_1377 : std_logic; + signal sig_1378 : std_logic; + signal sig_1379 : std_logic; + signal sig_1380 : std_logic; + signal sig_1381 : std_logic; + signal sig_1382 : std_logic; + signal sig_1383 : std_logic; + signal sig_1384 : std_logic; + signal sig_1385 : std_logic; + signal sig_1386 : std_logic; + signal sig_1387 : std_logic; + signal sig_1388 : std_logic; + signal sig_1389 : std_logic; + signal sig_1390 : std_logic; + signal sig_1391 : std_logic; + signal sig_1392 : std_logic; + signal sig_1393 : std_logic; + signal sig_1394 : std_logic; + signal sig_1395 : std_logic; + signal sig_1396 : std_logic; + signal sig_1397 : std_logic; + signal sig_1398 : std_logic; + signal sig_1399 : std_logic; + signal sig_1400 : std_logic; + signal sig_1401 : std_logic; + signal sig_1402 : std_logic; + signal sig_1403 : std_logic; + signal sig_1404 : std_logic; + signal sig_1405 : std_logic; + signal sig_1406 : std_logic; + signal sig_1407 : std_logic; + signal sig_1408 : std_logic; + signal sig_1409 : std_logic; + signal sig_1410 : std_logic; + signal sig_1411 : std_logic; + signal sig_1412 : std_logic; + signal sig_1413 : std_logic; + signal sig_1414 : std_logic; + signal sig_1415 : std_logic; + signal sig_1416 : std_logic; + signal sig_1417 : std_logic; + signal sig_1418 : std_logic; + signal sig_1419 : std_logic; + signal sig_1420 : std_logic; + signal sig_1421 : std_logic; + signal sig_1422 : std_logic; + signal sig_1423 : std_logic; + signal sig_1424 : std_logic; + signal sig_1425 : std_logic; + signal sig_1426 : std_logic; + signal sig_1427 : std_logic; + signal sig_1428 : std_logic; + signal sig_1429 : std_logic; + signal sig_1430 : std_logic; + signal sig_1431 : std_logic; + signal sig_1432 : std_logic; + signal sig_1433 : std_logic; + signal sig_1434 : std_logic; + signal sig_1435 : std_logic; + signal sig_1436 : std_logic; + signal sig_1437 : std_logic; + signal sig_1438 : std_logic; + signal sig_1439 : std_logic; + signal sig_1440 : std_logic; + signal sig_1441 : std_logic; + signal sig_1442 : std_logic; + signal sig_1443 : std_logic; + signal sig_1444 : std_logic; + signal sig_1445 : std_logic; + signal sig_1446 : std_logic; + signal sig_1447 : std_logic; + signal sig_1448 : std_logic; + signal sig_1449 : std_logic; + signal sig_1450 : std_logic; + signal sig_1451 : std_logic; + signal sig_1452 : std_logic; + signal sig_1453 : std_logic; + signal sig_1454 : std_logic; + signal sig_1455 : std_logic; + signal sig_1456 : std_logic; + signal sig_1457 : std_logic; + signal sig_1458 : std_logic; + signal sig_1459 : std_logic; + signal sig_1460 : std_logic; + signal sig_1461 : std_logic; + signal sig_1462 : std_logic; + signal sig_1463 : std_logic; + signal sig_1464 : std_logic; + signal sig_1465 : std_logic; + signal sig_1466 : std_logic; + signal sig_1467 : std_logic; + signal sig_1468 : std_logic; + signal sig_1469 : std_logic; + signal sig_1470 : std_logic; + signal sig_1471 : std_logic; + signal sig_1472 : std_logic; + signal sig_1473 : std_logic; + signal sig_1474 : std_logic; + signal sig_1475 : std_logic; + signal sig_1476 : std_logic; + signal sig_1477 : std_logic; + signal sig_1478 : std_logic; + signal sig_1479 : std_logic; + signal sig_1480 : std_logic; + signal sig_1481 : std_logic; + signal sig_1482 : std_logic; + signal sig_1483 : std_logic; + signal sig_1484 : std_logic; + signal sig_1485 : std_logic; + signal sig_1486 : std_logic; + signal sig_1487 : std_logic; + signal sig_1488 : std_logic; + signal sig_1489 : std_logic; + signal sig_1490 : std_logic; + signal sig_1491 : std_logic; + signal sig_1492 : std_logic; + signal sig_1493 : std_logic; + signal sig_1494 : std_logic; + signal sig_1495 : std_logic; + signal sig_1496 : std_logic; + signal sig_1497 : std_logic; + signal sig_1498 : std_logic; + signal sig_1499 : std_logic; + signal sig_1500 : std_logic; + signal sig_1501 : std_logic; + signal sig_1502 : std_logic; + signal sig_1503 : std_logic; + signal sig_1504 : std_logic; + signal sig_1505 : std_logic; + signal sig_1506 : std_logic; + signal sig_1507 : std_logic; + signal sig_1508 : std_logic; + signal sig_1509 : std_logic; + signal sig_1510 : std_logic; + signal sig_1511 : std_logic; + signal sig_1512 : std_logic; + signal sig_1513 : std_logic; + signal sig_1514 : std_logic; + signal sig_1515 : std_logic; + signal sig_1516 : std_logic; + signal sig_1517 : std_logic; + signal sig_1518 : std_logic; + signal sig_1519 : std_logic; + signal sig_1520 : std_logic; + signal sig_1521 : std_logic; + signal sig_1522 : std_logic; + signal sig_1523 : std_logic; + signal sig_1524 : std_logic; + signal sig_1525 : std_logic; + signal sig_1526 : std_logic; + signal sig_1527 : std_logic; + signal sig_1528 : std_logic; + signal sig_1529 : std_logic; + signal sig_1530 : std_logic; + signal sig_1531 : std_logic; + signal sig_1532 : std_logic; + signal sig_1533 : std_logic; + signal sig_1534 : std_logic; + signal sig_1535 : std_logic; + signal sig_1536 : std_logic; + signal sig_1537 : std_logic; + signal sig_1538 : std_logic; + signal sig_1539 : std_logic; + signal sig_1540 : std_logic; + signal sig_1541 : std_logic; + signal sig_1542 : std_logic; + signal sig_1543 : std_logic; + signal sig_1544 : std_logic; + signal sig_1545 : std_logic; + signal sig_1546 : std_logic; + signal sig_1547 : std_logic; + signal sig_1548 : std_logic; + signal sig_1549 : std_logic; + signal sig_1550 : std_logic; + signal sig_1551 : std_logic; + signal sig_1552 : std_logic; + signal sig_1553 : std_logic; + signal sig_1554 : std_logic; + signal sig_1555 : std_logic; + signal sig_1556 : std_logic; + signal sig_1557 : std_logic; + signal sig_1558 : std_logic; + signal sig_1559 : std_logic; + signal sig_1560 : std_logic; + signal sig_1561 : std_logic; + signal sig_1562 : std_logic; + signal sig_1563 : std_logic; + signal sig_1564 : std_logic; + signal sig_1565 : std_logic; + signal sig_1566 : std_logic; + signal sig_1567 : std_logic; + signal sig_1568 : std_logic; + signal sig_1569 : std_logic; + signal sig_1570 : std_logic; + signal sig_1571 : std_logic; + signal sig_1572 : std_logic; + signal sig_1573 : std_logic; + signal sig_1574 : std_logic; + signal sig_1575 : std_logic; + signal sig_1576 : std_logic; + signal sig_1577 : std_logic; + signal sig_1578 : std_logic; + signal sig_1579 : std_logic; + signal sig_1580 : std_logic; + signal sig_1581 : std_logic; + signal sig_1582 : std_logic; + signal sig_1583 : std_logic; + signal sig_1584 : std_logic; + signal sig_1585 : std_logic_vector(40 downto 0); + signal sig_1586 : std_logic; + signal sig_1587 : std_logic_vector(40 downto 0); + signal sig_1588 : std_logic_vector(40 downto 0); + signal sig_1589 : std_logic; + signal sig_1590 : std_logic_vector(40 downto 0); + signal sig_1591 : std_logic; + signal sig_1592 : std_logic_vector(40 downto 0); + signal sig_1593 : std_logic; + signal sig_1594 : std_logic; + signal sig_1595 : std_logic; + signal sig_1596 : std_logic_vector(40 downto 0); + signal sig_1597 : std_logic; + signal sig_1598 : std_logic; + signal sig_1599 : std_logic; + signal sig_1600 : std_logic_vector(40 downto 0); + signal sig_1601 : std_logic; + signal sig_1602 : std_logic; + signal sig_1603 : std_logic; + signal sig_1604 : std_logic; + signal sig_1605 : std_logic; + signal sig_1606 : std_logic; + signal sig_1607 : std_logic; + signal sig_1608 : std_logic; + signal sig_1609 : std_logic_vector(38 downto 0); + signal sig_1610 : std_logic_vector(38 downto 0); + signal sig_1611 : std_logic_vector(24 downto 0); + signal sig_1612 : std_logic_vector(38 downto 0); + signal sig_1613 : std_logic_vector(31 downto 0); + signal sig_1614 : std_logic_vector(40 downto 0); + signal sig_1615 : std_logic; + signal sig_1616 : std_logic; + signal sig_1617 : std_logic; + signal sig_1618 : std_logic; + signal sig_1619 : std_logic_vector(40 downto 0); + signal sig_1620 : std_logic; + signal sig_1621 : std_logic_vector(40 downto 0); + signal sig_1622 : std_logic; + signal sig_1623 : std_logic; + signal sig_1624 : std_logic_vector(40 downto 0); + signal sig_1625 : std_logic; + signal sig_1626 : std_logic_vector(31 downto 0); + signal sig_1627 : std_logic_vector(40 downto 0); + signal sig_1628 : std_logic_vector(40 downto 0); + signal sig_1629 : std_logic_vector(31 downto 0); + signal sig_1630 : std_logic_vector(5 downto 0); + signal sig_1631 : std_logic_vector(7 downto 0); + signal sig_1632 : std_logic_vector(31 downto 0); + signal sig_1633 : std_logic_vector(31 downto 0); + signal sig_1634 : std_logic_vector(31 downto 0); + signal sig_1635 : std_logic_vector(31 downto 0); + signal sig_1636 : std_logic_vector(31 downto 0); + signal sig_1637 : std_logic_vector(31 downto 0); + signal sig_1638 : std_logic_vector(20 downto 0); + signal sig_1639 : std_logic_vector(31 downto 0); + signal sig_1640 : std_logic_vector(31 downto 0); + signal sig_1641 : std_logic_vector(31 downto 0); + signal sig_1642 : std_logic_vector(31 downto 0); + signal sig_1643 : std_logic_vector(31 downto 0); + signal sig_1644 : std_logic_vector(7 downto 0); + signal sig_1645 : std_logic_vector(5 downto 0); + signal sig_1646 : std_logic_vector(7 downto 0); + signal sig_1647 : std_logic_vector(31 downto 0); + signal sig_1648 : std_logic_vector(31 downto 0); + signal sig_1649 : std_logic_vector(8 downto 0); + signal sig_1650 : std_logic_vector(8 downto 0); + signal sig_1651 : std_logic_vector(31 downto 0); + signal sig_1652 : std_logic_vector(31 downto 0); + signal sig_1653 : std_logic_vector(8 downto 0); + signal sig_1654 : std_logic_vector(8 downto 0); + signal sig_1655 : std_logic_vector(31 downto 0); + signal sig_1656 : std_logic_vector(31 downto 0); + signal sig_1657 : std_logic_vector(31 downto 0); + signal sig_1658 : std_logic_vector(31 downto 0); + signal sig_1659 : std_logic_vector(31 downto 0); + signal sig_1660 : std_logic_vector(31 downto 0); + signal sig_1661 : std_logic_vector(31 downto 0); + signal sig_1662 : std_logic; + signal sig_1663 : std_logic_vector(1 downto 0); + signal sig_1664 : std_logic_vector(7 downto 0); + signal sig_1665 : std_logic_vector(7 downto 0); + signal sig_1666 : std_logic_vector(40 downto 0); + signal sig_1667 : std_logic_vector(40 downto 0); + signal sig_1668 : std_logic_vector(40 downto 0); + signal sig_1669 : std_logic; + signal sig_1670 : std_logic; + signal sig_1671 : std_logic_vector(31 downto 0); + signal sig_1672 : std_logic_vector(31 downto 0); + signal sig_1673 : std_logic_vector(40 downto 0); + signal sig_1674 : std_logic_vector(40 downto 0); + signal sig_1675 : std_logic_vector(40 downto 0); + signal sig_1676 : std_logic_vector(40 downto 0); + signal sig_1677 : std_logic_vector(31 downto 0); + signal sig_1678 : std_logic_vector(31 downto 0); + signal sig_1679 : std_logic_vector(40 downto 0); + signal sig_1680 : std_logic_vector(31 downto 0); + signal sig_1681 : std_logic_vector(31 downto 0); + signal sig_1682 : std_logic_vector(31 downto 0); + signal sig_1683 : std_logic_vector(31 downto 0); + signal sig_1684 : std_logic_vector(31 downto 0); + signal sig_1685 : std_logic_vector(31 downto 0); + signal sig_1686 : std_logic_vector(31 downto 0); + signal sig_1687 : std_logic_vector(31 downto 0); + signal sig_1688 : std_logic_vector(24 downto 0); + signal sig_1689 : std_logic_vector(40 downto 0); + signal sig_1690 : std_logic_vector(31 downto 0); + signal sig_1691 : std_logic_vector(9 downto 0); + signal sig_1692 : std_logic_vector(8 downto 0); + signal sig_1693 : std_logic_vector(14 downto 0); + signal sig_1694 : std_logic_vector(14 downto 0); + signal sig_1695 : std_logic_vector(6 downto 0); + signal sig_1696 : std_logic_vector(6 downto 0); + signal sig_1697 : std_logic_vector(6 downto 0); + signal sig_1698 : std_logic_vector(6 downto 0); + signal sig_1699 : std_logic_vector(6 downto 0); + signal sig_1700 : std_logic_vector(6 downto 0); + signal sig_1701 : std_logic_vector(6 downto 0); + signal sig_1702 : std_logic_vector(6 downto 0); + signal sig_1703 : std_logic_vector(9 downto 0); + signal sig_1704 : std_logic_vector(6 downto 0); + signal sig_1705 : std_logic_vector(9 downto 0); + signal sig_1706 : std_logic_vector(6 downto 0); + signal sig_1707 : std_logic_vector(7 downto 0); + signal sig_1708 : std_logic_vector(31 downto 0); + signal sig_1709 : std_logic_vector(31 downto 0); + signal sig_1710 : std_logic_vector(31 downto 0); + signal sig_1711 : std_logic_vector(31 downto 0); + signal sig_1712 : std_logic_vector(31 downto 0); + signal sig_1713 : std_logic_vector(31 downto 0); + signal sig_1714 : std_logic_vector(31 downto 0); + signal sig_1715 : std_logic_vector(31 downto 0); + signal sig_1716 : std_logic_vector(31 downto 0); + + -- Other inlined components + + signal mux_967 : std_logic_vector(31 downto 0); + signal and_976 : std_logic; + signal and_982 : std_logic_vector(31 downto 0); + signal and_983 : std_logic_vector(27 downto 0); + signal and_984 : std_logic_vector(31 downto 0); + signal mux_689 : std_logic_vector(31 downto 0); + signal mux_690 : std_logic_vector(6 downto 0); + signal mux_691 : std_logic_vector(6 downto 0); + signal and_853 : std_logic_vector(31 downto 0); + signal izigzagmatrix_i : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_233 : std_logic_vector(31 downto 0); + signal izigzagmatrix_out_idx : std_logic_vector(31 downto 0) := (others => '0'); + signal iquantize_qidx : std_logic_vector(1 downto 0) := (others => '0'); + signal write8_u8 : std_logic_vector(7 downto 0) := (others => '0'); + signal p_jinfo_image_height : std_logic_vector(15 downto 0) := (others => '0'); + signal p_jinfo_image_width : std_logic_vector(15 downto 0) := (others => '0'); + signal mux_671 : std_logic_vector(31 downto 0); + signal p_jinfo_num_components : std_logic_vector(7 downto 0) := (others => '0'); + signal p_jinfo_smp_fact : std_logic_vector(1 downto 0) := (others => '0'); + signal mux_665 : std_logic_vector(1 downto 0); + signal mux_663 : std_logic_vector(31 downto 0); + signal mux_664 : std_logic_vector(1 downto 0); + signal mux_659 : std_logic_vector(31 downto 0); + signal mux_660 : std_logic_vector(1 downto 0); + signal mux_661 : std_logic_vector(1 downto 0); + signal mux_652 : std_logic_vector(12 downto 0); + signal mux_648 : std_logic_vector(31 downto 0); + signal mux_633 : std_logic_vector(31 downto 0); + signal mux_622 : std_logic_vector(31 downto 0); + signal mux_614 : std_logic_vector(31 downto 0); + signal mux_616 : std_logic_vector(31 downto 0); + signal p_jinfo_mcuwidth : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_602 : std_logic_vector(31 downto 0); + signal p_jinfo_mcuheight : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_600 : std_logic_vector(31 downto 0); + signal p_jinfo_nummcu : std_logic_vector(31 downto 0) := (others => '0'); + signal i_jinfo_jpeg_data : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_593 : std_logic_vector(31 downto 0); + signal curhuffreadbuf_idx : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_587 : std_logic_vector(31 downto 0); + signal outdata_image_width : std_logic_vector(7 downto 0) := (others => '0'); + signal mux_585 : std_logic_vector(15 downto 0); + signal outdata_image_height : std_logic_vector(7 downto 0) := (others => '0'); + signal mux_580 : std_logic_vector(7 downto 0); + signal mux_569 : std_logic_vector(7 downto 0); + signal mux_567 : std_logic_vector(31 downto 0); + signal mux_568 : std_logic_vector(7 downto 0); + signal mux_563 : std_logic_vector(8 downto 0); + signal mux_565 : std_logic_vector(8 downto 0); + signal mux_561 : std_logic_vector(31 downto 0); + signal mux_562 : std_logic_vector(8 downto 0); + signal mux_557 : std_logic_vector(31 downto 0); + signal mux_558 : std_logic_vector(5 downto 0); + signal mux_559 : std_logic_vector(5 downto 0); + signal mux_555 : std_logic_vector(31 downto 0); + signal mux_551 : std_logic_vector(31 downto 0); + signal mux_553 : std_logic_vector(31 downto 0); + signal mux_549 : std_logic_vector(31 downto 0); + signal mux_545 : std_logic_vector(31 downto 0); + signal mux_547 : std_logic_vector(31 downto 0); + signal mux_543 : std_logic_vector(31 downto 0); + signal mux_731 : std_logic_vector(7 downto 0); + signal mux_727 : std_logic_vector(6 downto 0); + signal mux_723 : std_logic_vector(9 downto 0); + signal mux_719 : std_logic_vector(6 downto 0); + signal mux_539 : std_logic_vector(31 downto 0); + signal mux_541 : std_logic_vector(31 downto 0); + signal mux_537 : std_logic_vector(31 downto 0); + signal mux_533 : std_logic_vector(31 downto 0); + signal mux_535 : std_logic_vector(31 downto 0); + signal mux_715 : std_logic_vector(9 downto 0); + signal mux_711 : std_logic; + signal mux_705 : std_logic_vector(31 downto 0); + signal mux_706 : std_logic_vector(6 downto 0); + signal mux_707 : std_logic_vector(6 downto 0); + signal mux_531 : std_logic_vector(31 downto 0); + signal mux_529 : std_logic_vector(31 downto 0); + signal mux_695 : std_logic; + signal mux_524 : std_logic_vector(4 downto 0); + signal mux_521 : std_logic_vector(31 downto 0); + signal readbuf_idx : std_logic_vector(31 downto 0) := (others => '0'); + signal read_byte : std_logic_vector(7 downto 0) := (others => '0'); + signal read_word : std_logic_vector(15 downto 0) := (others => '0'); + signal read_word_c : std_logic_vector(7 downto 0) := (others => '0'); + signal mux_519 : std_logic_vector(31 downto 0); + signal mux_517 : std_logic_vector(7 downto 0); + signal next_marker : std_logic_vector(7 downto 0) := (others => '0'); + signal next_marker_c : std_logic_vector(7 downto 0) := (others => '0'); + signal get_sof_ci : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_507 : std_logic_vector(31 downto 0); + signal mux_505 : std_logic_vector(31 downto 0); + signal get_sof_i_comp_info_id : std_logic_vector(1 downto 0) := (others => '0'); + signal mux_501 : std_logic_vector(31 downto 0); + signal get_sof_i_comp_info_h_samp_factor : std_logic_vector(1 downto 0) := (others => '0'); + signal get_sof_i_comp_info_quant_tbl_no : std_logic_vector(1 downto 0) := (others => '0'); + signal mux_492 : std_logic_vector(31 downto 0); + signal mux_488 : std_logic_vector(31 downto 0); + signal mux_490 : std_logic_vector(31 downto 0); + signal get_sos_num_comp : std_logic_vector(7 downto 0) := (others => '0'); + signal mux_486 : std_logic_vector(31 downto 0); + signal get_sos_i : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_482 : std_logic_vector(31 downto 0); + signal mux_484 : std_logic_vector(31 downto 0); + signal get_sos_c : std_logic := '0'; + signal mux_480 : std_logic_vector(31 downto 0); + signal get_sos_cc : std_logic_vector(7 downto 0) := (others => '0'); + signal mux_476 : std_logic_vector(31 downto 0); + signal mux_478 : std_logic_vector(8 downto 0); + signal get_sos_ci : std_logic_vector(31 downto 0) := (others => '0'); + signal get_sos_j : std_logic_vector(31 downto 0) := (others => '0'); + signal get_sos_i_comp_info_dc_tbl_no : std_logic_vector(1 downto 0) := (others => '0'); + signal get_dht_length : std_logic_vector(31 downto 0) := (others => '0'); + signal get_dht_index : std_logic := '0'; + signal mux_459 : std_logic_vector(31 downto 0); + signal get_dht_i : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_455 : std_logic_vector(31 downto 0); + signal mux_457 : std_logic_vector(31 downto 0); + signal get_dht_count : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_453 : std_logic_vector(31 downto 0); + signal mux_449 : std_logic_vector(31 downto 0); + signal mux_451 : std_logic_vector(31 downto 0); + signal get_dht_is_ac : std_logic := '0'; + signal get_dqt_length : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_447 : std_logic_vector(31 downto 0); + signal get_dqt_prec : std_logic_vector(3 downto 0) := (others => '0'); + signal mux_443 : std_logic_vector(31 downto 0); + signal mux_445 : std_logic_vector(8 downto 0); + signal get_dqt_num : std_logic_vector(1 downto 0) := (others => '0'); + signal get_dqt_i : std_logic_vector(31 downto 0) := (others => '0'); + signal get_dqt_tmp : std_logic_vector(15 downto 0) := (others => '0'); + signal read_markers_unread_marker : std_logic_vector(7 downto 0) := (others => '0'); + signal read_markers_sow_soi : std_logic := '0'; + signal mux_430 : std_logic_vector(31 downto 0); + signal mux_422 : std_logic_vector(31 downto 0); + signal mux_424 : std_logic_vector(31 downto 0); + signal chenidct_i : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_416 : std_logic_vector(31 downto 0); + signal chenidct_aidx : std_logic_vector(31 downto 0) := (others => '0'); + signal chenidct_a0 : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_410 : std_logic_vector(31 downto 0); + signal chenidct_a1 : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_408 : std_logic_vector(31 downto 0); + signal chenidct_a2 : std_logic_vector(31 downto 0) := (others => '0'); + signal chenidct_a3 : std_logic_vector(31 downto 0) := (others => '0'); + signal chenidct_b0 : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_398 : std_logic_vector(31 downto 0); + signal mux_400 : std_logic_vector(31 downto 0); + signal chenidct_b1 : std_logic_vector(31 downto 0) := (others => '0'); + signal chenidct_b2 : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_392 : std_logic_vector(31 downto 0); + signal mux_394 : std_logic_vector(31 downto 0); + signal chenidct_b3 : std_logic_vector(31 downto 0) := (others => '0'); + signal chenidct_c0 : std_logic_vector(31 downto 0) := (others => '0'); + signal chenidct_c1 : std_logic_vector(31 downto 0) := (others => '0'); + signal chenidct_c2 : std_logic_vector(31 downto 0) := (others => '0'); + signal chenidct_c3 : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_378 : std_logic_vector(7 downto 0); + signal mux_379 : std_logic_vector(9 downto 0); + signal mux_375 : std_logic_vector(1 downto 0); + signal mux_373 : std_logic_vector(1 downto 0); + signal current_read_byte : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_365 : std_logic_vector(31 downto 0); + signal mux_367 : std_logic_vector(31 downto 0); + signal read_position : std_logic_vector(31 downto 0) := "11111111111111111111111111111111"; + signal pgetc : std_logic_vector(7 downto 0) := (others => '0'); + signal pgetc_temp : std_logic_vector(7 downto 0) := (others => '0'); + signal buf_getb : std_logic := '0'; + signal buf_getv : std_logic_vector(31 downto 0) := (others => '0'); + signal buf_getv_n : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_363 : std_logic_vector(31 downto 0); + signal buf_getv_p : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_359 : std_logic_vector(31 downto 0); + signal mux_361 : std_logic_vector(31 downto 0); + signal buf_getv_rv : std_logic_vector(31 downto 0) := (others => '0'); + signal huff_make_dhuff_tb_ac : std_logic_vector(31 downto 0) := (others => '0'); + signal huff_make_dhuff_tb_ac_tbl_no : std_logic := '0'; + signal huff_make_dhuff_tb_ac_p_dhtbl_ml : std_logic_vector(31 downto 0) := (others => '0'); + signal huff_make_dhuff_tb_ac_i_c0 : std_logic_vector(31 downto 0) := (others => '0'); + signal huff_make_dhuff_tb_ac_j : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_347 : std_logic_vector(31 downto 0); + signal huff_make_dhuff_tb_ac_p : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_345 : std_logic_vector(31 downto 0); + signal huff_make_dhuff_tb_ac_code : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_341 : std_logic_vector(2 downto 0); + signal mux_343 : std_logic_vector(1 downto 0); + signal huff_make_dhuff_tb_ac_size : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_339 : std_logic_vector(2 downto 0); + signal huff_make_dhuff_tb_ac_l : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_335 : std_logic_vector(31 downto 0); + signal mux_337 : std_logic_vector(2 downto 0); + signal mux_333 : std_logic_vector(31 downto 0); + signal mux_331 : std_logic_vector(31 downto 0); + signal huff_make_dhuff_tb_dc : std_logic_vector(31 downto 0) := (others => '0'); + signal huff_make_dhuff_tb_dc_tbl_no : std_logic := '0'; + signal huff_make_dhuff_tb_dc_p_dhtbl_ml : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_323 : std_logic_vector(5 downto 0); + signal huff_make_dhuff_tb_dc_i_c0 : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_320 : std_logic_vector(31 downto 0); + signal mux_322 : std_logic_vector(31 downto 0); + signal huff_make_dhuff_tb_dc_j : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_317 : std_logic_vector(1 downto 0); + signal huff_make_dhuff_tb_dc_p : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_314 : std_logic_vector(31 downto 0); + signal mux_315 : std_logic_vector(31 downto 0); + signal mux_316 : std_logic_vector(31 downto 0); + signal huff_make_dhuff_tb_dc_code : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_313 : std_logic_vector(8 downto 0); + signal huff_make_dhuff_tb_dc_size : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_308 : std_logic_vector(2 downto 0); + signal huff_make_dhuff_tb_dc_l : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_306 : std_logic_vector(40 downto 0); + signal mux_307 : std_logic_vector(40 downto 0); + signal mux_302 : std_logic_vector(40 downto 0); + signal mux_303 : std_logic_vector(40 downto 0); + signal decodehuffman_ac : std_logic_vector(31 downto 0) := (others => '0'); + signal decodehuffman_ac_tbl_no : std_logic := '0'; + signal mux_294 : std_logic_vector(1 downto 0); + signal decodehuffman_ac_dhuff_ml : std_logic_vector(5 downto 0) := (others => '0'); + signal mux_290 : std_logic_vector(40 downto 0); + signal mux_291 : std_logic_vector(40 downto 0); + signal mux_292 : std_logic_vector(31 downto 0); + signal decodehuffman_ac_code : std_logic_vector(31 downto 0) := (others => '0'); + signal decodehuffman_ac_l : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_286 : std_logic_vector(31 downto 0); + signal decodehuffman_ac_p : std_logic_vector(8 downto 0) := (others => '0'); + signal decodehuffman_dc : std_logic_vector(31 downto 0) := (others => '0'); + signal decodehuffman_dc_tbl_no : std_logic := '0'; + signal decodehuffman_dc_dhuff_ml : std_logic_vector(5 downto 0) := (others => '0'); + signal mux_275 : std_logic_vector(31 downto 0); + signal decodehuffman_dc_code : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_272 : std_logic_vector(38 downto 0); + signal mux_274 : std_logic_vector(31 downto 0); + signal decodehuffman_dc_l : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_271 : std_logic_vector(38 downto 0); + signal decodehuffman_dc_p : std_logic_vector(8 downto 0) := (others => '0'); + signal decodehuffmcu_bufdim1 : std_logic_vector(1 downto 0) := (others => '0'); + signal mux_266 : std_logic_vector(38 downto 0); + signal mux_265 : std_logic_vector(38 downto 0); + signal decodehuffmcu_s : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_260 : std_logic_vector(38 downto 0); + signal mux_261 : std_logic_vector(38 downto 0); + signal mux_262 : std_logic_vector(31 downto 0); + signal decodehuffmcu_diff : std_logic_vector(31 downto 0) := (others => '0'); + signal mux_257 : std_logic_vector(31 downto 0); + signal decodehuffmcu_tbl_no : std_logic := '0'; + signal decodehuffmcu_i : std_logic_vector(31 downto 0) := (others => '0'); + signal decodehuffmcu_k : std_logic_vector(31 downto 0) := (others => '0'); + signal decodehuffmcu_n : std_logic_vector(27 downto 0) := (others => '0'); + signal writeoneblock_outidx : std_logic_vector(1 downto 0) := (others => '0'); + signal writeoneblock_indim1 : std_logic_vector(1 downto 0) := (others => '0'); + signal writeoneblock_width : std_logic_vector(31 downto 0) := (others => '0'); + signal writeoneblock_height : std_logic_vector(31 downto 0) := (others => '0'); + signal writeoneblock_voffs : std_logic_vector(31 downto 0) := (others => '0'); + signal writeoneblock_hoffs : std_logic_vector(31 downto 0) := (others => '0'); + signal writeoneblock_i : std_logic_vector(31 downto 0) := (others => '0'); + signal writeoneblock_e : std_logic_vector(31 downto 0) := (others => '0'); + signal writeoneblock_inidx : std_logic_vector(31 downto 0) := (others => '0'); + signal writeoneblock_diff : std_logic_vector(12 downto 0) := (others => '0'); + signal writeblock_i : std_logic_vector(1 downto 0) := (others => '0'); + signal write4blocks_i : std_logic_vector(1 downto 0) := (others => '0'); + signal write4blocks_voffs : std_logic_vector(31 downto 0) := (others => '0'); + signal write4blocks_hoffs : std_logic_vector(31 downto 0) := (others => '0'); + signal yuvtorgb_p : std_logic_vector(1 downto 0) := (others => '0'); + signal yuvtorgb_yidx : std_logic_vector(2 downto 0) := (others => '0'); + signal yuvtorgb_uidx : std_logic_vector(2 downto 0) := (others => '0'); + signal yuvtorgb_vidx : std_logic_vector(2 downto 0) := (others => '0'); + signal yuvtorgb_r : std_logic_vector(31 downto 0) := (others => '0'); + signal yuvtorgb_g : std_logic_vector(31 downto 0) := (others => '0'); + signal yuvtorgb_b : std_logic_vector(31 downto 0) := (others => '0'); + signal yuvtorgb_y : std_logic_vector(23 downto 0) := (others => '0'); + signal yuvtorgb_u : std_logic_vector(30 downto 0) := (others => '0'); + signal yuvtorgb_v : std_logic_vector(31 downto 0) := (others => '0'); + signal yuvtorgb_i : std_logic_vector(31 downto 0) := (others => '0'); + signal decode_block_comp_no : std_logic_vector(1 downto 0) := (others => '0'); + signal decode_block_out_buf_idx : std_logic_vector(2 downto 0) := (others => '0'); + signal decode_block_in_buf_idx : std_logic_vector(1 downto 0) := (others => '0'); + signal decode_start_i : std_logic_vector(31 downto 0) := (others => '0'); + signal decode_start_currentmcu : std_logic_vector(31 downto 0) := (others => '0'); + signal nand_786 : std_logic; + signal or_845 : std_logic_vector(31 downto 0); + signal or_854 : std_logic_vector(31 downto 0); + signal or_866 : std_logic_vector(31 downto 0); + signal jpeg2bmp_main_i : std_logic_vector(31 downto 0) := (others => '0'); + signal jpeg2bmp_main_j : std_logic_vector(31 downto 0) := (others => '0'); + signal read8_ret0_195 : std_logic_vector(7 downto 0) := (others => '0'); + signal and_785 : std_logic; + signal and_801 : std_logic_vector(31 downto 0); + signal mux_761 : std_logic_vector(8 downto 0); + signal mux_782 : std_logic_vector(31 downto 0); + signal or_802 : std_logic_vector(23 downto 0); + signal and_803 : std_logic_vector(31 downto 0); + signal mux_822 : std_logic_vector(31 downto 0); + signal mux_823 : std_logic_vector(31 downto 0); + signal mux_776 : std_logic_vector(31 downto 0); + signal mux_820 : std_logic_vector(31 downto 0); + signal mux_824 : std_logic_vector(31 downto 0); + signal mux_825 : std_logic_vector(31 downto 0); + signal mux_760 : std_logic_vector(31 downto 0); + signal and_789 : std_logic; + signal mux_759 : std_logic_vector(5 downto 0); + signal mux_768 : std_logic_vector(31 downto 0); + signal mux_757 : std_logic_vector(7 downto 0); + signal mux_773 : std_logic_vector(7 downto 0); + signal mux_762 : std_logic_vector(31 downto 0); + signal mux_766 : std_logic_vector(31 downto 0); + signal mux_781 : std_logic_vector(31 downto 0); + signal mux_797 : std_logic_vector(31 downto 0); + signal mux_821 : std_logic_vector(31 downto 0); + signal mux_826 : std_logic_vector(31 downto 0); + signal mux_778 : std_logic_vector(31 downto 0); + signal mux_827 : std_logic_vector(31 downto 0); + signal mux_815 : std_logic_vector(31 downto 0); + signal mux_798 : std_logic_vector(31 downto 0); + signal mux_816 : std_logic_vector(31 downto 0); + signal mux_817 : std_logic_vector(31 downto 0); + signal mux_777 : std_logic_vector(31 downto 0); + signal mux_819 : std_logic_vector(31 downto 0); + signal mux_783 : std_logic_vector(31 downto 0); + signal mux_795 : std_logic_vector(31 downto 0); + signal mux_796 : std_logic_vector(31 downto 0); + signal mux_805 : std_logic_vector(31 downto 0); + signal mux_806 : std_logic_vector(31 downto 0); + signal mux_807 : std_logic_vector(31 downto 0); + signal mux_808 : std_logic_vector(31 downto 0); + signal mux_809 : std_logic_vector(31 downto 0); + signal mux_810 : std_logic_vector(31 downto 0); + signal mux_811 : std_logic_vector(31 downto 0); + signal mux_812 : std_logic_vector(31 downto 0); + signal mux_813 : std_logic_vector(31 downto 0); + signal mux_814 : std_logic_vector(31 downto 0); + signal mux_818 : std_logic_vector(31 downto 0); + signal mux_828 : std_logic_vector(31 downto 0); + signal mux_829 : std_logic_vector(31 downto 0); + signal mux_830 : std_logic_vector(31 downto 0); + signal mux_831 : std_logic_vector(31 downto 0); + signal mux_832 : std_logic_vector(31 downto 0); + signal mux_836 : std_logic_vector(31 downto 0); + signal mux_837 : std_logic_vector(31 downto 0); + signal mux_839 : std_logic_vector(31 downto 0); + signal mux_840 : std_logic_vector(31 downto 0); + signal mux_841 : std_logic_vector(31 downto 0); + signal mux_842 : std_logic_vector(31 downto 0); + signal mux_843 : std_logic_vector(31 downto 0); + signal mux_856 : std_logic_vector(31 downto 0); + signal and_864 : std_logic; + signal mux_870 : std_logic_vector(31 downto 0); + signal mux_872 : std_logic_vector(1 downto 0); + signal mux_875 : std_logic_vector(31 downto 0); + signal mux_891 : std_logic_vector(31 downto 0); + signal mux_892 : std_logic_vector(31 downto 0); + signal mux_893 : std_logic_vector(31 downto 0); + signal mux_894 : std_logic_vector(31 downto 0); + signal mux_895 : std_logic_vector(31 downto 0); + signal mux_896 : std_logic_vector(31 downto 0); + signal mux_897 : std_logic_vector(31 downto 0); + signal mux_898 : std_logic_vector(31 downto 0); + signal mux_899 : std_logic_vector(31 downto 0); + signal mux_900 : std_logic_vector(31 downto 0); + signal mux_901 : std_logic_vector(31 downto 0); + signal mux_902 : std_logic_vector(31 downto 0); + signal mux_903 : std_logic_vector(31 downto 0); + signal mux_904 : std_logic_vector(31 downto 0); + signal mux_905 : std_logic_vector(31 downto 0); + signal mux_906 : std_logic_vector(31 downto 0); + signal mux_907 : std_logic_vector(31 downto 0); + signal mux_908 : std_logic_vector(31 downto 0); + signal mux_917 : std_logic_vector(31 downto 0); + signal mux_918 : std_logic_vector(31 downto 0); + signal mux_924 : std_logic_vector(31 downto 0); + signal mux_925 : std_logic_vector(31 downto 0); + signal mux_928 : std_logic_vector(31 downto 0); + signal mux_929 : std_logic_vector(31 downto 0); + signal mux_931 : std_logic_vector(31 downto 0); + signal mux_932 : std_logic_vector(31 downto 0); + signal mux_934 : std_logic_vector(31 downto 0); + signal mux_935 : std_logic_vector(31 downto 0); + signal mux_936 : std_logic_vector(31 downto 0); + signal mux_937 : std_logic_vector(31 downto 0); + signal mux_938 : std_logic_vector(31 downto 0); + signal mux_939 : std_logic_vector(31 downto 0); + signal mux_941 : std_logic_vector(31 downto 0); + signal mux_944 : std_logic_vector(31 downto 0); + signal mux_945 : std_logic_vector(31 downto 0); + signal mux_946 : std_logic_vector(31 downto 0); + signal mux_833 : std_logic_vector(31 downto 0); + signal mux_834 : std_logic_vector(31 downto 0); + signal mux_835 : std_logic_vector(31 downto 0); + signal mux_838 : std_logic_vector(31 downto 0); + signal mux_844 : std_logic_vector(31 downto 0); + signal mux_857 : std_logic_vector(31 downto 0); + signal mux_858 : std_logic_vector(31 downto 0); + signal mux_859 : std_logic_vector(31 downto 0); + signal mux_874 : std_logic_vector(31 downto 0); + signal mux_888 : std_logic_vector(31 downto 0); + signal mux_889 : std_logic_vector(31 downto 0); + signal mux_913 : std_logic_vector(31 downto 0); + signal mux_914 : std_logic_vector(31 downto 0); + signal mux_915 : std_logic_vector(31 downto 0); + signal mux_916 : std_logic_vector(31 downto 0); + signal mux_933 : std_logic_vector(31 downto 0); + signal mux_940 : std_logic_vector(31 downto 0); + signal mux_942 : std_logic_vector(31 downto 0); + signal and_867 : std_logic; + signal mux_909 : std_logic_vector(31 downto 0); + signal mux_910 : std_logic_vector(31 downto 0); + signal mux_911 : std_logic_vector(31 downto 0); + signal mux_920 : std_logic_vector(31 downto 0); + signal mux_921 : std_logic_vector(31 downto 0); + signal mux_926 : std_logic_vector(31 downto 0); + signal mux_927 : std_logic_vector(31 downto 0); + signal mux_943 : std_logic_vector(31 downto 0); + signal mux_886 : std_logic; + signal mux_922 : std_logic_vector(31 downto 0); + signal mux_923 : std_logic_vector(31 downto 0); + signal mux_930 : std_logic_vector(31 downto 0); + signal mux_987 : std_logic_vector(31 downto 0); + signal and_860 : std_logic_vector(31 downto 0); + signal and_881 : std_logic_vector(31 downto 0); + signal and_884 : std_logic_vector(31 downto 0); + signal mux_890 : std_logic_vector(31 downto 0); + signal mux_912 : std_logic_vector(31 downto 0); + signal mux_919 : std_logic_vector(31 downto 0); + signal mux_948 : std_logic_vector(31 downto 0); + signal mux_949 : std_logic_vector(31 downto 0); + signal mux_950 : std_logic_vector(31 downto 0); + signal and_862 : std_logic; + signal mux_953 : std_logic_vector(31 downto 0); + signal mux_954 : std_logic_vector(31 downto 0); + signal mux_955 : std_logic_vector(31 downto 0); + signal mux_951 : std_logic_vector(31 downto 0); + signal mux_952 : std_logic_vector(31 downto 0); + signal mux_959 : std_logic_vector(31 downto 0); + signal mux_960 : std_logic_vector(31 downto 0); + signal mux_961 : std_logic_vector(31 downto 0); + signal mux_965 : std_logic_vector(31 downto 0); + signal mux_966 : std_logic_vector(31 downto 0); + signal and_876 : std_logic_vector(7 downto 0); + signal mux_956 : std_logic_vector(31 downto 0); + signal mux_957 : std_logic_vector(31 downto 0); + signal mux_947 : std_logic_vector(31 downto 0); + signal mux_968 : std_logic_vector(31 downto 0); + signal mux_969 : std_logic_vector(31 downto 0); + signal mux_970 : std_logic_vector(31 downto 0); + signal mux_980 : std_logic_vector(31 downto 0); + signal mux_981 : std_logic_vector(31 downto 0); + signal mux_958 : std_logic_vector(31 downto 0); + signal and_963 : std_logic; + signal mux_986 : std_logic_vector(31 downto 0); + signal mux_988 : std_logic_vector(31 downto 0); + signal mux_989 : std_logic_vector(31 downto 0); + + -- This utility function is used for inlining MUX behaviour + + -- Little utility function to ease concatenation of an std_logic + -- and explicitely return an std_logic_vector + function repeat(N: natural; B: std_logic) return std_logic_vector is + variable result: std_logic_vector(N-1 downto 0); + begin + result := (others => B); + return result; + end; + +begin + + -- Instantiation of components + + cmp_869_i : cmp_869 port map ( + eq => sig_1670, + in1 => sig_1665, + in0 => get_sos_cc + ); + + cmp_978_i : cmp_978 port map ( + ne => augh_test_132, + in1 => sig_1633, + in0 => huff_make_dhuff_tb_dc_size + ); + + cmp_979_i : cmp_979 port map ( + ne => augh_test_124, + in1 => sig_1635, + in0 => huff_make_dhuff_tb_ac_size + ); + + cmp_847_i : cmp_847 port map ( + eq => augh_test_100, + in1 => sig_1716, + in0 => "00000000000000000000000011000000" + ); + + cmp_855_i : cmp_855 port map ( + ne => sig_1669, + in1 => sig_1715, + in0 => "00000000000000000000000000000000" + ); + + cmp_852_i : cmp_852 port map ( + eq => augh_test_94, + in1 => sig_1714, + in0 => "00000000000000000000000000000000" + ); + + mul_213_i : mul_213 port map ( + output => sig_1668, + in_b => "00000000000000000000000000110001", + in_a => chenidct_b3 + ); + + mul_216_i : mul_216 port map ( + output => sig_1667, + in_b => sig_1713, + in_a => mux_762 + ); + + mul_214_i : mul_214 port map ( + output => sig_1666, + in_b => sig_1712, + in_a => mux_760 + ); + + cmp_846_i : cmp_846 port map ( + eq => augh_test_99, + in1 => sig_1711, + in0 => "00000000000000000000000011011000" + ); + + cmp_848_i : cmp_848 port map ( + eq => augh_test_101, + in1 => sig_1710, + in0 => "00000000000000000000000011011010" + ); + + cmp_849_i : cmp_849 port map ( + eq => augh_test_102, + in1 => sig_1709, + in0 => "00000000000000000000000011000100" + ); + + p_jinfo_comps_info_id_i : p_jinfo_comps_info_id port map ( + wa0_data => read_byte, + wa0_addr => get_sof_i_comp_info_id, + clk => sig_clock, + ra0_addr => get_sos_ci(1 downto 0), + ra0_data => sig_1665, + wa0_en => sig_1213 + ); + + p_jinfo_comps_info_h_samp_factor_i : p_jinfo_comps_info_h_samp_factor port map ( + wa0_data => and_876, + wa0_addr => get_sof_i_comp_info_h_samp_factor, + clk => sig_clock, + ra0_addr => "00", + ra0_data => sig_1664, + wa0_en => sig_1214 + ); + + p_jinfo_comps_info_quant_tbl_no_i : p_jinfo_comps_info_quant_tbl_no port map ( + wa0_data => read_byte(1 downto 0), + wa0_addr => get_sof_i_comp_info_quant_tbl_no, + clk => sig_clock, + ra0_addr => decode_block_comp_no, + ra0_data => sig_1663, + wa0_en => sig_1212 + ); + + p_jinfo_comps_info_dc_tbl_no_i : p_jinfo_comps_info_dc_tbl_no port map ( + wa0_data => get_sos_c, + wa0_addr => get_sos_i_comp_info_dc_tbl_no, + clk => sig_clock, + ra0_addr => decode_block_comp_no, + ra0_data => sig_1662, + wa0_en => sig_1252 + ); + + p_jinfo_quant_tbl_quantval_i : p_jinfo_quant_tbl_quantval port map ( + wa0_data => sig_1708, + wa0_addr => sig_1707, + clk => sig_clock, + ra0_addr => mux_731, + ra0_data => sig_1661, + wa0_en => sig_1334 + ); + + p_jinfo_dc_xhuff_tbl_bits_i : p_jinfo_dc_xhuff_tbl_bits port map ( + wa0_data => mux_782, + wa0_addr => sig_1706, + clk => sig_clock, + ra0_addr => mux_727, + ra0_data => sig_1660, + wa0_en => sig_1457 + ); + + p_jinfo_dc_xhuff_tbl_huffval_i : p_jinfo_dc_xhuff_tbl_huffval port map ( + wa0_data => mux_778, + wa0_addr => sig_1705, + clk => sig_clock, + ra0_addr => mux_723, + ra0_data => sig_1659, + wa0_en => sig_1540 + ); + + p_jinfo_ac_xhuff_tbl_bits_i : p_jinfo_ac_xhuff_tbl_bits port map ( + wa0_data => mux_783, + wa0_addr => sig_1704, + clk => sig_clock, + ra0_addr => mux_719, + ra0_data => sig_1658, + wa0_en => sig_1457 + ); + + p_jinfo_ac_xhuff_tbl_huffval_i : p_jinfo_ac_xhuff_tbl_huffval port map ( + wa0_data => mux_781, + wa0_addr => sig_1703, + clk => sig_clock, + ra0_addr => mux_715, + ra0_data => sig_1657, + wa0_en => sig_1540 + ); + + p_jinfo_dc_dhuff_tbl_ml_i : p_jinfo_dc_dhuff_tbl_ml port map ( + wa0_data => huff_make_dhuff_tb_dc, + wa0_addr => sig_1188, + clk => sig_clock, + ra0_addr => mux_711, + ra0_data => sig_1656, + wa0_en => sig_1190 + ); + + p_jinfo_dc_dhuff_tbl_maxcode_i : p_jinfo_dc_dhuff_tbl_maxcode port map ( + wa0_data => mux_705, + wa0_addr => mux_706, + clk => sig_clock, + ra0_addr => mux_707, + ra0_data => sig_1655, + wa0_en => sig_1560 + ); + + p_jinfo_dc_dhuff_tbl_mincode_i : p_jinfo_dc_dhuff_tbl_mincode port map ( + wa0_data => sig_1632(8 downto 0), + wa0_addr => sig_1702, + clk => sig_clock, + ra0_addr => sig_1701, + ra0_data => sig_1654, + wa0_en => sig_1039 + ); + + p_jinfo_dc_dhuff_tbl_valptr_i : p_jinfo_dc_dhuff_tbl_valptr port map ( + wa0_data => huff_make_dhuff_tb_dc_p(8 downto 0), + wa0_addr => sig_1700, + clk => sig_clock, + ra0_addr => sig_1699, + ra0_data => sig_1653, + wa0_en => sig_1039 + ); + + p_jinfo_ac_dhuff_tbl_ml_i : p_jinfo_ac_dhuff_tbl_ml port map ( + wa0_data => huff_make_dhuff_tb_ac, + wa0_addr => sig_1183, + clk => sig_clock, + ra0_addr => mux_695, + ra0_data => sig_1652, + wa0_en => sig_1185 + ); + + p_jinfo_ac_dhuff_tbl_maxcode_i : p_jinfo_ac_dhuff_tbl_maxcode port map ( + wa0_data => mux_689, + wa0_addr => mux_690, + clk => sig_clock, + ra0_addr => mux_691, + ra0_data => sig_1651, + wa0_en => sig_1522 + ); + + p_jinfo_ac_dhuff_tbl_mincode_i : p_jinfo_ac_dhuff_tbl_mincode port map ( + wa0_data => sig_1634(8 downto 0), + wa0_addr => sig_1698, + clk => sig_clock, + ra0_addr => sig_1697, + ra0_data => sig_1650, + wa0_en => sig_1549 + ); + + p_jinfo_ac_dhuff_tbl_valptr_i : p_jinfo_ac_dhuff_tbl_valptr port map ( + wa0_data => huff_make_dhuff_tb_ac_p(8 downto 0), + wa0_addr => sig_1696, + clk => sig_clock, + ra0_addr => sig_1695, + ra0_data => sig_1649, + wa0_en => sig_1549 + ); + + outdata_comp_vpos_i : outdata_comp_vpos port map ( + wa0_data => mux_663, + wa0_addr => mux_664, + clk => sig_clock, + ra0_addr => mux_665, + ra0_data => sig_1648, + wa0_en => sig_1295 + ); + + outdata_comp_hpos_i : outdata_comp_hpos port map ( + wa0_data => mux_659, + wa0_addr => mux_660, + clk => sig_clock, + ra0_addr => mux_661, + ra0_data => sig_1647, + wa0_en => sig_1295 + ); + + outdata_comp_buf_i : outdata_comp_buf port map ( + wa0_data => sig_1631, + wa0_addr => sig_1694, + clk => sig_clock, + ra0_addr => sig_1693, + ra0_data => sig_1646, + wa0_en => sig_1013 + ); + + izigzag_index_i : izigzag_index port map ( + clk => sig_clock, + ra0_addr => get_dqt_i(5 downto 0), + ra0_data => sig_1645 + ); + + jpegfilebuf_i : jpegfilebuf port map ( + wa0_data => read8_ret0_195, + wa0_addr => jpeg2bmp_main_i(12 downto 0), + clk => sig_clock, + ra0_addr => mux_652, + ra0_data => sig_1644, + wa0_en => sig_1041 + ); + + huffbuff_i : huffbuff port map ( + wa0_data => mux_567, + wa0_addr => mux_568, + clk => sig_clock, + ra0_addr => mux_569, + ra0_data => sig_1643, + wa0_en => sig_1428 + ); + + idctbuff_i : idctbuff port map ( + wa0_data => mux_561, + wa0_addr => mux_562, + clk => sig_clock, + ra2_data => sig_1642, + ra2_addr => mux_563, + ra1_data => sig_1641, + ra1_addr => sig_1692, + ra0_addr => mux_565, + ra0_data => sig_1640, + wa0_en => sig_1474 + ); + + quantbuff_i : quantbuff port map ( + wa0_data => mux_557, + wa0_addr => mux_558, + clk => sig_clock, + ra0_addr => mux_559, + ra0_data => sig_1639, + wa0_en => sig_1431 + ); + + extend_mask_i : extend_mask port map ( + clk => sig_clock, + ra0_addr => decodehuffmcu_s(4 downto 0), + ra0_data => sig_1638 + ); + + bit_set_mask_i : bit_set_mask port map ( + clk => sig_clock, + ra0_addr => mux_524, + ra0_data => sig_1637 + ); + + lmask_i : lmask port map ( + clk => sig_clock, + ra0_addr => buf_getv_n(4 downto 0), + ra0_data => sig_1636 + ); + + huff_make_dhuff_tb_ac_huffsize_i : huff_make_dhuff_tb_ac_huffsize port map ( + wa0_data => mux_476, + wa0_addr => huff_make_dhuff_tb_ac_p(8 downto 0), + clk => sig_clock, + ra0_addr => mux_478, + ra0_data => sig_1635, + wa0_en => sig_1501 + ); + + huff_make_dhuff_tb_ac_huffcode_i : huff_make_dhuff_tb_ac_huffcode port map ( + wa0_data => huff_make_dhuff_tb_ac_code, + wa0_addr => huff_make_dhuff_tb_ac_p(8 downto 0), + clk => sig_clock, + ra0_addr => huff_make_dhuff_tb_ac_p(8 downto 0), + ra0_data => sig_1634, + wa0_en => sig_1024 + ); + + huff_make_dhuff_tb_dc_huffsize_i : huff_make_dhuff_tb_dc_huffsize port map ( + wa0_data => mux_443, + wa0_addr => huff_make_dhuff_tb_dc_p(8 downto 0), + clk => sig_clock, + ra0_addr => mux_445, + ra0_data => sig_1633, + wa0_en => sig_1530 + ); + + huff_make_dhuff_tb_dc_huffcode_i : huff_make_dhuff_tb_dc_huffcode port map ( + wa0_data => huff_make_dhuff_tb_dc_code, + wa0_addr => huff_make_dhuff_tb_dc_p(8 downto 0), + clk => sig_clock, + ra0_addr => huff_make_dhuff_tb_dc_p(8 downto 0), + ra0_data => sig_1632, + wa0_en => sig_1036 + ); + + rgb_buf_i : rgb_buf port map ( + wa0_data => mux_378, + wa0_addr => mux_379, + clk => sig_clock, + ra0_addr => sig_1691, + ra0_data => sig_1631, + wa0_en => sig_1236 + ); + + zigzag_index_i : zigzag_index port map ( + clk => sig_clock, + ra0_addr => izigzagmatrix_i(5 downto 0), + ra0_data => sig_1630 + ); + + shr_212_i : shr_212 port map ( + output => sig_1629, + input => mux_322, + shift => mux_323, + padding => '0' + ); + + mul_209_i : mul_209 port map ( + output => sig_1628, + in_b => mux_315, + in_a => mux_316 + ); + + mul_210_i : mul_210 port map ( + output => sig_1627, + in_b => sig_1690, + in_a => mux_314 + ); + + shl_211_i : shl_211 port map ( + output => sig_1626, + input => current_read_byte, + shift => buf_getv_p(5 downto 0), + padding => '0' + ); + + sub_206_i : sub_206 port map ( + gt => sig_1625, + output => sig_1624, + sign => '1', + in_b => mux_306, + in_a => mux_307 + ); + + sub_207_i : sub_207 port map ( + ge => sig_1623, + le => sig_1622, + output => sig_1621, + sign => '1', + in_b => mux_302, + in_a => mux_303 + ); + + sub_208_i : sub_208 port map ( + ge => sig_1620, + output => sig_1619, + sign => '1', + in_b => "00000000000000000000000000000000000000000", + in_a => sig_1689 + ); + + sub_205_i : sub_205 port map ( + gt => sig_1618, + ge => sig_1617, + lt => sig_1616, + le => sig_1615, + output => sig_1614, + sign => '1', + in_b => mux_290, + in_a => mux_291 + ); + + add_202_i : add_202 port map ( + output => sig_1613, + in_b => mux_274, + in_a => mux_275 + ); + + add_203_i : add_203 port map ( + output => sig_1612, + in_b => mux_271, + in_a => mux_272 + ); + + add_204_i : add_204 port map ( + output => sig_1611, + in_b => "0000000000000000000000001", + in_a => sig_1688 + ); + + add_201_i : add_201 port map ( + output => sig_1610, + in_b => mux_265, + in_a => mux_266 + ); + + add_200_i : add_200 port map ( + output => sig_1609, + in_b => mux_260, + in_a => mux_261 + ); + + cmp_775_i : cmp_775 port map ( + eq => augh_test_158, + in1 => sig_1687, + in0 => "00000000000000000000000000001111" + ); + + cmp_779_i : cmp_779 port map ( + eq => sig_1608, + in1 => sig_1686, + in0 => "00000000000000000000000000000000" + ); + + cmp_780_i : cmp_780 port map ( + ne => sig_1607, + in1 => sig_1685, + in0 => "00000000000000000000000000000000" + ); + + cmp_787_i : cmp_787 port map ( + eq => sig_1606, + in1 => '0', + in0 => sig_1610(0) + ); + + cmp_788_i : cmp_788 port map ( + eq => sig_1605, + in1 => "000", + in0 => sig_1642(2 downto 0) + ); + + cmp_790_i : cmp_790 port map ( + ne => sig_1604, + in1 => sig_1624(3 downto 0), + in0 => "0000" + ); + + cmp_792_i : cmp_792 port map ( + eq => augh_test_134, + in1 => sig_1660, + in0 => "00000000000000000000000000000000" + ); + + cmp_793_i : cmp_793 port map ( + eq => augh_test_131, + in1 => sig_1633, + in0 => "00000000000000000000000000000000" + ); + + cmp_794_i : cmp_794 port map ( + eq => augh_test_126, + in1 => sig_1658, + in0 => "00000000000000000000000000000000" + ); + + cmp_791_i : cmp_791 port map ( + ne => augh_test_148, + in1 => decodehuffman_dc, + in0 => "00000000000000000000000000000000" + ); + + cmp_804_i : cmp_804 port map ( + ne => augh_test_113, + in1 => and_803, + in0 => "00000000000000000000000000000000" + ); + + cmp_800_i : cmp_800 port map ( + eq => augh_test_118, + in1 => buf_getv_p, + in0 => "00000000000000000000000000000000" + ); + + cmp_799_i : cmp_799 port map ( + eq => augh_test_123, + in1 => sig_1635, + in0 => "00000000000000000000000000000000" + ); + + cmp_865_i : cmp_865 port map ( + ne => sig_1603, + in1 => sig_1624(2 downto 0), + in0 => "000" + ); + + cmp_882_i : cmp_882 port map ( + eq => augh_test_157, + in1 => and_881, + in0 => "00000000000000000000000000000000" + ); + + cmp_885_i : cmp_885 port map ( + ne => sig_1602, + in1 => and_884, + in0 => "00000000000000000000000000000000" + ); + + cmp_887_i : cmp_887 port map ( + eq => sig_1601, + in1 => and_884, + in0 => "00000000000000000000000000000000" + ); + + mul_215_i : mul_215 port map ( + output => sig_1600, + in_b => "00000000000000000000000111011001", + in_a => chenidct_b2 + ); + + cmp_850_i : cmp_850 port map ( + eq => augh_test_103, + in1 => sig_1684, + in0 => "00000000000000000000000011011011" + ); + + cmp_851_i : cmp_851 port map ( + eq => augh_test_104, + in1 => sig_1683, + in0 => "00000000000000000000000011011001" + ); + + cmp_861_i : cmp_861 port map ( + eq => augh_test_150, + in1 => and_860, + in0 => "00000000000000000000000000000000" + ); + + cmp_871_i : cmp_871 port map ( + eq => sig_1599, + in1 => sig_1682, + in0 => "00000000000000000000000000000000" + ); + + cmp_873_i : cmp_873 port map ( + eq => sig_1598, + in1 => sig_1664, + in0 => "00000010" + ); + + cmp_879_i : cmp_879 port map ( + ne => augh_test_6, + in1 => sig_1681, + in0 => "00000000000000000000000011111111" + ); + + cmp_880_i : cmp_880 port map ( + eq => augh_test_9, + in1 => sig_1680, + in0 => "00000000000000000000000011111111" + ); + + sub_217_i : sub_217 port map ( + ge => sig_1597, + output => sig_1596, + sign => '1', + in_b => "00000000000000000000000000000000000000000", + in_a => sig_1679 + ); + + cmp_863_i : cmp_863 port map ( + ne => sig_1595, + in1 => sig_1614(2 downto 0), + in0 => "000" + ); + + cmp_868_i : cmp_868 port map ( + eq => sig_1594, + in1 => "000000000000000000000000", + in0 => "000000000000000000000000" + ); + + cmp_877_i : cmp_877 port map ( + ne => augh_test_109, + in1 => sig_1678, + in0 => "00000000000000000000000000000000" + ); + + cmp_878_i : cmp_878 port map ( + ne => augh_test_10, + in1 => sig_1677, + in0 => "00000000000000000000000000000000" + ); + + sub_218_i : sub_218 port map ( + le => sig_1593, + output => sig_1592, + sign => '1', + in_b => "00000000000000000000000000000000011111111", + in_a => sig_1676 + ); + + sub_220_i : sub_220 port map ( + gt => sig_1591, + output => sig_1590, + sign => '1', + in_b => "00000000000000000000000000000000011111111", + in_a => sig_1675 + ); + + sub_221_i : sub_221 port map ( + gt => sig_1589, + output => sig_1588, + sign => '1', + in_b => "00000000000000000000000000000000011111111", + in_a => sig_1674 + ); + + mul_222_i : mul_222 port map ( + output => sig_1587, + in_b => "00000000000000000000000010110101", + in_a => mux_233 + ); + + sub_219_i : sub_219 port map ( + le => sig_1586, + output => sig_1585, + sign => '1', + in_b => "00000000000000000000000000000000011111111", + in_a => sig_1673 + ); + + cmp_962_i : cmp_962 port map ( + ne => augh_test_62, + in1 => get_sos_j, + in0 => "11111111111111111111111111111111" + ); + + cmp_975_i : cmp_975 port map ( + ne => augh_test_154, + in1 => decodehuffmcu_s, + in0 => "00000000000000000000000000000000" + ); + + fsm_224_i : fsm_224 port map ( + clock => sig_clock, + reset => sig_reset, + out40 => sig_1584, + in2 => augh_test_152, + in11 => augh_test_131, + out146 => sig_1583, + out148 => sig_1582, + out150 => sig_1581, + out152 => sig_1580, + in12 => augh_test_128, + out153 => sig_1579, + out154 => sig_1578, + in13 => augh_test_127, + out156 => sig_1577, + out157 => sig_1576, + out160 => sig_1575, + out162 => sig_1574, + out165 => sig_1573, + out170 => sig_1572, + out171 => sig_1571, + out173 => sig_1570, + out175 => sig_1569, + out177 => sig_1568, + out180 => sig_1567, + out184 => sig_1566, + in14 => augh_test_126, + out186 => sig_1565, + out189 => sig_1564, + out191 => sig_1563, + out192 => sig_1562, + out193 => sig_1561, + out197 => sig_1560, + out199 => sig_1559, + out201 => sig_1558, + out202 => sig_1557, + out205 => sig_1556, + out207 => sig_1555, + out208 => sig_1554, + out209 => sig_1553, + out210 => sig_1552, + out212 => sig_1551, + out213 => sig_1550, + in15 => augh_test_125, + out221 => sig_1549, + out222 => sig_1548, + out224 => sig_1547, + out225 => sig_1546, + out228 => sig_1545, + out229 => sig_1544, + out230 => sig_1543, + out231 => sig_1542, + out99 => sig_1541, + in6 => augh_test_142, + out92 => sig_1540, + out232 => sig_1539, + in16 => augh_test_123, + out234 => sig_1538, + out236 => sig_1537, + out239 => sig_1536, + out240 => sig_1535, + out241 => sig_1534, + out245 => sig_1533, + out246 => sig_1532, + out247 => sig_1531, + out251 => sig_1530, + out252 => sig_1529, + out253 => sig_1528, + out255 => sig_1527, + out256 => sig_1526, + out258 => sig_1525, + out259 => sig_1524, + in17 => augh_test_120, + out263 => sig_1523, + out264 => sig_1522, + out266 => sig_1521, + in18 => augh_test_119, + out267 => sig_1520, + out268 => sig_1519, + out270 => sig_1518, + out273 => sig_1517, + out275 => sig_1516, + out276 => sig_1515, + in19 => augh_test_118, + out279 => sig_1514, + in20 => augh_test_115, + out281 => sig_1513, + out282 => sig_1512, + in21 => augh_test_114, + out283 => sig_1511, + out286 => sig_1510, + out289 => sig_1509, + out296 => sig_1508, + out297 => sig_1507, + out299 => sig_1506, + out300 => sig_1505, + out304 => sig_1504, + out305 => sig_1503, + in22 => augh_test_113, + out306 => sig_1502, + out310 => sig_1501, + out311 => sig_1500, + out313 => sig_1499, + out314 => sig_1498, + in23 => augh_test_111, + out316 => sig_1497, + out317 => sig_1496, + out320 => sig_1495, + out322 => sig_1494, + out324 => sig_1493, + out325 => sig_1492, + out326 => sig_1491, + out328 => sig_1490, + out332 => sig_1489, + out333 => sig_1488, + out334 => sig_1487, + out335 => sig_1486, + out338 => sig_1485, + out339 => sig_1484, + out341 => sig_1483, + out342 => sig_1482, + out344 => sig_1481, + out93 => sig_1480, + out98 => sig_1479, + out85 => sig_1478, + out87 => sig_1477, + out88 => sig_1476, + out80 => sig_1475, + out82 => sig_1474, + out83 => sig_1473, + out84 => sig_1472, + in5 => augh_test_144, + out77 => sig_1471, + out78 => sig_1470, + out71 => sig_1469, + out72 => sig_1468, + in4 => augh_test_148, + out65 => sig_1467, + out67 => sig_1466, + out60 => sig_1465, + out64 => sig_1464, + in3 => augh_test_151, + out59 => sig_1463, + out53 => sig_1462, + out55 => sig_1461, + out49 => sig_1460, + out44 => sig_1459, + out104 => sig_1458, + out107 => sig_1457, + out111 => sig_1456, + out112 => sig_1455, + out114 => sig_1454, + in7 => augh_test_138, + out117 => sig_1453, + out119 => sig_1452, + out122 => sig_1451, + in8 => augh_test_136, + out128 => sig_1450, + in9 => augh_test_134, + out129 => sig_1449, + out130 => sig_1448, + out133 => sig_1447, + out134 => sig_1446, + out136 => sig_1445, + out137 => sig_1444, + in10 => augh_test_133, + out139 => sig_1443, + out143 => sig_1442, + out144 => sig_1441, + out32 => sig_1440, + out35 => sig_1439, + out27 => sig_1438, + out25 => sig_1437, + out26 => sig_1436, + in1 => augh_test_158, + out15 => sig_1435, + out16 => sig_1434, + out11 => sig_1433, + out13 => sig_1432, + out14 => sig_1431, + out7 => sig_1430, + out1 => sig_1429, + out2 => sig_1428, + out3 => sig_1427, + out4 => sig_1426, + in0 => augh_test_159, + in24 => augh_test_107, + out346 => sig_1425, + out347 => sig_1424, + out348 => sig_1423, + out349 => sig_1422, + in25 => augh_test_106, + out350 => sig_1421, + out351 => sig_1420, + out355 => sig_1419, + out356 => sig_1418, + out357 => sig_1417, + out358 => sig_1416, + out360 => sig_1415, + out362 => sig_1414, + out363 => sig_1413, + out364 => sig_1412, + out365 => sig_1411, + out366 => sig_1410, + out370 => sig_1409, + out371 => sig_1408, + out372 => sig_1407, + out373 => sig_1406, + out375 => sig_1405, + in26 => augh_test_105, + out376 => sig_1404, + out378 => sig_1403, + out379 => sig_1402, + out381 => sig_1401, + out382 => sig_1400, + in27 => augh_test_99, + out384 => sig_1399, + in28 => augh_test_100, + out391 => sig_1398, + out395 => sig_1397, + out396 => sig_1396, + out401 => sig_1395, + out402 => sig_1394, + out403 => sig_1393, + out404 => sig_1392, + out405 => sig_1391, + out407 => sig_1390, + out408 => sig_1389, + out409 => sig_1388, + out410 => sig_1387, + in29 => augh_test_101, + out412 => sig_1386, + out414 => sig_1385, + out415 => sig_1384, + out417 => sig_1383, + out418 => sig_1382, + out419 => sig_1381, + out420 => sig_1380, + out422 => sig_1379, + out424 => sig_1378, + out425 => sig_1377, + out426 => sig_1376, + in30 => augh_test_102, + out428 => sig_1375, + out429 => sig_1374, + out432 => sig_1373, + out433 => sig_1372, + out434 => sig_1371, + out437 => sig_1370, + out440 => sig_1369, + out441 => sig_1368, + in31 => augh_test_103, + out443 => sig_1367, + in32 => augh_test_104, + out445 => sig_1366, + out447 => sig_1365, + out448 => sig_1364, + out450 => sig_1363, + in33 => augh_test_94, + out453 => sig_1362, + out455 => sig_1361, + out458 => sig_1360, + in34 => augh_test_90, + out462 => sig_1359, + out464 => sig_1358, + out467 => sig_1357, + out468 => sig_1356, + out472 => sig_1355, + in35 => augh_test_89, + out478 => sig_1354, + out479 => sig_1353, + out480 => sig_1352, + out487 => sig_1351, + out488 => sig_1350, + in36 => augh_test_83, + out491 => sig_1349, + out496 => sig_1348, + out497 => sig_1347, + out498 => sig_1346, + out500 => sig_1345, + out504 => sig_1344, + out505 => sig_1343, + in37 => augh_test_150, + out506 => sig_1342, + out508 => sig_1341, + in38 => augh_test_77, + out510 => sig_1340, + out513 => sig_1339, + out514 => sig_1338, + out515 => sig_1337, + out517 => sig_1336, + out519 => sig_1335, + in39 => augh_test_72, + out523 => sig_1334, + out526 => sig_1333, + out527 => sig_1332, + out528 => sig_1331, + out530 => sig_1330, + out531 => sig_1329, + out533 => sig_1328, + out534 => sig_1327, + out537 => sig_1326, + out538 => sig_1325, + out549 => sig_1324, + out558 => sig_1323, + out559 => sig_1322, + out561 => sig_1321, + in40 => augh_test_67, + out566 => sig_1320, + out567 => sig_1319, + out568 => sig_1318, + out569 => sig_1317, + out570 => sig_1316, + out572 => sig_1315, + out574 => sig_1314, + out575 => sig_1313, + out577 => sig_1312, + in41 => augh_test_52, + out578 => sig_1311, + out581 => sig_1310, + out589 => sig_1309, + out590 => sig_1308, + out595 => sig_1307, + out597 => sig_1306, + out599 => sig_1305, + out601 => sig_1304, + out602 => sig_1303, + out607 => sig_1302, + out610 => sig_1301, + out612 => sig_1300, + in42 => augh_test_53, + out614 => sig_1299, + out621 => sig_1298, + out628 => sig_1297, + out635 => sig_1296, + out636 => sig_1295, + out638 => sig_1294, + out640 => sig_1293, + out643 => sig_1292, + out646 => sig_1291, + out649 => sig_1290, + out651 => sig_1289, + out656 => sig_1288, + in43 => augh_test_49, + out658 => sig_1287, + out659 => sig_1286, + out661 => sig_1285, + out663 => sig_1284, + out664 => sig_1283, + in44 => augh_test_109, + out667 => sig_1282, + out668 => sig_1281, + out670 => sig_1280, + out672 => sig_1279, + out674 => sig_1278, + in45 => augh_test_26, + out679 => sig_1277, + out681 => sig_1276, + out683 => sig_1275, + out686 => sig_1274, + out688 => sig_1273, + out690 => sig_1272, + out692 => sig_1271, + out694 => sig_1270, + out696 => sig_1269, + out697 => sig_1268, + out698 => sig_1267, + out699 => sig_1266, + out700 => sig_1265, + out703 => sig_1264, + out704 => sig_1263, + out706 => sig_1262, + out708 => sig_1261, + out710 => sig_1260, + out712 => sig_1259, + out715 => sig_1258, + out718 => sig_1257, + in46 => augh_test_10, + out722 => sig_1256, + out724 => sig_1255, + out726 => sig_1254, + out728 => sig_1253, + out731 => sig_1252, + out733 => sig_1251, + out734 => sig_1250, + out737 => sig_1249, + out739 => sig_1248, + out740 => sig_1247, + out743 => sig_1246, + out745 => sig_1245, + out746 => sig_1244, + in47 => augh_test_6, + out749 => sig_1243, + out753 => sig_1242, + out755 => sig_1241, + out759 => sig_1240, + in48 => augh_test_9, + out762 => sig_1239, + out764 => sig_1238, + out765 => sig_1237, + out767 => sig_1236, + out768 => sig_1235, + in49 => augh_test_157, + out772 => sig_1234, + in50 => stdout_ack, + out775 => sig_1233, + out776 => sig_1232, + out778 => sig_1231, + out783 => sig_1230, + out784 => sig_1229, + out787 => sig_1228, + out791 => sig_1227, + in51 => stdin_ack, + out794 => sig_1226, + out795 => sig_1225, + in52 => augh_test_62, + out799 => sig_1224, + out802 => sig_1223, + out806 => sig_1222, + out809 => sig_1221, + out812 => sig_1220, + out815 => sig_1219, + out826 => sig_1218, + out828 => sig_1217, + in53 => augh_test_122, + in54 => augh_test_197, + out843 => sig_1216, + out848 => sig_1215, + out852 => sig_1214, + in55 => augh_test_196, + out855 => sig_1213, + out858 => sig_1212, + in56 => augh_test_189, + out860 => sig_1211, + out861 => sig_1210, + out863 => sig_1209, + out866 => sig_1208, + out872 => sig_1207, + in57 => augh_test_188, + out874 => sig_1206, + out876 => sig_1205, + out879 => sig_1204, + out882 => sig_1203, + out886 => sig_1202, + out887 => sig_1201, + in58 => augh_test_187, + out888 => sig_1200, + out892 => sig_1199, + out894 => sig_1198, + out895 => sig_1197, + out896 => sig_1196, + out901 => sig_1195, + out902 => sig_1194, + out903 => sig_1193, + out905 => sig_1192, + out907 => sig_1191, + out918 => sig_1190, + out920 => sig_1189, + out921 => sig_1188, + out923 => sig_1187, + out925 => sig_1186, + out928 => sig_1185, + out929 => sig_1184, + out931 => sig_1183, + out933 => sig_1182, + out936 => stdout_rdy, + out937 => sig_1181, + out938 => sig_1180, + out939 => sig_1179, + out942 => sig_1178, + out943 => sig_1177, + out944 => sig_1176, + out947 => sig_1175, + out948 => sig_1174, + out949 => sig_1173, + out951 => sig_1172, + in59 => augh_test_186, + out952 => sig_1171, + out953 => sig_1170, + out955 => sig_1169, + out956 => sig_1168, + out957 => sig_1167, + out958 => sig_1166, + in60 => augh_test_184, + in61 => augh_test_183, + out962 => sig_1165, + out963 => sig_1164, + out972 => sig_1163, + out973 => sig_1162, + out974 => sig_1161, + in62 => augh_test_182, + out978 => sig_1160, + out979 => sig_1159, + out981 => sig_1158, + out982 => sig_1157, + out985 => sig_1156, + out986 => sig_1155, + out989 => sig_1154, + in63 => augh_test_180, + in64 => augh_test_179, + in65 => augh_test_178, + in66 => augh_test_194, + in67 => augh_test_154, + in68 => augh_test_130, + in69 => augh_test_132, + in70 => augh_test_124, + in71 => augh_test_171, + in72 => augh_test_168, + in73 => augh_test_167, + in74 => augh_test_166, + in75 => augh_test_165, + in76 => augh_test_108, + in77 => sig_start, + in78 => augh_test_155, + out990 => sig_1153, + out991 => sig_1152, + out993 => sig_1151, + out994 => sig_1150, + out996 => sig_1149, + out997 => sig_1148, + out998 => sig_1147, + out999 => sig_1146, + out1000 => sig_1145, + out1002 => sig_1144, + out1003 => sig_1143, + out1005 => sig_1142, + out1006 => sig_1141, + out1007 => sig_1140, + out1009 => sig_1139, + out1011 => sig_1138, + out1012 => sig_1137, + out1013 => sig_1136, + out1014 => sig_1135, + out1015 => sig_1134, + out1016 => sig_1133, + out1018 => sig_1132, + out1019 => sig_1131, + out1021 => sig_1130, + out1022 => sig_1129, + out1024 => sig_1128, + out1026 => sig_1127, + out1027 => sig_1126, + out1029 => sig_1125, + out1030 => sig_1124, + out1032 => sig_1123, + out1033 => sig_1122, + out1035 => sig_1121, + out1036 => sig_1120, + out1037 => sig_1119, + out1057 => sig_1118, + out1068 => sig_1117, + out1069 => sig_1116, + out1070 => sig_1115, + out1072 => sig_1114, + out1073 => sig_1113, + out1075 => sig_1112, + out1078 => sig_1111, + out1080 => sig_1110, + out1082 => sig_1109, + out1083 => sig_1108, + out1084 => sig_1107, + out1085 => sig_1106, + out1088 => sig_1105, + out1089 => sig_1104, + out1091 => sig_1103, + out1092 => sig_1102, + out1094 => sig_1101, + out1096 => sig_1100, + out1098 => sig_1099, + out1101 => sig_1098, + out1104 => sig_1097, + out1107 => sig_1096, + out1109 => sig_1095, + out1111 => sig_1094, + out1114 => sig_1093, + out1119 => sig_1092, + out1121 => sig_1091, + out1125 => sig_1090, + out1126 => sig_1089, + out1128 => sig_1088, + out1131 => sig_1087, + out1134 => sig_1086, + out1137 => sig_1085, + out1139 => sig_1084, + out1141 => sig_1083, + out1145 => sig_1082, + out1146 => sig_1081, + out1147 => sig_1080, + out1150 => sig_1079, + out1151 => sig_1078, + out1152 => sig_1077, + out1155 => sig_1076, + out1158 => sig_1075, + out1160 => sig_1074, + out1164 => sig_1073, + out1166 => sig_1072, + out1169 => sig_1071, + out1171 => sig_1070, + out1174 => sig_1069, + out1175 => sig_1068, + out1176 => sig_1067, + out1180 => sig_1066, + out1181 => sig_1065, + out1182 => sig_1064, + out1185 => sig_1063, + out1186 => sig_1062, + out1187 => sig_1061, + out1190 => sig_1060, + out1213 => sig_1059, + out1215 => sig_1058, + out1217 => sig_1057, + out1220 => sig_1056, + out1221 => sig_1055, + out1223 => sig_1054, + out1228 => sig_1053, + out1229 => sig_1052, + out1231 => sig_1051, + out1235 => sig_1050, + out1236 => sig_1049, + out1240 => sig_1048, + out1243 => sig_1047, + out1250 => sig_1046, + out1252 => sig_1045, + out1253 => sig_1044, + out1258 => sig_1043, + out1262 => sig_1042, + out1266 => sig_1041, + out1269 => sig_1040, + out1275 => sig_1039, + out1278 => sig_1038, + out1279 => sig_1037, + out1284 => sig_1036, + out1286 => sig_1035, + out1287 => sig_1034, + out1289 => sig_1033, + out1290 => sig_1032, + out1292 => sig_1031, + out1293 => sig_1030, + out1295 => sig_1029, + out1298 => sig_1028, + out1301 => sig_1027, + out1302 => sig_1026, + out1303 => sig_1025, + out1308 => sig_1024, + out1309 => sig_1023, + out1311 => sig_1022, + out1318 => sig_1021, + out1319 => sig_1020, + out1320 => sig_1019, + out1323 => sig_1018, + out1324 => sig_1017, + out1326 => sig_1016, + out1327 => sig_1015, + out1329 => sig_1014, + out1337 => sig_1013, + out1339 => sig_1012, + out1340 => sig_1011, + out1341 => sig_1010, + out1344 => sig_1009, + out1346 => sig_1008, + out1349 => sig_1007, + out1353 => sig_1006, + out1356 => sig_1005, + out1362 => sig_1004, + out1363 => sig_1003, + out1364 => sig_1002, + out1365 => sig_1001, + out1366 => sig_1000, + out1368 => sig_999, + out1370 => sig_998, + out1375 => sig_997, + out1378 => sig_996, + out1381 => sig_995, + out1383 => sig_994, + out1387 => sig_993 + ); + + muxb_784_i : muxb_784 port map ( + in_sel => sig_1616, + out_data => sig_992, + in_data0 => sig_1609(31 downto 0), + in_data1 => sig_1613 + ); + + cmp_964_i : cmp_964 port map ( + eq => sig_991, + in1 => sig_1635, + in0 => huff_make_dhuff_tb_ac_size + ); + + cmp_972_i : cmp_972 port map ( + ne => augh_test_196, + in1 => jpeg2bmp_main_i, + in0 => "00000000000000000000000000000010" + ); + + cmp_973_i : cmp_973 port map ( + eq => augh_test_180, + in1 => sig_1672, + in0 => "00000000000000000000000000000000" + ); + + cmp_974_i : cmp_974 port map ( + ne => augh_test_194, + in1 => jpeg2bmp_main_i, + in0 => "00000000000000000001010001010110" + ); + + cmp_985_i : cmp_985 port map ( + eq => augh_test_108, + in1 => sig_1671, + in0 => "00000000000000000000000011111111" + ); + + cmp_971_i : cmp_971 port map ( + ne => augh_test_197, + in1 => jpeg2bmp_main_j, + in0 => "00000000000000000001010010111101" + ); + + cmp_977_i : cmp_977 port map ( + eq => sig_990, + in1 => sig_1633, + in0 => huff_make_dhuff_tb_dc_size + ); + + -- Behaviour of component 'mux_967' model 'mux' + mux_967 <= + (repeat(32, sig_1620) and mux_968); + + -- Behaviour of component 'and_976' model 'and' + and_976 <= + sig_1615 and + sig_990; + + -- Behaviour of component 'and_982' model 'and' + and_982 <= + "00000000000000000000000000001111" and + decodehuffman_ac; + + -- Behaviour of component 'and_983' model 'and' + and_983 <= + "0000000000000000000000001111" and + decodehuffman_ac(31 downto 4); + + -- Behaviour of component 'and_984' model 'and' + and_984 <= + sig_1636 and + buf_getv_rv; + + -- Behaviour of component 'mux_689' model 'mux' + mux_689 <= + (repeat(32, sig_1034) and sig_1634) or + (repeat(32, sig_1520) and "11111111111111111111111111111111") or + (repeat(32, sig_1523) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_690' model 'mux' + mux_690 <= + (repeat(7, sig_1519) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0)) or + (repeat(7, sig_1523) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_p_dhtbl_ml(5 downto 0)); + + -- Behaviour of component 'mux_691' model 'mux' + mux_691 <= + (repeat(7, sig_1523) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_p_dhtbl_ml(5 downto 0)) or + (repeat(7, sig_1568) and decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0)) or + (repeat(7, sig_1570) and decodehuffman_ac_tbl_no & decodehuffman_ac_dhuff_ml); + + -- Behaviour of component 'and_853' model 'and' + and_853 <= + sig_1636 and + sig_1629; + + -- Behaviour of component 'mux_233' model 'mux' + mux_233 <= + (repeat(32, sig_1118) and sig_1609(31 downto 0)) or + (repeat(32, sig_1324) and sig_1624(31 downto 0)); + + -- Behaviour of component 'mux_671' model 'mux' + mux_671 <= + (repeat(32, sig_1183) and i_jinfo_jpeg_data) or + (repeat(32, sig_1441) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_665' model 'mux' + mux_665 <= + (repeat(2, sig_1162) and write4blocks_i) or + (repeat(2, sig_1196) and decode_start_i(1 downto 0)) or + (repeat(2, sig_1296) and writeblock_i); + + -- Behaviour of component 'mux_663' model 'mux' + mux_663 <= + (repeat(32, sig_1163) and sig_1609(30 downto 0) & sig_1648(0)) or + (repeat(32, sig_1161) and mux_896) or + (repeat(32, sig_1215) and mux_874) or + (repeat(32, sig_1297) and sig_1609(31 downto 0)); + + -- Behaviour of component 'mux_664' model 'mux' + mux_664 <= + (repeat(2, sig_1043) and decode_start_i(1 downto 0)) or + (repeat(2, sig_1162) and write4blocks_i) or + (repeat(2, sig_1296) and writeblock_i); + + -- Behaviour of component 'mux_659' model 'mux' + mux_659 <= + (repeat(32, sig_1163) and sig_1610(30 downto 0) & sig_1647(0)) or + (repeat(32, sig_1161) and mux_897) or + (repeat(32, sig_1215) and mux_875) or + (repeat(32, sig_1297) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_660' model 'mux' + mux_660 <= + (repeat(2, sig_1043) and decode_start_i(1 downto 0)) or + (repeat(2, sig_1162) and write4blocks_i) or + (repeat(2, sig_1296) and writeblock_i); + + -- Behaviour of component 'mux_661' model 'mux' + mux_661 <= + (repeat(2, sig_1162) and write4blocks_i) or + (repeat(2, sig_1196) and decode_start_i(1 downto 0)) or + (repeat(2, sig_1296) and writeblock_i); + + -- Behaviour of component 'mux_652' model 'mux' + mux_652 <= + (repeat(13, sig_1247) and readbuf_idx(12 downto 0)) or + (repeat(13, sig_1441) and curhuffreadbuf_idx(12 downto 0)); + + -- Behaviour of component 'mux_648' model 'mux' + mux_648 <= + (repeat(32, sig_1247) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_633' model 'mux' + mux_633 <= + (repeat(32, sig_1211) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_622' model 'mux' + mux_622 <= + (repeat(32, sig_1251) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_614' model 'mux' + mux_614 <= + (repeat(32, sig_1269) and "00000000000000000000000000000011") or + (repeat(32, sig_1287) and sig_1614(31 downto 0)); + + -- Behaviour of component 'mux_616' model 'mux' + mux_616 <= + (repeat(32, sig_1254) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_602' model 'mux' + mux_602 <= + (repeat(32, sig_1198) and "00000000000000000000000000000001") or + (repeat(32, sig_1479) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_600' model 'mux' + mux_600 <= + (repeat(32, sig_1458) and sig_1609(31 downto 0)); + + -- Behaviour of component 'mux_593' model 'mux' + mux_593 <= + (repeat(32, sig_1240) and mux_870) or + (repeat(32, sig_1317) and sig_1614(31 downto 0)); + + -- Behaviour of component 'mux_587' model 'mux' + mux_587 <= + (repeat(32, sig_1335) and sig_1609(31 downto 0)); + + -- Behaviour of component 'mux_585' model 'mux' + mux_585 <= + (repeat(16, sig_1337) and read_word) or + (repeat(16, sig_1339) and "00000000" & read_byte); + + -- Behaviour of component 'mux_580' model 'mux' + mux_580 <= + (repeat(8, sig_1346) and read_byte) or + (repeat(8, sig_1348) and next_marker); + + -- Behaviour of component 'mux_569' model 'mux' + mux_569 <= + (repeat(8, sig_1027) and decodehuffmcu_bufdim1 & "000000") or + (repeat(8, sig_1268) and decodehuffmcu_bufdim1 & decodehuffmcu_k(5 downto 0)) or + (repeat(8, sig_1436) and decode_block_in_buf_idx & sig_1630); + + -- Behaviour of component 'mux_567' model 'mux' + mux_567 <= + (repeat(32, sig_1257) and sig_1610(31 downto 0)) or + (repeat(32, sig_1000) and decodehuffmcu_diff) or + (repeat(32, sig_1202) and buf_getv) or + (repeat(32, sig_1267) and or_866); + + -- Behaviour of component 'mux_568' model 'mux' + mux_568 <= + (repeat(8, sig_1266) and decodehuffmcu_bufdim1 & decodehuffmcu_k(5 downto 0)) or + (repeat(8, sig_1000) and decodehuffmcu_bufdim1 & "000000") or + (repeat(8, sig_1443) and decodehuffmcu_bufdim1 & decodehuffmcu_i(5 downto 0)) or + (repeat(8, sig_1429) and decode_start_i(1 downto 0) & "000000"); + + -- Behaviour of component 'mux_563' model 'mux' + mux_563 <= + (repeat(9, sig_1555) and decode_block_out_buf_idx & "011000") or + (repeat(9, sig_1408) and decode_block_out_buf_idx & "001010") or + (repeat(9, sig_1407) and decode_block_out_buf_idx & "101010") or + (repeat(9, sig_1405) and decode_block_out_buf_idx & "010100") or + (repeat(9, sig_1403) and decode_block_out_buf_idx & "110101") or + (repeat(9, sig_1401) and decode_block_out_buf_idx & "111000") or + (repeat(9, sig_1510) and decode_block_out_buf_idx & "101000") or + (repeat(9, sig_1389) and decode_block_out_buf_idx & "011001") or + (repeat(9, sig_1388) and decode_block_out_buf_idx & "100110") or + (repeat(9, sig_1384) and decode_block_out_buf_idx & "111010") or + (repeat(9, sig_1382) and decode_block_out_buf_idx & "111011") or + (repeat(9, sig_1381) and decode_block_out_buf_idx & "111100") or + (repeat(9, sig_1377) and decode_block_out_buf_idx & "000100") or + (repeat(9, sig_1375) and decode_block_out_buf_idx & "100100") or + (repeat(9, sig_1372) and decode_block_out_buf_idx & "010010") or + (repeat(9, sig_1512) and decode_block_out_buf_idx & "000001") or + (repeat(9, sig_1515) and decode_block_out_buf_idx & "011110") or + (repeat(9, sig_1517) and decode_block_out_buf_idx & "011100") or + (repeat(9, sig_1418) and decode_block_out_buf_idx & "111101") or + (repeat(9, sig_1417) and decode_block_out_buf_idx & "100010") or + (repeat(9, sig_1415) and decode_block_out_buf_idx & "010111") or + (repeat(9, sig_1414) and decode_block_out_buf_idx & chenidct_aidx(5 downto 0)) or + (repeat(9, sig_1451) and decode_block_out_buf_idx & chenidct_i(5 downto 0)) or + (repeat(9, sig_1469) and decode_block_out_buf_idx & "010000") or + (repeat(9, sig_1370) and decode_block_out_buf_idx & "000111") or + (repeat(9, sig_1368) and decode_block_out_buf_idx & "001100") or + (repeat(9, sig_1366) and decode_block_out_buf_idx & "111111") or + (repeat(9, sig_1365) and decode_block_out_buf_idx & "101100") or + (repeat(9, sig_1362) and decode_block_out_buf_idx & "110010") or + (repeat(9, sig_1331) and decode_block_out_buf_idx & "000101") or + (repeat(9, sig_1330) and decode_block_out_buf_idx & "010001") or + (repeat(9, sig_1328) and decode_block_out_buf_idx & "001111") or + (repeat(9, sig_1326) and decode_block_out_buf_idx & "100111") or + (repeat(9, sig_1299) and yuvtorgb_yidx & yuvtorgb_i(5 downto 0)) or + (repeat(9, sig_1281) and decode_block_out_buf_idx & "011101") or + (repeat(9, sig_1279) and decode_block_out_buf_idx & "101110") or + (repeat(9, sig_1278) and decode_block_out_buf_idx & "110110") or + (repeat(9, sig_1265) and decode_block_out_buf_idx & "001110") or + (repeat(9, sig_1261) and decode_block_out_buf_idx & "001001") or + (repeat(9, sig_1238) and decode_block_out_buf_idx & "010110") or + (repeat(9, sig_1232) and decode_block_out_buf_idx & "001011") or + (repeat(9, sig_1177) and decode_block_out_buf_idx & "111110") or + (repeat(9, sig_1174) and decode_block_out_buf_idx & "100001") or + (repeat(9, sig_1171) and decode_block_out_buf_idx & "011111") or + (repeat(9, sig_1159) and decode_block_out_buf_idx & "000000") or + (repeat(9, sig_1157) and decode_block_out_buf_idx & "100000") or + (repeat(9, sig_1153) and decode_block_out_buf_idx & "000010") or + (repeat(9, sig_1151) and decode_block_out_buf_idx & "010101") or + (repeat(9, sig_1146) and decode_block_out_buf_idx & "101001") or + (repeat(9, sig_1144) and decode_block_out_buf_idx & "110111") or + (repeat(9, sig_1141) and decode_block_out_buf_idx & "001000") or + (repeat(9, sig_1137) and decode_block_out_buf_idx & "101011") or + (repeat(9, sig_1134) and decode_block_out_buf_idx & "111001") or + (repeat(9, sig_1132) and decode_block_out_buf_idx & "000110") or + (repeat(9, sig_1130) and decode_block_out_buf_idx & "011010") or + (repeat(9, sig_1126) and decode_block_out_buf_idx & "100101") or + (repeat(9, sig_1124) and decode_block_out_buf_idx & "011011") or + (repeat(9, sig_1122) and decode_block_out_buf_idx & "000011") or + (repeat(9, sig_1120) and decode_block_out_buf_idx & "100011") or + (repeat(9, sig_1116) and decode_block_out_buf_idx & "001101") or + (repeat(9, sig_1114) and decode_block_out_buf_idx & "101101") or + (repeat(9, sig_1108) and decode_block_out_buf_idx & "110011") or + (repeat(9, sig_1107) and decode_block_out_buf_idx & "010011") or + (repeat(9, sig_1104) and decode_block_out_buf_idx & "110100") or + (repeat(9, sig_1102) and decode_block_out_buf_idx & "110000") or + (repeat(9, sig_1096) and decode_block_out_buf_idx & "101111") or + (repeat(9, sig_1095) and decode_block_out_buf_idx & "110001") or + (repeat(9, sig_1088) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "000"); + + -- Behaviour of component 'mux_565' model 'mux' + mux_565 <= + (repeat(9, sig_1088) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "001") or + (repeat(9, sig_1299) and yuvtorgb_vidx & yuvtorgb_i(5 downto 0)); + + -- Behaviour of component 'mux_561' model 'mux' + mux_561 <= + (repeat(32, sig_1556) and sig_1610(24 downto 0) & sig_1642(6 downto 0)) or + (repeat(32, sig_1400) and mux_817) or + (repeat(32, sig_1399) and mux_819) or + (repeat(32, sig_1395) and sig_1609(31 downto 0)) or + (repeat(32, sig_1392) and sig_1614(31 downto 0)) or + (repeat(32, sig_1390) and mux_821) or + (repeat(32, sig_1416) and mux_807) or + (repeat(32, sig_1387) and mux_823) or + (repeat(32, sig_1386) and mux_825) or + (repeat(32, sig_1385) and mux_827) or + (repeat(32, sig_1383) and mux_829) or + (repeat(32, sig_1380) and mux_831) or + (repeat(32, sig_1379) and mux_833) or + (repeat(32, sig_1378) and mux_835) or + (repeat(32, sig_1374) and mux_837) or + (repeat(32, sig_1419) and mux_805) or + (repeat(32, sig_1513) and mux_797) or + (repeat(32, sig_1516) and mux_795) or + (repeat(32, sig_1409) and mux_809) or + (repeat(32, sig_1406) and mux_811) or + (repeat(32, sig_1404) and mux_813) or + (repeat(32, sig_1402) and mux_815) or + (repeat(32, sig_1451) and sig_992) or + (repeat(32, sig_1475) and mux_776) or + (repeat(32, sig_1373) and mux_839) or + (repeat(32, sig_1369) and mux_841) or + (repeat(32, sig_1364) and mux_843) or + (repeat(32, sig_1329) and mux_856) or + (repeat(32, sig_1327) and mux_858) or + (repeat(32, sig_1263) and sig_1610(31 downto 0)) or + (repeat(32, sig_1176) and mux_888) or + (repeat(32, sig_1175) and mux_890) or + (repeat(32, sig_1173) and mux_892) or + (repeat(32, sig_1172) and mux_894) or + (repeat(32, sig_1160) and mux_898) or + (repeat(32, sig_1158) and mux_900) or + (repeat(32, sig_1154) and mux_902) or + (repeat(32, sig_1152) and mux_904) or + (repeat(32, sig_1150) and mux_906) or + (repeat(32, sig_1149) and mux_908) or + (repeat(32, sig_1148) and mux_910) or + (repeat(32, sig_1147) and mux_912) or + (repeat(32, sig_1145) and mux_914) or + (repeat(32, sig_1143) and mux_916) or + (repeat(32, sig_1142) and mux_918) or + (repeat(32, sig_1140) and mux_920) or + (repeat(32, sig_1139) and mux_922) or + (repeat(32, sig_1138) and mux_924) or + (repeat(32, sig_1136) and mux_926) or + (repeat(32, sig_1135) and mux_928) or + (repeat(32, sig_1133) and mux_930) or + (repeat(32, sig_1131) and mux_932) or + (repeat(32, sig_1129) and mux_934) or + (repeat(32, sig_1128) and mux_936) or + (repeat(32, sig_1127) and mux_938) or + (repeat(32, sig_1125) and mux_940) or + (repeat(32, sig_1123) and mux_942) or + (repeat(32, sig_1121) and mux_944) or + (repeat(32, sig_1119) and mux_946) or + (repeat(32, sig_1117) and mux_948) or + (repeat(32, sig_1115) and mux_950) or + (repeat(32, sig_1113) and mux_952) or + (repeat(32, sig_1109) and mux_954) or + (repeat(32, sig_1106) and mux_956) or + (repeat(32, sig_1105) and mux_958) or + (repeat(32, sig_1103) and mux_960) or + (repeat(32, sig_1031) and mux_980) or + (repeat(32, sig_1003) and mux_986) or + (repeat(32, sig_1002) and mux_988); + + -- Behaviour of component 'mux_562' model 'mux' + mux_562 <= + (repeat(9, sig_1555) and decode_block_out_buf_idx & "011000") or + (repeat(9, sig_1407) and decode_block_out_buf_idx & "101010") or + (repeat(9, sig_1405) and decode_block_out_buf_idx & "010100") or + (repeat(9, sig_1403) and decode_block_out_buf_idx & "110101") or + (repeat(9, sig_1401) and decode_block_out_buf_idx & "111000") or + (repeat(9, sig_1391) and decode_block_out_buf_idx & chenidct_aidx(5 downto 0)) or + (repeat(9, sig_1510) and decode_block_out_buf_idx & "101000") or + (repeat(9, sig_1389) and decode_block_out_buf_idx & "011001") or + (repeat(9, sig_1388) and decode_block_out_buf_idx & "100110") or + (repeat(9, sig_1384) and decode_block_out_buf_idx & "111010") or + (repeat(9, sig_1382) and decode_block_out_buf_idx & "111011") or + (repeat(9, sig_1381) and decode_block_out_buf_idx & "111100") or + (repeat(9, sig_1377) and decode_block_out_buf_idx & "000100") or + (repeat(9, sig_1375) and decode_block_out_buf_idx & "100100") or + (repeat(9, sig_1372) and decode_block_out_buf_idx & "010010") or + (repeat(9, sig_1512) and decode_block_out_buf_idx & "000001") or + (repeat(9, sig_1515) and decode_block_out_buf_idx & "011110") or + (repeat(9, sig_1517) and decode_block_out_buf_idx & "011100") or + (repeat(9, sig_1418) and decode_block_out_buf_idx & "111101") or + (repeat(9, sig_1417) and decode_block_out_buf_idx & "100010") or + (repeat(9, sig_1415) and decode_block_out_buf_idx & "010111") or + (repeat(9, sig_1408) and decode_block_out_buf_idx & "001010") or + (repeat(9, sig_1450) and decode_block_out_buf_idx & chenidct_i(5 downto 0)) or + (repeat(9, sig_1469) and decode_block_out_buf_idx & "010000") or + (repeat(9, sig_1370) and decode_block_out_buf_idx & "000111") or + (repeat(9, sig_1368) and decode_block_out_buf_idx & "001100") or + (repeat(9, sig_1366) and decode_block_out_buf_idx & "111111") or + (repeat(9, sig_1365) and decode_block_out_buf_idx & "101100") or + (repeat(9, sig_1362) and decode_block_out_buf_idx & "110010") or + (repeat(9, sig_1331) and decode_block_out_buf_idx & "000101") or + (repeat(9, sig_1330) and decode_block_out_buf_idx & "010001") or + (repeat(9, sig_1328) and decode_block_out_buf_idx & "001111") or + (repeat(9, sig_1326) and decode_block_out_buf_idx & "100111") or + (repeat(9, sig_1281) and decode_block_out_buf_idx & "011101") or + (repeat(9, sig_1279) and decode_block_out_buf_idx & "101110") or + (repeat(9, sig_1278) and decode_block_out_buf_idx & "110110") or + (repeat(9, sig_1265) and decode_block_out_buf_idx & "001110") or + (repeat(9, sig_1261) and decode_block_out_buf_idx & "001001") or + (repeat(9, sig_1238) and decode_block_out_buf_idx & "010110") or + (repeat(9, sig_1232) and decode_block_out_buf_idx & "001011") or + (repeat(9, sig_1177) and decode_block_out_buf_idx & "111110") or + (repeat(9, sig_1174) and decode_block_out_buf_idx & "100001") or + (repeat(9, sig_1171) and decode_block_out_buf_idx & "011111") or + (repeat(9, sig_1159) and decode_block_out_buf_idx & "000000") or + (repeat(9, sig_1157) and decode_block_out_buf_idx & "100000") or + (repeat(9, sig_1153) and decode_block_out_buf_idx & "000010") or + (repeat(9, sig_1151) and decode_block_out_buf_idx & "010101") or + (repeat(9, sig_1146) and decode_block_out_buf_idx & "101001") or + (repeat(9, sig_1144) and decode_block_out_buf_idx & "110111") or + (repeat(9, sig_1141) and decode_block_out_buf_idx & "001000") or + (repeat(9, sig_1137) and decode_block_out_buf_idx & "101011") or + (repeat(9, sig_1134) and decode_block_out_buf_idx & "111001") or + (repeat(9, sig_1132) and decode_block_out_buf_idx & "000110") or + (repeat(9, sig_1130) and decode_block_out_buf_idx & "011010") or + (repeat(9, sig_1126) and decode_block_out_buf_idx & "100101") or + (repeat(9, sig_1124) and decode_block_out_buf_idx & "011011") or + (repeat(9, sig_1122) and decode_block_out_buf_idx & "000011") or + (repeat(9, sig_1120) and decode_block_out_buf_idx & "100011") or + (repeat(9, sig_1116) and decode_block_out_buf_idx & "001101") or + (repeat(9, sig_1114) and decode_block_out_buf_idx & "101101") or + (repeat(9, sig_1108) and decode_block_out_buf_idx & "110011") or + (repeat(9, sig_1107) and decode_block_out_buf_idx & "010011") or + (repeat(9, sig_1104) and decode_block_out_buf_idx & "110100") or + (repeat(9, sig_1102) and decode_block_out_buf_idx & "110000") or + (repeat(9, sig_1096) and decode_block_out_buf_idx & "101111") or + (repeat(9, sig_1095) and decode_block_out_buf_idx & "110001") or + (repeat(9, sig_1087) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "000") or + (repeat(9, sig_1083) and decode_block_out_buf_idx & chenidct_i(2 downto 0) & "001"); + + -- Behaviour of component 'mux_557' model 'mux' + mux_557 <= + (repeat(32, sig_1436) and sig_1643) or + (repeat(32, sig_1433) and sig_1628(31 downto 0)); + + -- Behaviour of component 'mux_558' model 'mux' + mux_558 <= + (repeat(6, sig_1564) and "000101") or + (repeat(6, sig_1321) and "110001") or + (repeat(6, sig_1320) and "000110") or + (repeat(6, sig_1315) and "010101") or + (repeat(6, sig_1311) and "011111") or + (repeat(6, sig_1301) and "100101") or + (repeat(6, sig_1367) and "111010") or + (repeat(6, sig_1293) and "100111") or + (repeat(6, sig_1277) and "000010") or + (repeat(6, sig_1276) and "111001") or + (repeat(6, sig_1275) and "010001") or + (repeat(6, sig_1270) and "110000") or + (repeat(6, sig_1260) and "101001") or + (repeat(6, sig_1259) and "111100") or + (repeat(6, sig_1258) and "011000") or + (repeat(6, sig_1371) and "110111") or + (repeat(6, sig_1410) and "011001") or + (repeat(6, sig_1508) and "001101") or + (repeat(6, sig_1361) and "101100") or + (repeat(6, sig_1359) and "001000") or + (repeat(6, sig_1358) and "101011") or + (repeat(6, sig_1436) and izigzagmatrix_out_idx(5 downto 0)) or + (repeat(6, sig_1432) and "010010") or + (repeat(6, sig_1256) and "010110") or + (repeat(6, sig_1255) and "000011") or + (repeat(6, sig_1246) and "100011") or + (repeat(6, sig_1239) and "100001") or + (repeat(6, sig_1235) and "100100") or + (repeat(6, sig_1231) and "100110") or + (repeat(6, sig_1230) and "100000") or + (repeat(6, sig_1228) and "110101") or + (repeat(6, sig_1227) and "101101") or + (repeat(6, sig_1226) and "011110") or + (repeat(6, sig_1225) and "000100") or + (repeat(6, sig_1223) and "000111") or + (repeat(6, sig_1222) and "110110") or + (repeat(6, sig_1221) and "011101") or + (repeat(6, sig_1220) and "101110") or + (repeat(6, sig_1166) and "001110") or + (repeat(6, sig_1164) and "110100") or + (repeat(6, sig_1156) and "010100") or + (repeat(6, sig_1155) and "101010") or + (repeat(6, sig_1099) and "011010") or + (repeat(6, sig_1098) and "101111") or + (repeat(6, sig_1097) and "010011") or + (repeat(6, sig_1094) and "010111") or + (repeat(6, sig_1093) and "111000") or + (repeat(6, sig_1092) and "011100") or + (repeat(6, sig_1091) and "000001") or + (repeat(6, sig_1090) and "001001") or + (repeat(6, sig_1086) and "001011") or + (repeat(6, sig_1085) and "110010") or + (repeat(6, sig_1084) and "010000") or + (repeat(6, sig_1079) and "001111") or + (repeat(6, sig_1076) and "001010") or + (repeat(6, sig_1075) and "110011") or + (repeat(6, sig_1074) and "111111") or + (repeat(6, sig_1071) and "011011") or + (repeat(6, sig_1063) and "001100") or + (repeat(6, sig_1054) and "101000") or + (repeat(6, sig_1050) and "100010") or + (repeat(6, sig_1028) and "111101") or + (repeat(6, sig_1022) and "111110") or + (repeat(6, sig_1007) and "111011"); + + -- Behaviour of component 'mux_559' model 'mux' + mux_559 <= + (repeat(6, sig_1581) and chenidct_i(5 downto 0)) or + (repeat(6, sig_1358) and "101011") or + (repeat(6, sig_1321) and "110001") or + (repeat(6, sig_1320) and "000110") or + (repeat(6, sig_1315) and "010101") or + (repeat(6, sig_1311) and "011111") or + (repeat(6, sig_1371) and "110111") or + (repeat(6, sig_1301) and "100101") or + (repeat(6, sig_1293) and "100111") or + (repeat(6, sig_1277) and "000010") or + (repeat(6, sig_1276) and "111001") or + (repeat(6, sig_1275) and "010001") or + (repeat(6, sig_1270) and "110000") or + (repeat(6, sig_1260) and "101001") or + (repeat(6, sig_1259) and "111100") or + (repeat(6, sig_1410) and "011001") or + (repeat(6, sig_1508) and "001101") or + (repeat(6, sig_1564) and "000101") or + (repeat(6, sig_1367) and "111010") or + (repeat(6, sig_1361) and "101100") or + (repeat(6, sig_1359) and "001000") or + (repeat(6, sig_1473) and chenidct_aidx(5 downto 0)) or + (repeat(6, sig_1432) and "010010") or + (repeat(6, sig_1258) and "011000") or + (repeat(6, sig_1256) and "010110") or + (repeat(6, sig_1255) and "000011") or + (repeat(6, sig_1246) and "100011") or + (repeat(6, sig_1239) and "100001") or + (repeat(6, sig_1235) and "100100") or + (repeat(6, sig_1231) and "100110") or + (repeat(6, sig_1230) and "100000") or + (repeat(6, sig_1228) and "110101") or + (repeat(6, sig_1227) and "101101") or + (repeat(6, sig_1226) and "011110") or + (repeat(6, sig_1225) and "000100") or + (repeat(6, sig_1223) and "000111") or + (repeat(6, sig_1222) and "110110") or + (repeat(6, sig_1221) and "011101") or + (repeat(6, sig_1220) and "101110") or + (repeat(6, sig_1166) and "001110") or + (repeat(6, sig_1164) and "110100") or + (repeat(6, sig_1156) and "010100") or + (repeat(6, sig_1155) and "101010") or + (repeat(6, sig_1099) and "011010") or + (repeat(6, sig_1098) and "101111") or + (repeat(6, sig_1097) and "010011") or + (repeat(6, sig_1094) and "010111") or + (repeat(6, sig_1093) and "111000") or + (repeat(6, sig_1092) and "011100") or + (repeat(6, sig_1091) and "000001") or + (repeat(6, sig_1090) and "001001") or + (repeat(6, sig_1086) and "001011") or + (repeat(6, sig_1085) and "110010") or + (repeat(6, sig_1084) and "010000") or + (repeat(6, sig_1079) and "001111") or + (repeat(6, sig_1076) and "001010") or + (repeat(6, sig_1075) and "110011") or + (repeat(6, sig_1074) and "111111") or + (repeat(6, sig_1071) and "011011") or + (repeat(6, sig_1063) and "001100") or + (repeat(6, sig_1054) and "101000") or + (repeat(6, sig_1050) and "100010") or + (repeat(6, sig_1028) and "111101") or + (repeat(6, sig_1022) and "111110") or + (repeat(6, sig_1007) and "111011"); + + -- Behaviour of component 'mux_555' model 'mux' + mux_555 <= + (repeat(32, sig_1396) and sig_1613) or + (repeat(32, sig_1449) and sig_1612(31 downto 0)); + + -- Behaviour of component 'mux_551' model 'mux' + mux_551 <= + (repeat(32, sig_1118) and sig_1587(39 downto 8)) or + (repeat(32, sig_1088) and sig_1640) or + (repeat(32, sig_1332) and sig_1639(29 downto 0) & "00") or + (repeat(32, sig_1463) and sig_1609(31 downto 0)); + + -- Behaviour of component 'mux_553' model 'mux' + mux_553 <= + (repeat(32, sig_1411) and sig_1610(31 downto 0)) or + (repeat(32, sig_1111) and sig_1609(28 downto 0) & chenidct_aidx(2 downto 0)) or + (repeat(32, sig_1262) and sig_1609(31 downto 0)) or + (repeat(32, sig_1582) and sig_1610(28 downto 0) & chenidct_i(2 downto 0)) or + (repeat(32, sig_1477) and sig_1610(28 downto 0) & chenidct_aidx(2 downto 0)); + + -- Behaviour of component 'mux_549' model 'mux' + mux_549 <= + (repeat(32, sig_1323) and sig_1639(29 downto 0) & "00") or + (repeat(32, sig_1274) and sig_1642) or + (repeat(32, sig_1324) and sig_1587(39 downto 8)) or + (repeat(32, sig_1463) and sig_1614(31 downto 0)); + + -- Behaviour of component 'mux_545' model 'mux' + mux_545 <= + (repeat(32, sig_1118) and sig_1612(38 downto 7)) or + (repeat(32, sig_1040) and sig_1639(29 downto 0) & "00") or + (repeat(32, sig_1351) and sig_1642) or + (repeat(32, sig_1463) and sig_1613); + + -- Behaviour of component 'mux_547' model 'mux' + mux_547 <= + (repeat(32, sig_1349) and sig_1614(40 downto 9)) or + (repeat(32, sig_1001) and sig_1639(29 downto 0) & "00") or + (repeat(32, sig_1413) and sig_1642) or + (repeat(32, sig_1463) and sig_1624(31 downto 0)); + + -- Behaviour of component 'mux_543' model 'mux' + mux_543 <= + (repeat(32, sig_1088) and sig_1642) or + (repeat(32, sig_1581) and sig_1639(29 downto 0) & "00") or + (repeat(32, sig_1463) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_731' model 'mux' + mux_731 <= + (repeat(8, sig_1508) and iquantize_qidx & "001101") or + (repeat(8, sig_1320) and iquantize_qidx & "000110") or + (repeat(8, sig_1315) and iquantize_qidx & "010101") or + (repeat(8, sig_1311) and iquantize_qidx & "011111") or + (repeat(8, sig_1301) and iquantize_qidx & "100101") or + (repeat(8, sig_1293) and iquantize_qidx & "100111") or + (repeat(8, sig_1361) and iquantize_qidx & "101100") or + (repeat(8, sig_1277) and iquantize_qidx & "000010") or + (repeat(8, sig_1276) and iquantize_qidx & "111001") or + (repeat(8, sig_1275) and iquantize_qidx & "010001") or + (repeat(8, sig_1270) and iquantize_qidx & "110000") or + (repeat(8, sig_1260) and iquantize_qidx & "101001") or + (repeat(8, sig_1259) and iquantize_qidx & "111100") or + (repeat(8, sig_1258) and iquantize_qidx & "011000") or + (repeat(8, sig_1256) and iquantize_qidx & "010110") or + (repeat(8, sig_1367) and iquantize_qidx & "111010") or + (repeat(8, sig_1371) and iquantize_qidx & "110111") or + (repeat(8, sig_1410) and iquantize_qidx & "011001") or + (repeat(8, sig_1360) and iquantize_qidx & "000000") or + (repeat(8, sig_1359) and iquantize_qidx & "001000") or + (repeat(8, sig_1358) and iquantize_qidx & "101011") or + (repeat(8, sig_1321) and iquantize_qidx & "110001") or + (repeat(8, sig_1564) and iquantize_qidx & "000101") or + (repeat(8, sig_1432) and iquantize_qidx & "010010") or + (repeat(8, sig_1255) and iquantize_qidx & "000011") or + (repeat(8, sig_1246) and iquantize_qidx & "100011") or + (repeat(8, sig_1239) and iquantize_qidx & "100001") or + (repeat(8, sig_1235) and iquantize_qidx & "100100") or + (repeat(8, sig_1231) and iquantize_qidx & "100110") or + (repeat(8, sig_1230) and iquantize_qidx & "100000") or + (repeat(8, sig_1228) and iquantize_qidx & "110101") or + (repeat(8, sig_1227) and iquantize_qidx & "101101") or + (repeat(8, sig_1226) and iquantize_qidx & "011110") or + (repeat(8, sig_1225) and iquantize_qidx & "000100") or + (repeat(8, sig_1223) and iquantize_qidx & "000111") or + (repeat(8, sig_1222) and iquantize_qidx & "110110") or + (repeat(8, sig_1221) and iquantize_qidx & "011101") or + (repeat(8, sig_1220) and iquantize_qidx & "101110") or + (repeat(8, sig_1166) and iquantize_qidx & "001110") or + (repeat(8, sig_1164) and iquantize_qidx & "110100") or + (repeat(8, sig_1156) and iquantize_qidx & "010100") or + (repeat(8, sig_1155) and iquantize_qidx & "101010") or + (repeat(8, sig_1099) and iquantize_qidx & "011010") or + (repeat(8, sig_1098) and iquantize_qidx & "101111") or + (repeat(8, sig_1097) and iquantize_qidx & "010011") or + (repeat(8, sig_1094) and iquantize_qidx & "010111") or + (repeat(8, sig_1093) and iquantize_qidx & "111000") or + (repeat(8, sig_1092) and iquantize_qidx & "011100") or + (repeat(8, sig_1091) and iquantize_qidx & "000001") or + (repeat(8, sig_1090) and iquantize_qidx & "001001") or + (repeat(8, sig_1086) and iquantize_qidx & "001011") or + (repeat(8, sig_1085) and iquantize_qidx & "110010") or + (repeat(8, sig_1084) and iquantize_qidx & "010000") or + (repeat(8, sig_1079) and iquantize_qidx & "001111") or + (repeat(8, sig_1076) and iquantize_qidx & "001010") or + (repeat(8, sig_1075) and iquantize_qidx & "110011") or + (repeat(8, sig_1074) and iquantize_qidx & "111111") or + (repeat(8, sig_1071) and iquantize_qidx & "011011") or + (repeat(8, sig_1063) and iquantize_qidx & "001100") or + (repeat(8, sig_1054) and iquantize_qidx & "101000") or + (repeat(8, sig_1050) and iquantize_qidx & "100010") or + (repeat(8, sig_1028) and iquantize_qidx & "111101") or + (repeat(8, sig_1022) and iquantize_qidx & "111110") or + (repeat(8, sig_1007) and iquantize_qidx & "111011"); + + -- Behaviour of component 'mux_727' model 'mux' + mux_727 <= + (repeat(7, sig_1534) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_i_c0(5 downto 0)) or + (repeat(7, sig_1552) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0)) or + (repeat(7, sig_1458) and get_dht_index & get_dht_i(5 downto 0)); + + -- Behaviour of component 'mux_723' model 'mux' + mux_723 <= + (repeat(10, sig_1304) and decodehuffman_dc_tbl_no & decodehuffman_dc_p) or + (repeat(10, sig_1480) and get_dht_index & get_dht_i(8 downto 0)); + + -- Behaviour of component 'mux_719' model 'mux' + mux_719 <= + (repeat(7, sig_1505) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_i_c0(5 downto 0)) or + (repeat(7, sig_1547) and huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0)) or + (repeat(7, sig_1458) and get_dht_index & get_dht_i(5 downto 0)); + + -- Behaviour of component 'mux_539' model 'mux' + mux_539 <= + (repeat(32, sig_1118) and sig_1624(31 downto 0)) or + (repeat(32, sig_1354) and sig_1642) or + (repeat(32, sig_1472) and sig_1639(29 downto 0) & "00"); + + -- Behaviour of component 'mux_541' model 'mux' + mux_541 <= + (repeat(32, sig_999) and sig_1639(29 downto 0) & "00") or + (repeat(32, sig_1118) and sig_1613) or + (repeat(32, sig_1357) and sig_1642); + + -- Behaviour of component 'mux_537' model 'mux' + mux_537 <= + (repeat(32, sig_1285) and sig_1642) or + (repeat(32, sig_1325) and sig_1639(29 downto 0) & "00") or + (repeat(32, sig_1463) and sig_1621(31 downto 0)); + + -- Behaviour of component 'mux_533' model 'mux' + mux_533 <= + (repeat(32, sig_1324) and sig_1614(40 downto 9)) or + (repeat(32, sig_1395) and sig_1627(39 downto 8)); + + -- Behaviour of component 'mux_535' model 'mux' + mux_535 <= + (repeat(32, sig_1118) and sig_1614(40 downto 9)) or + (repeat(32, sig_1463) and sig_1609(31 downto 0)); + + -- Behaviour of component 'mux_715' model 'mux' + mux_715 <= + (repeat(10, sig_1284) and decodehuffman_ac_tbl_no & decodehuffman_ac_p) or + (repeat(10, sig_1480) and get_dht_index & get_dht_i(8 downto 0)); + + -- Behaviour of component 'mux_711' model 'mux' + mux_711 <= + (sig_1170 and decodehuffmcu_tbl_no) or + (sig_1189 and '1'); + + -- Behaviour of component 'mux_705' model 'mux' + mux_705 <= + (repeat(32, sig_1271) and sig_1632) or + (repeat(32, sig_1554) and "11111111111111111111111111111111") or + (repeat(32, sig_1561) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_706' model 'mux' + mux_706 <= + (repeat(7, sig_1553) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0)) or + (repeat(7, sig_1561) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_p_dhtbl_ml(5 downto 0)); + + -- Behaviour of component 'mux_707' model 'mux' + mux_707 <= + (repeat(7, sig_1561) and huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_p_dhtbl_ml(5 downto 0)) or + (repeat(7, sig_1575) and decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0)) or + (repeat(7, sig_1577) and decodehuffman_dc_tbl_no & decodehuffman_dc_dhuff_ml); + + -- Behaviour of component 'mux_531' model 'mux' + mux_531 <= + (repeat(32, sig_1324) and sig_1609(38 downto 7)) or + (repeat(32, sig_1395) and sig_1628(39 downto 8)); + + -- Behaviour of component 'mux_529' model 'mux' + mux_529 <= + (repeat(32, sig_1118) and sig_1610(38 downto 7)) or + (repeat(32, sig_1463) and sig_1613); + + -- Behaviour of component 'mux_695' model 'mux' + mux_695 <= + (sig_1184 and '1') or + (sig_1453 and decodehuffmcu_tbl_no); + + -- Behaviour of component 'mux_524' model 'mux' + mux_524 <= + (repeat(5, sig_1310) and decodehuffmcu_s(4 downto 0)) or + (repeat(5, sig_1482) and read_position(4 downto 0)); + + -- Behaviour of component 'mux_521' model 'mux' + mux_521 <= + (repeat(32, sig_1422) and "000000000000000000000000" & pgetc) or + (repeat(32, sig_1493) and or_802 & pgetc); + + -- Behaviour of component 'mux_519' model 'mux' + mux_519 <= + (repeat(32, sig_1484) and sig_1614(31 downto 0)) or + (repeat(32, sig_1355) and sig_1624(31 downto 0)) or + (repeat(32, sig_1421) and "00000000000000000000000000000111") or + (repeat(32, sig_1493) and sig_1610(28 downto 0) & read_position(2 downto 0)) or + (repeat(32, sig_1497) and "11111111111111111111111111111111"); + + -- Behaviour of component 'mux_517' model 'mux' + mux_517 <= + (repeat(8, sig_1423) and "11111111") or + (repeat(8, sig_1425) and pgetc_temp); + + -- Behaviour of component 'mux_507' model 'mux' + mux_507 <= + (repeat(32, sig_1008) and and_984) or + (repeat(32, sig_1345) and and_853) or + (repeat(32, sig_1497) and and_801); + + -- Behaviour of component 'mux_505' model 'mux' + mux_505 <= + (repeat(32, sig_1167) and sig_1614(31 downto 0)) or + (repeat(32, sig_1197) and decodehuffmcu_s) or + (repeat(32, sig_1201) and decodehuffman_dc); + + -- Behaviour of component 'mux_501' model 'mux' + mux_501 <= + (repeat(32, sig_1355) and or_845) or + (repeat(32, sig_1489) and sig_1626); + + -- Behaviour of component 'mux_492' model 'mux' + mux_492 <= + (repeat(32, sig_1186) and sig_1652) or + (repeat(32, sig_1514) and "00000000000000000000000000000001") or + (repeat(32, sig_1544) and huff_make_dhuff_tb_ac_l); + + -- Behaviour of component 'mux_488' model 'mux' + mux_488 <= + (repeat(32, sig_1499) and sig_1609(31 downto 0)) or + (repeat(32, sig_1504) and "00000000000000000000000000000001"); + + -- Behaviour of component 'mux_490' model 'mux' + mux_490 <= + (repeat(32, sig_1498) and "00000000000000000000000000000001") or + (repeat(32, sig_1507) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_486' model 'mux' + mux_486 <= + (repeat(32, sig_1500) and sig_1610(31 downto 0)) or + (repeat(32, sig_1544) and sig_1609(31 downto 0)); + + -- Behaviour of component 'mux_482' model 'mux' + mux_482 <= + (repeat(32, sig_1283) and sig_1610(31 downto 0)) or + (repeat(32, sig_1558) and sig_1635); + + -- Behaviour of component 'mux_484' model 'mux' + mux_484 <= + (repeat(32, sig_1023) and sig_1609(31 downto 0)) or + (repeat(32, sig_1283) and huff_make_dhuff_tb_ac_code(30 downto 0) & '0'); + + -- Behaviour of component 'mux_480' model 'mux' + mux_480 <= + (repeat(32, sig_1514) and "00000000000000000000000000000001") or + (repeat(32, sig_1525) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_476' model 'mux' + mux_476 <= + (repeat(32, sig_1499) and huff_make_dhuff_tb_ac_i_c0); + + -- Behaviour of component 'mux_478' model 'mux' + mux_478 <= + (repeat(9, sig_1511) and huff_make_dhuff_tb_ac_p(8 downto 0)); + + -- Behaviour of component 'mux_459' model 'mux' + mux_459 <= + (repeat(32, sig_1038) and huff_make_dhuff_tb_dc_l) or + (repeat(32, sig_1305) and sig_1656) or + (repeat(32, sig_1542) and "00000000000000000000000000000001"); + + -- Behaviour of component 'mux_455' model 'mux' + mux_455 <= + (repeat(32, sig_1527) and sig_1609(31 downto 0)) or + (repeat(32, sig_1533) and "00000000000000000000000000000001"); + + -- Behaviour of component 'mux_457' model 'mux' + mux_457 <= + (repeat(32, sig_1526) and "00000000000000000000000000000001") or + (repeat(32, sig_1536) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_453' model 'mux' + mux_453 <= + (repeat(32, sig_1038) and sig_1609(31 downto 0)) or + (repeat(32, sig_1528) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_449' model 'mux' + mux_449 <= + (repeat(32, sig_1033) and sig_1633) or + (repeat(32, sig_1068) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_451' model 'mux' + mux_451 <= + (repeat(32, sig_1035) and sig_1609(31 downto 0)) or + (repeat(32, sig_1068) and huff_make_dhuff_tb_dc_code(30 downto 0) & '0'); + + -- Behaviour of component 'mux_447' model 'mux' + mux_447 <= + (repeat(32, sig_1542) and "00000000000000000000000000000001") or + (repeat(32, sig_1563) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_443' model 'mux' + mux_443 <= + (repeat(32, sig_1527) and huff_make_dhuff_tb_dc_i_c0); + + -- Behaviour of component 'mux_445' model 'mux' + mux_445 <= + (repeat(9, sig_1537) and huff_make_dhuff_tb_dc_p(8 downto 0)); + + -- Behaviour of component 'mux_430' model 'mux' + mux_430 <= + (repeat(32, sig_1284) and sig_1657); + + -- Behaviour of component 'mux_422' model 'mux' + mux_422 <= + (repeat(32, sig_1565) and "00000000000000000000000000000001") or + (repeat(32, sig_1567) and sig_1609(31 downto 0)); + + -- Behaviour of component 'mux_424' model 'mux' + mux_424 <= + (repeat(32, sig_1565) and "0000000000000000000000000000000" & buf_getb) or + (repeat(32, sig_1567) and sig_1610(30 downto 0) & buf_getb); + + -- Behaviour of component 'mux_416' model 'mux' + mux_416 <= + (repeat(32, sig_1304) and sig_1659); + + -- Behaviour of component 'mux_410' model 'mux' + mux_410 <= + (repeat(32, sig_1571) and "0000000000000000000000000000000" & buf_getb) or + (repeat(32, sig_1574) and sig_1610(30 downto 0) & buf_getb); + + -- Behaviour of component 'mux_408' model 'mux' + mux_408 <= + (repeat(32, sig_1571) and "00000000000000000000000000000001") or + (repeat(32, sig_1574) and sig_1609(31 downto 0)); + + -- Behaviour of component 'mux_398' model 'mux' + mux_398 <= + (repeat(32, sig_1026) and sig_1610(31 downto 0)) or + (repeat(32, sig_1341) and buf_getv) or + (repeat(32, sig_1344) and or_854); + + -- Behaviour of component 'mux_400' model 'mux' + mux_400 <= + (repeat(32, sig_1030) and and_982) or + (repeat(32, sig_1342) and sig_1614(31 downto 0)) or + (repeat(32, sig_1579) and decodehuffman_dc); + + -- Behaviour of component 'mux_392' model 'mux' + mux_392 <= + (repeat(32, sig_1454) and "00000000000000000000000000000001") or + (repeat(32, sig_1466) and sig_1610(31 downto 0)) or + (repeat(32, sig_1464) and sig_1610(27 downto 0) & decodehuffmcu_k(3 downto 0)); + + -- Behaviour of component 'mux_394' model 'mux' + mux_394 <= + (repeat(32, sig_1443) and sig_1610(31 downto 0)) or + (repeat(32, sig_1445) and "00000000000000000000000000000001"); + + -- Behaviour of component 'mux_378' model 'mux' + mux_378 <= + (repeat(8, sig_1070) and yuvtorgb_r(7 downto 0)) or + (repeat(8, sig_1234) and yuvtorgb_b(7 downto 0)) or + (repeat(8, sig_1237) and yuvtorgb_g(7 downto 0)); + + -- Behaviour of component 'mux_379' model 'mux' + mux_379 <= + (repeat(10, sig_1070) and yuvtorgb_p & "00" & yuvtorgb_i(5 downto 0)) or + (repeat(10, sig_1234) and yuvtorgb_p & "10" & yuvtorgb_i(5 downto 0)) or + (repeat(10, sig_1237) and yuvtorgb_p & "01" & yuvtorgb_i(5 downto 0)); + + -- Behaviour of component 'mux_375' model 'mux' + mux_375 <= + (repeat(2, sig_1020) and write4blocks_i) or + (repeat(2, sig_1196) and decode_start_i(1 downto 0)); + + -- Behaviour of component 'mux_373' model 'mux' + mux_373 <= + (repeat(2, sig_1005) and "10") or + (repeat(2, sig_1004) and "11") or + (repeat(2, sig_1019) and "01"); + + -- Behaviour of component 'mux_365' model 'mux' + mux_365 <= + (repeat(32, sig_1005) and sig_1614(31 downto 0)) or + (repeat(32, sig_1021) and sig_1610(28 downto 0) & write4blocks_hoffs(2 downto 0)) or + (repeat(32, sig_1196) and sig_1647(28 downto 0) & "000"); + + -- Behaviour of component 'mux_367' model 'mux' + mux_367 <= + (repeat(32, sig_1005) and sig_1610(28 downto 0) & write4blocks_voffs(2 downto 0)) or + (repeat(32, sig_1021) and write4blocks_voffs) or + (repeat(32, sig_1196) and sig_1648(28 downto 0) & "000"); + + -- Behaviour of component 'mux_363' model 'mux' + mux_363 <= + (repeat(32, sig_1018) and sig_1610(31 downto 0)) or + (repeat(32, sig_1065) and writeoneblock_voffs); + + -- Behaviour of component 'mux_359' model 'mux' + mux_359 <= + (repeat(32, sig_1012) and sig_1609(31 downto 0)); + + -- Behaviour of component 'mux_361' model 'mux' + mux_361 <= + (repeat(32, sig_1017) and sig_1610(31 downto 0)) or + (repeat(32, sig_1081) and writeoneblock_hoffs); + + -- Behaviour of component 'mux_347' model 'mux' + mux_347 <= + (repeat(32, sig_1005) and sig_1610(28 downto 0) & write4blocks_voffs(2 downto 0)) or + (repeat(32, sig_1194) and sig_1648(28 downto 0) & "000"); + + -- Behaviour of component 'mux_345' model 'mux' + mux_345 <= + (repeat(32, sig_1005) and sig_1614(31 downto 0)) or + (repeat(32, sig_1021) and sig_1610(28 downto 0) & write4blocks_hoffs(2 downto 0)) or + (repeat(32, sig_1194) and sig_1647(28 downto 0) & "000"); + + -- Behaviour of component 'mux_341' model 'mux' + mux_341 <= + (repeat(3, sig_993) and decode_start_i(2 downto 0)); + + -- Behaviour of component 'mux_343' model 'mux' + mux_343 <= + (repeat(2, sig_993) and decode_start_i(1 downto 0)); + + -- Behaviour of component 'mux_339' model 'mux' + mux_339 <= + (repeat(3, sig_993) and "100") or + (repeat(3, sig_997) and "001"); + + -- Behaviour of component 'mux_335' model 'mux' + mux_335 <= + (repeat(32, sig_1060) and mux_965) or + (repeat(32, sig_1217) and sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24) & sig_1611(24 downto 1)); + + -- Behaviour of component 'mux_337' model 'mux' + mux_337 <= + (repeat(3, sig_993) and "101") or + (repeat(3, sig_997) and "010"); + + -- Behaviour of component 'mux_333' model 'mux' + mux_333 <= + (repeat(32, sig_1060) and mux_969) or + (repeat(32, sig_1217) and sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24) & sig_1610(24 downto 1)); + + -- Behaviour of component 'mux_331' model 'mux' + mux_331 <= + (repeat(32, sig_1060) and mux_967) or + (repeat(32, sig_1217) and sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24) & sig_1613(24 downto 1)); + + -- Behaviour of component 'mux_323' model 'mux' + mux_323 <= + (repeat(6, sig_1345) and buf_getv_p(5 downto 0)) or + (repeat(6, sig_1355) and sig_1614(5 downto 0)); + + -- Behaviour of component 'mux_320' model 'mux' + mux_320 <= + (repeat(32, sig_1234) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_322' model 'mux' + mux_322 <= + (repeat(32, sig_1345) and current_read_byte) or + (repeat(32, sig_1355) and "000000000000000000000000" & pgetc); + + -- Behaviour of component 'mux_317' model 'mux' + mux_317 <= + (repeat(2, sig_995) and "01") or + (repeat(2, sig_994) and "10") or + (repeat(2, sig_1045) and decode_start_i(1 downto 0)); + + -- Behaviour of component 'mux_314' model 'mux' + mux_314 <= + (repeat(32, sig_1324) and chenidct_a2) or + (repeat(32, sig_1118) and chenidct_a3) or + (repeat(32, sig_1217) and yuvtorgb_v(30) & yuvtorgb_v(30 downto 0)) or + (repeat(32, sig_1349) and chenidct_b3) or + (repeat(32, sig_1395) and sig_1614(31 downto 0)); + + -- Behaviour of component 'mux_315' model 'mux' + mux_315 <= + (repeat(32, sig_1349) and "00000000000000000000000000110001") or + (repeat(32, sig_1101) and p_jinfo_mcuwidth) or + (repeat(32, sig_1118) and "00000000000000000000000000011001") or + (repeat(32, sig_1217) and "00000000000000000000000000001011") or + (repeat(32, sig_1324) and "00000000000000000000000011010101") or + (repeat(32, sig_1081) and writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12) & writeoneblock_i(12 downto 0)) or + (repeat(32, sig_1395) and "00000000000000000000000010110101") or + (repeat(32, sig_1433) and sig_1661); + + -- Behaviour of component 'mux_316' model 'mux' + mux_316 <= + (repeat(32, sig_1349) and chenidct_b2) or + (repeat(32, sig_1101) and p_jinfo_mcuheight) or + (repeat(32, sig_1118) and chenidct_a0) or + (repeat(32, sig_1217) and yuvtorgb_u(28) & yuvtorgb_u(28) & yuvtorgb_u(28) & yuvtorgb_u(28 downto 0)) or + (repeat(32, sig_1324) and chenidct_a1) or + (repeat(32, sig_1081) and writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12) & writeoneblock_width(12 downto 0)) or + (repeat(32, sig_1395) and sig_1610(31 downto 0)) or + (repeat(32, sig_1433) and sig_1639); + + -- Behaviour of component 'mux_313' model 'mux' + mux_313 <= + (repeat(9, sig_1324) and "001000111") or + (repeat(9, sig_1118) and "011111011") or + (repeat(9, sig_1217) and "001011011") or + (repeat(9, sig_1349) and "111011001") or + (repeat(9, sig_1395) and "010110101"); + + -- Behaviour of component 'mux_308' model 'mux' + mux_308 <= + (repeat(3, sig_994) and "101") or + (repeat(3, sig_995) and "100") or + (repeat(3, sig_1046) and decode_start_i(2 downto 0)); + + -- Behaviour of component 'mux_306' model 'mux' + mux_306 <= + (repeat(41, sig_1451) and "00000000000000000000000000000000000001000") or + (repeat(41, sig_1299) and "00000000000000000000000000000000010000000") or + (repeat(41, sig_1308) and "00000000000000000000000000000000000000001") or + (repeat(41, sig_1324) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or + (repeat(41, sig_1355) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or + (repeat(41, sig_1217) and sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30) & sig_1627(30 downto 0) & '0') or + (repeat(41, sig_1161) and "00000000000000000000000000000000000000010") or + (repeat(41, sig_1118) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or + (repeat(41, sig_1470) and "00000000000000000000000000000000011111111") or + (repeat(41, sig_1463) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2); + + -- Behaviour of component 'mux_307' model 'mux' + mux_307 <= + (repeat(41, sig_1355) and "00000000000000000000000000000000000000111") or + (repeat(41, sig_1217) and sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31) & sig_1614(31 downto 0)) or + (repeat(41, sig_1299) and sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30) & sig_1641(30 downto 0)) or + (repeat(41, sig_1309) and p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width) or + (repeat(41, sig_1324) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or + (repeat(41, sig_1216) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648) or + (repeat(41, sig_1118) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or + (repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or + (repeat(41, sig_1468) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or + (repeat(41, sig_1463) and chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3(31) & chenidct_c3); + + -- Behaviour of component 'mux_302' model 'mux' + mux_302 <= + (repeat(41, sig_1216) and p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth) or + (repeat(41, sig_1470) and "00000000000000000000000000000000011111111") or + (repeat(41, sig_1463) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3); + + -- Behaviour of component 'mux_303' model 'mux' + mux_303 <= + (repeat(41, sig_1216) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or + (repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or + (repeat(41, sig_1471) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or + (repeat(41, sig_1463) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0); + + -- Behaviour of component 'mux_294' model 'mux' + mux_294 <= + (repeat(2, sig_995) and "01") or + (repeat(2, sig_994) and "10") or + (repeat(2, sig_1045) and decode_start_i(1 downto 0)); + + -- Behaviour of component 'mux_290' model 'mux' + mux_290 <= + (repeat(41, sig_1395) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or + (repeat(41, sig_1376) and "00000000000000000000000000000000000000111") or + (repeat(41, sig_1363) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2) or + (repeat(41, sig_1355) and buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5) & buf_getv_p(5 downto 0)) or + (repeat(41, sig_1349) and sig_1627) or + (repeat(41, sig_1534) and sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660) or + (repeat(41, sig_1324) and sig_1667(38 downto 0) & "00") or + (repeat(41, sig_1318) and "00000000000000000000000000000000000000010") or + (repeat(41, sig_1313) and get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count) or + (repeat(41, sig_1300) and "00000000000000000000000000000000000010001") or + (repeat(41, sig_1299) and "00000000000000000000000000000000010000000") or + (repeat(41, sig_1292) and sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654(8) & sig_1654) or + (repeat(41, sig_1289) and sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650(8) & sig_1650) or + (repeat(41, sig_1280) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or + (repeat(41, sig_1550) and "00000000000000000000000000000000000010000") or + (repeat(41, sig_1569) and sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651) or + (repeat(41, sig_1576) and sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655) or + (repeat(41, sig_1505) and sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658) or + (repeat(41, sig_1491) and "00000000000000000000000000000000000001000") or + (repeat(41, sig_1486) and "00000000000000000000000000000000000010111") or + (repeat(41, sig_1485) and "00000000000000000000000000000000000000001") or + (repeat(41, sig_1440) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or + (repeat(41, sig_1434) and "00000000000000000000000000000000000111111") or + (repeat(41, sig_1244) and "000000000000000000000000000000000" & p_jinfo_num_components) or + (repeat(41, sig_1241) and "000000000000000000000000000000000" & get_sos_num_comp) or + (repeat(41, sig_1240) and "00000000000000000000000000000000001000000") or + (repeat(41, sig_1229) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or + (repeat(41, sig_1217) and sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28) & sig_1628(28 downto 0) & "000") or + (repeat(41, sig_1216) and p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth(31) & p_jinfo_mcuwidth) or + (repeat(41, sig_1165) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or + (repeat(41, sig_1118) and sig_1627(39 downto 0) & '0') or + (repeat(41, sig_1089) and "00000000000000000000000000000000001000001") or + (repeat(41, sig_1077) and "00000000000000000000000000000000100000000") or + (repeat(41, sig_1049) and "00000000000000000000000000000000000000011") or + (repeat(41, sig_1048) and p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu(31) & p_jinfo_nummcu) or + (repeat(41, sig_1032) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position) or + (repeat(41, sig_1015) and writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width(31) & writeoneblock_width) or + (repeat(41, sig_1014) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 0) & writeoneblock_hoffs(2 downto 0)) or + (repeat(41, sig_1010) and writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height(31) & writeoneblock_height) or + (repeat(41, sig_1009) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 0) & writeoneblock_voffs(2 downto 0)); + + -- Behaviour of component 'mux_291' model 'mux' + mux_291 <= + (repeat(41, sig_1468) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642) or + (repeat(41, sig_1505) and huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j) or + (repeat(41, sig_1502) and huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0) or + (repeat(41, sig_1492) and buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p(31) & buf_getv_p) or + (repeat(41, sig_1487) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position) or + (repeat(41, sig_1420) and chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i) or + (repeat(41, sig_1569) and decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code(31) & decodehuffman_ac_code) or + (repeat(41, sig_1395) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or + (repeat(41, sig_1393) and chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2) or + (repeat(41, sig_1363) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or + (repeat(41, sig_1355) and "00000000000000000000000000000000000001000") or + (repeat(41, sig_1349) and sig_1628(38 downto 0) & "00") or + (repeat(41, sig_1342) and decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s(31) & decodehuffmcu_s) or + (repeat(41, sig_1336) and get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i) or + (repeat(41, sig_1324) and sig_1666(39 downto 0) & '0') or + (repeat(41, sig_1576) and decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code(31) & decodehuffman_dc_code) or + (repeat(41, sig_1446) and decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i) or + (repeat(41, sig_1455) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k) or + (repeat(41, sig_1551) and huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l) or + (repeat(41, sig_1534) and huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j) or + (repeat(41, sig_1531) and huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0) or + (repeat(41, sig_1518) and huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l) or + (repeat(41, sig_1463) and chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0) or + (repeat(41, sig_1435) and izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i) or + (repeat(41, sig_1322) and get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length(31) & get_dqt_length) or + (repeat(41, sig_1319) and read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word(15) & read_word) or + (repeat(41, sig_1314) and get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length(31) & get_dht_length) or + (repeat(41, sig_1309) and p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height) or + (repeat(41, sig_1303) and get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i) or + (repeat(41, sig_1299) and sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640(31) & sig_1640) or + (repeat(41, sig_1291) and sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8) & sig_1610(8 downto 0)) or + (repeat(41, sig_1287) and get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j(31) & get_sos_j) or + (repeat(41, sig_1280) and chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3) or + (repeat(41, sig_1245) and get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci) or + (repeat(41, sig_1241) and get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i) or + (repeat(41, sig_1229) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or + (repeat(41, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y & "00000000") or + (repeat(41, sig_1216) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or + (repeat(41, sig_1209) and get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci) or + (repeat(41, sig_1168) and buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n(31) & buf_getv_n) or + (repeat(41, sig_1118) and sig_1628(37) & sig_1628(37 downto 0) & "00") or + (repeat(41, sig_1078) and huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p) or + (repeat(41, sig_1060) and yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r(31) & yuvtorgb_r) or + (repeat(41, sig_1051) and decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i) or + (repeat(41, sig_1048) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu) or + (repeat(41, sig_1037) and huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p) or + (repeat(41, sig_1025) and yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i) or + (repeat(41, sig_1016) and writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e) or + (repeat(41, sig_1011) and writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i) or + (repeat(41, sig_1005) and write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs); + + -- Behaviour of component 'mux_292' model 'mux' + mux_292 <= + (repeat(32, sig_1294) and sig_1613) or + (repeat(32, sig_1427) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_286' model 'mux' + mux_286 <= + (repeat(32, sig_1047) and sig_1610(31 downto 0)) or + (repeat(32, sig_1052) and sig_1610(29 downto 0) & decode_start_currentmcu(1 downto 0)); + + -- Behaviour of component 'mux_275' model 'mux' + mux_275 <= + (repeat(32, sig_1396) and chenidct_i) or + (repeat(32, sig_1118) and chenidct_a1) or + (repeat(32, sig_1217) and sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23) & sig_1609(23 downto 0) & sig_1666(6)) or + (repeat(32, sig_1294) and decode_start_i) or + (repeat(32, sig_1309) and sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16) & sig_1624(16 downto 3)) or + (repeat(32, sig_1451) and sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31 downto 4)) or + (repeat(32, sig_1463) and chenidct_c3); + + -- Behaviour of component 'mux_272' model 'mux' + mux_272 <= + (repeat(39, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y) or + (repeat(39, sig_1118) and sig_1600(40 downto 2)) or + (repeat(39, sig_1309) and sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16) & sig_1613(16 downto 0)) or + (repeat(39, sig_1449) and chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i(31) & chenidct_i); + + -- Behaviour of component 'mux_274' model 'mux' + mux_274 <= + (repeat(32, sig_1397) and "00000000000000000000000000000001") or + (repeat(32, sig_1118) and chenidct_a2) or + (repeat(32, sig_1309) and "0000000000000000000000000000000" & and_864) or + (repeat(32, sig_1451) and "0000000000000000000000000000000" & and_789) or + (repeat(32, sig_1463) and chenidct_c2); + + -- Behaviour of component 'mux_271' model 'mux' + mux_271 <= + (repeat(39, sig_1118) and sig_1668(38 downto 0)) or + (repeat(39, sig_1217) and sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31) & sig_1667(31 downto 8)) or + (repeat(39, sig_1448) and "000000000000000000000000000000000000001"); + + -- Behaviour of component 'mux_266' model 'mux' + mux_266 <= + (repeat(39, sig_1463) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or + (repeat(39, sig_1574) and decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30) & decodehuffman_dc_code(30 downto 0)) or + (repeat(39, sig_1567) and decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30) & decodehuffman_ac_code(30 downto 0)) or + (repeat(39, sig_1563) and huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l(31) & huff_make_dhuff_tb_dc_l) or + (repeat(39, sig_1561) and sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655(31) & sig_1655) or + (repeat(39, sig_1556) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31 downto 7)) or + (repeat(39, sig_1479) and get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i(31) & get_dht_i) or + (repeat(39, sig_1548) and huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p(31) & huff_make_dhuff_tb_ac_p) or + (repeat(39, sig_1536) and huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0(31) & huff_make_dhuff_tb_dc_i_c0) or + (repeat(39, sig_1529) and huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p(31) & huff_make_dhuff_tb_dc_p) or + (repeat(39, sig_1525) and huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l(31) & huff_make_dhuff_tb_ac_l) or + (repeat(39, sig_1523) and sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651(31) & sig_1651) or + (repeat(39, sig_1507) and huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0(31) & huff_make_dhuff_tb_ac_i_c0) or + (repeat(39, sig_1493) and read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31) & read_position(31 downto 3)) or + (repeat(39, sig_1412) and "0000000" & chenidct_aidx) or + (repeat(39, sig_1477) and "0000000000" & chenidct_aidx(31 downto 3)) or + (repeat(39, sig_1466) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k) or + (repeat(39, sig_1464) and decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31) & decodehuffmcu_k(31 downto 4)) or + (repeat(39, sig_1451) and sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31) & sig_1642(31 downto 3)) or + (repeat(39, sig_1443) and decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i(31) & decodehuffmcu_i) or + (repeat(39, sig_1441) and "0000000" & curhuffreadbuf_idx) or + (repeat(39, sig_1582) and "0000000000" & chenidct_i(31 downto 3)) or + (repeat(39, sig_1436) and izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i(31) & izigzagmatrix_i) or + (repeat(39, sig_1427) and decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i(31) & decode_start_i) or + (repeat(39, sig_1395) and chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1(31) & chenidct_a1) or + (repeat(39, sig_1350) and "0000000" & chenidct_i(28 downto 0) & "001") or + (repeat(39, sig_1335) and get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num(1) & get_dqt_num) or + (repeat(39, sig_1309) and sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16) & sig_1614(16 downto 3)) or + (repeat(39, sig_1297) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647) or + (repeat(39, sig_1292) and sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653(8) & sig_1653) or + (repeat(39, sig_1289) and sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649(8) & sig_1649) or + (repeat(39, sig_1283) and huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size(31) & huff_make_dhuff_tb_ac_size) or + (repeat(39, sig_1264) and chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2(31) & chenidct_b2) or + (repeat(39, sig_1257) and sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643) or + (repeat(39, sig_1254) and get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci(31) & get_sos_ci) or + (repeat(39, sig_1251) and get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i(31) & get_sos_i) or + (repeat(39, sig_1247) and "0000000" & readbuf_idx) or + (repeat(39, sig_1234) and yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i(31) & yuvtorgb_i) or + (repeat(39, sig_1217) and sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31) & sig_1624(31 downto 7)) or + (repeat(39, sig_1211) and get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci(31) & get_sof_ci) or + (repeat(39, sig_1163) and sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31) & sig_1647(31 downto 1)) or + (repeat(39, sig_1118) and sig_1666(39 downto 1)) or + (repeat(39, sig_1112) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or + (repeat(39, sig_1110) and chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3(31) & chenidct_b3) or + (repeat(39, sig_1073) and "0000000000000000000000000000000000000" & sig_1663) or + (repeat(39, sig_1068) and huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size(31) & huff_make_dhuff_tb_dc_size) or + (repeat(39, sig_1059) and "0000000" & jpeg2bmp_main_j) or + (repeat(39, sig_1056) and "0000000" & jpeg2bmp_main_i) or + (repeat(39, sig_1052) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31 downto 2)) or + (repeat(39, sig_1047) and decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu(31) & decode_start_currentmcu) or + (repeat(39, sig_1026) and decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff(31) & decodehuffmcu_diff) or + (repeat(39, sig_1021) and write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31) & write4blocks_hoffs(31 downto 3)) or + (repeat(39, sig_1018) and writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i(31) & writeoneblock_i) or + (repeat(39, sig_1017) and writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e(31) & writeoneblock_e) or + (repeat(39, sig_1014) and writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31) & writeoneblock_hoffs(31 downto 3)) or + (repeat(39, sig_1012) and writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff(12) & writeoneblock_diff) or + (repeat(39, sig_1009) and writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31) & writeoneblock_voffs(31 downto 3)) or + (repeat(39, sig_1005) and write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31) & write4blocks_voffs(31 downto 3)); + + -- Behaviour of component 'mux_265' model 'mux' + mux_265 <= + (repeat(39, sig_1112) and chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2(31) & chenidct_c2) or + (repeat(39, sig_1110) and chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0(31) & chenidct_a0) or + (repeat(39, sig_1027) and sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643(31) & sig_1643) or + (repeat(39, sig_1012) and writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12) & writeoneblock_e(12 downto 0)) or + (repeat(39, sig_1006) and "00000000000" & decodehuffmcu_n) or + (repeat(39, sig_1309) and "00000000000000000000000000000000000000" & and_862) or + (repeat(39, sig_1395) and chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2(31) & chenidct_a2) or + (repeat(39, sig_1546) and "111111111111111111111111111111111111111") or + (repeat(39, sig_1556) and "000000000000000000000000000000000000001") or + (repeat(39, sig_1292) and decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8) & decodehuffman_dc_code(8 downto 0)) or + (repeat(39, sig_1289) and decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8) & decodehuffman_ac_code(8 downto 0)) or + (repeat(39, sig_1264) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or + (repeat(39, sig_1118) and sig_1667(37) & sig_1667(37 downto 0)) or + (repeat(39, sig_1463) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or + (repeat(39, sig_1426) and "000000000000000000000000000000000000001"); + + -- Behaviour of component 'mux_260' model 'mux' + mux_260 <= + (repeat(39, sig_1458) and "0000000000000000000000000000000" & read_byte) or + (repeat(39, sig_1324) and sig_1627(38 downto 0)) or + (repeat(39, sig_1395) and chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3(31) & chenidct_a3) or + (repeat(39, sig_1544) and sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658(31) & sig_1658) or + (repeat(39, sig_1451) and "00000000000000000000000000000000000000" & and_785) or + (repeat(39, sig_1217) and sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30) & sig_1666(30 downto 7)) or + (repeat(39, sig_1118) and chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1(31) & chenidct_b1) or + (repeat(39, sig_1038) and sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660(31) & sig_1660) or + (repeat(39, sig_1463) and chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1(31) & chenidct_c1) or + (repeat(39, sig_1438) and "000000000000000000000000000000000000001"); + + -- Behaviour of component 'mux_261' model 'mux' + mux_261 <= + (repeat(39, sig_1458) and get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count(31) & get_dht_count) or + (repeat(39, sig_1324) and sig_1628(39 downto 1)) or + (repeat(39, sig_1309) and sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16) & sig_1610(16 downto 0)) or + (repeat(39, sig_1297) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648) or + (repeat(39, sig_1262) and "0000000" & chenidct_aidx) or + (repeat(39, sig_1217) and yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y(23) & yuvtorgb_y) or + (repeat(39, sig_1546) and sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31) & sig_1610(31 downto 0)) or + (repeat(39, sig_1163) and sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31) & sig_1648(31 downto 1)) or + (repeat(39, sig_1111) and "0000000000" & chenidct_aidx(31 downto 3)) or + (repeat(39, sig_1035) and huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code(31) & huff_make_dhuff_tb_dc_code) or + (repeat(39, sig_1023) and huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code(31) & huff_make_dhuff_tb_ac_code) or + (repeat(39, sig_1012) and "0000000" & writeoneblock_inidx) or + (repeat(39, sig_1567) and decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l(31) & decodehuffman_ac_l) or + (repeat(39, sig_1574) and decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l(31) & decodehuffman_dc_l) or + (repeat(39, sig_1451) and sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28) & sig_1610(28 downto 1)) or + (repeat(39, sig_1527) and huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j(31) & huff_make_dhuff_tb_dc_j) or + (repeat(39, sig_1499) and huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j(31) & huff_make_dhuff_tb_ac_j) or + (repeat(39, sig_1398) and chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0(31) & chenidct_b0) or + (repeat(39, sig_1335) and get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i(31) & get_dqt_i) or + (repeat(39, sig_1463) and chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0(31) & chenidct_c0) or + (repeat(39, sig_1436) and izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx(31) & izigzagmatrix_out_idx); + + -- Behaviour of component 'mux_262' model 'mux' + mux_262 <= + (repeat(32, sig_1056) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_257' model 'mux' + mux_257 <= + (repeat(32, sig_1059) and sig_1610(31 downto 0)); + + -- Behaviour of component 'nand_786' model 'nand' + nand_786 <= not ( + sig_1605 and + sig_1606 + ); + + -- Behaviour of component 'or_845' model 'or' + or_845 <= + sig_1629 or + buf_getv_rv; + + -- Behaviour of component 'or_854' model 'or' + or_854 <= + sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638 or + buf_getv; + + -- Behaviour of component 'or_866' model 'or' + or_866 <= + sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638(20) & sig_1638 or + sig_1643; + + -- Behaviour of component 'and_785' model 'and' + and_785 <= + nand_786 and + sig_1610(28); + + -- Behaviour of component 'and_801' model 'and' + and_801 <= + sig_1636 and + current_read_byte; + + -- Behaviour of component 'mux_761' model 'mux' + mux_761 <= + (repeat(9, sig_1118) and "000011001") or + (repeat(9, sig_1217) and "101100111") or + (repeat(9, sig_1324) and "001000111"); + + -- Behaviour of component 'mux_782' model 'mux' + mux_782 <= + (repeat(32, sig_1607) and sig_1660) or + (repeat(32, sig_1608) and "000000000000000000000000" & read_byte); + + -- Behaviour of component 'or_802' model 'or' + or_802 <= + current_read_byte(23 downto 0) or + "000000000000000000000000"; + + -- Behaviour of component 'and_803' model 'and' + and_803 <= + sig_1637 and + current_read_byte; + + -- Behaviour of component 'mux_822' model 'mux' + mux_822 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_823' model 'mux' + mux_823 <= + (repeat(32, sig_1617) and mux_824); + + -- Behaviour of component 'mux_776' model 'mux' + mux_776 <= + (repeat(32, sig_1617) and mux_777); + + -- Behaviour of component 'mux_820' model 'mux' + mux_820 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_824' model 'mux' + mux_824 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_825' model 'mux' + mux_825 <= + (repeat(32, sig_1617) and mux_826); + + -- Behaviour of component 'mux_760' model 'mux' + mux_760 <= + (repeat(32, sig_1118) and chenidct_a0) or + (repeat(32, sig_1217) and yuvtorgb_u(30) & yuvtorgb_u) or + (repeat(32, sig_1324) and chenidct_a2); + + -- Behaviour of component 'and_789' model 'and' + and_789 <= + sig_1604 and + sig_1624(31); + + -- Behaviour of component 'mux_759' model 'mux' + mux_759 <= + (repeat(6, sig_1118) and "111011") or + (repeat(6, sig_1217) and "100011") or + (repeat(6, sig_1324) and "010101"); + + -- Behaviour of component 'mux_768' model 'mux' + mux_768 <= + (repeat(32, sig_1436) and sig_1610(31 downto 0)); + + -- Behaviour of component 'mux_757' model 'mux' + mux_757 <= + (repeat(8, sig_1057) and sig_1646) or + (repeat(8, sig_1062) and outdata_image_height); + + -- Behaviour of component 'mux_773' model 'mux' + mux_773 <= + (repeat(8, sig_1179) and outdata_image_height) or + (repeat(8, sig_1180) and outdata_image_width) or + (repeat(8, sig_1181) and write8_u8); + + -- Behaviour of component 'mux_762' model 'mux' + mux_762 <= + (repeat(32, sig_1118) and chenidct_a3) or + (repeat(32, sig_1217) and yuvtorgb_v) or + (repeat(32, sig_1324) and chenidct_a1); + + -- Behaviour of component 'mux_766' model 'mux' + mux_766 <= + (repeat(32, sig_1436) and sig_1609(31 downto 0)); + + -- Behaviour of component 'mux_781' model 'mux' + mux_781 <= + (repeat(32, sig_1608) and sig_1657) or + (repeat(32, sig_1607) and "000000000000000000000000" & read_byte); + + -- Behaviour of component 'mux_797' model 'mux' + mux_797 <= + (repeat(32, sig_1617) and mux_798); + + -- Behaviour of component 'mux_821' model 'mux' + mux_821 <= + (repeat(32, sig_1617) and mux_822); + + -- Behaviour of component 'mux_826' model 'mux' + mux_826 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_778' model 'mux' + mux_778 <= + (repeat(32, sig_1607) and sig_1659) or + (repeat(32, sig_1608) and "000000000000000000000000" & read_byte); + + -- Behaviour of component 'mux_827' model 'mux' + mux_827 <= + (repeat(32, sig_1617) and mux_828); + + -- Behaviour of component 'mux_815' model 'mux' + mux_815 <= + (repeat(32, sig_1617) and mux_816); + + -- Behaviour of component 'mux_798' model 'mux' + mux_798 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_816' model 'mux' + mux_816 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_817' model 'mux' + mux_817 <= + (repeat(32, sig_1617) and mux_818); + + -- Behaviour of component 'mux_777' model 'mux' + mux_777 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_819' model 'mux' + mux_819 <= + (repeat(32, sig_1617) and mux_820); + + -- Behaviour of component 'mux_783' model 'mux' + mux_783 <= + (repeat(32, sig_1608) and sig_1658) or + (repeat(32, sig_1607) and "000000000000000000000000" & read_byte); + + -- Behaviour of component 'mux_795' model 'mux' + mux_795 <= + (repeat(32, sig_1617) and mux_796); + + -- Behaviour of component 'mux_796' model 'mux' + mux_796 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_805' model 'mux' + mux_805 <= + (repeat(32, sig_1617) and mux_806); + + -- Behaviour of component 'mux_806' model 'mux' + mux_806 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_807' model 'mux' + mux_807 <= + (repeat(32, sig_1617) and mux_808); + + -- Behaviour of component 'mux_808' model 'mux' + mux_808 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_809' model 'mux' + mux_809 <= + (repeat(32, sig_1617) and mux_810); + + -- Behaviour of component 'mux_810' model 'mux' + mux_810 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_811' model 'mux' + mux_811 <= + (repeat(32, sig_1617) and mux_812); + + -- Behaviour of component 'mux_812' model 'mux' + mux_812 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_813' model 'mux' + mux_813 <= + (repeat(32, sig_1617) and mux_814); + + -- Behaviour of component 'mux_814' model 'mux' + mux_814 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_818' model 'mux' + mux_818 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_828' model 'mux' + mux_828 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_829' model 'mux' + mux_829 <= + (repeat(32, sig_1617) and mux_830); + + -- Behaviour of component 'mux_830' model 'mux' + mux_830 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_831' model 'mux' + mux_831 <= + (repeat(32, sig_1617) and mux_832); + + -- Behaviour of component 'mux_832' model 'mux' + mux_832 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_836' model 'mux' + mux_836 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_837' model 'mux' + mux_837 <= + (repeat(32, sig_1617) and mux_838); + + -- Behaviour of component 'mux_839' model 'mux' + mux_839 <= + (repeat(32, sig_1617) and mux_840); + + -- Behaviour of component 'mux_840' model 'mux' + mux_840 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_841' model 'mux' + mux_841 <= + (repeat(32, sig_1617) and mux_842); + + -- Behaviour of component 'mux_842' model 'mux' + mux_842 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_843' model 'mux' + mux_843 <= + (repeat(32, sig_1617) and mux_844); + + -- Behaviour of component 'mux_856' model 'mux' + mux_856 <= + (repeat(32, sig_1617) and mux_857); + + -- Behaviour of component 'and_864' model 'and' + and_864 <= + sig_1603 and + sig_1624(16); + + -- Behaviour of component 'mux_870' model 'mux' + mux_870 <= + (repeat(32, sig_1599) and get_dqt_length) or + (repeat(32, sig_1669) and sig_1614(31 downto 0)); + + -- Behaviour of component 'mux_872' model 'mux' + mux_872 <= + (repeat(2, sig_1598) and "10"); + + -- Behaviour of component 'mux_875' model 'mux' + mux_875 <= + (repeat(32, sig_1616) and sig_1647); + + -- Behaviour of component 'mux_891' model 'mux' + mux_891 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_892' model 'mux' + mux_892 <= + (repeat(32, sig_1617) and mux_893); + + -- Behaviour of component 'mux_893' model 'mux' + mux_893 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_894' model 'mux' + mux_894 <= + (repeat(32, sig_1617) and mux_895); + + -- Behaviour of component 'mux_895' model 'mux' + mux_895 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_896' model 'mux' + mux_896 <= + (repeat(32, sig_1623) and sig_1648) or + (repeat(32, sig_1616) and sig_1624(31 downto 0)); + + -- Behaviour of component 'mux_897' model 'mux' + mux_897 <= + (repeat(32, sig_1616) and sig_1647); + + -- Behaviour of component 'mux_898' model 'mux' + mux_898 <= + (repeat(32, sig_1617) and mux_899); + + -- Behaviour of component 'mux_899' model 'mux' + mux_899 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_900' model 'mux' + mux_900 <= + (repeat(32, sig_1617) and mux_901); + + -- Behaviour of component 'mux_901' model 'mux' + mux_901 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_902' model 'mux' + mux_902 <= + (repeat(32, sig_1617) and mux_903); + + -- Behaviour of component 'mux_903' model 'mux' + mux_903 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_904' model 'mux' + mux_904 <= + (repeat(32, sig_1617) and mux_905); + + -- Behaviour of component 'mux_905' model 'mux' + mux_905 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_906' model 'mux' + mux_906 <= + (repeat(32, sig_1617) and mux_907); + + -- Behaviour of component 'mux_907' model 'mux' + mux_907 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_908' model 'mux' + mux_908 <= + (repeat(32, sig_1617) and mux_909); + + -- Behaviour of component 'mux_917' model 'mux' + mux_917 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_918' model 'mux' + mux_918 <= + (repeat(32, sig_1617) and mux_919); + + -- Behaviour of component 'mux_924' model 'mux' + mux_924 <= + (repeat(32, sig_1617) and mux_925); + + -- Behaviour of component 'mux_925' model 'mux' + mux_925 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_928' model 'mux' + mux_928 <= + (repeat(32, sig_1617) and mux_929); + + -- Behaviour of component 'mux_929' model 'mux' + mux_929 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_931' model 'mux' + mux_931 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_932' model 'mux' + mux_932 <= + (repeat(32, sig_1617) and mux_933); + + -- Behaviour of component 'mux_934' model 'mux' + mux_934 <= + (repeat(32, sig_1617) and mux_935); + + -- Behaviour of component 'mux_935' model 'mux' + mux_935 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_936' model 'mux' + mux_936 <= + (repeat(32, sig_1617) and mux_937); + + -- Behaviour of component 'mux_937' model 'mux' + mux_937 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_938' model 'mux' + mux_938 <= + (repeat(32, sig_1617) and mux_939); + + -- Behaviour of component 'mux_939' model 'mux' + mux_939 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_941' model 'mux' + mux_941 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_944' model 'mux' + mux_944 <= + (repeat(32, sig_1617) and mux_945); + + -- Behaviour of component 'mux_945' model 'mux' + mux_945 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_946' model 'mux' + mux_946 <= + (repeat(32, sig_1617) and mux_947); + + -- Behaviour of component 'mux_833' model 'mux' + mux_833 <= + (repeat(32, sig_1617) and mux_834); + + -- Behaviour of component 'mux_834' model 'mux' + mux_834 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_835' model 'mux' + mux_835 <= + (repeat(32, sig_1617) and mux_836); + + -- Behaviour of component 'mux_838' model 'mux' + mux_838 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_844' model 'mux' + mux_844 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_857' model 'mux' + mux_857 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_858' model 'mux' + mux_858 <= + (repeat(32, sig_1617) and mux_859); + + -- Behaviour of component 'mux_859' model 'mux' + mux_859 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_874' model 'mux' + mux_874 <= + (repeat(32, sig_1623) and sig_1648) or + (repeat(32, sig_1616) and sig_1624(31 downto 0)); + + -- Behaviour of component 'mux_888' model 'mux' + mux_888 <= + (repeat(32, sig_1617) and mux_889); + + -- Behaviour of component 'mux_889' model 'mux' + mux_889 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_913' model 'mux' + mux_913 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_914' model 'mux' + mux_914 <= + (repeat(32, sig_1617) and mux_915); + + -- Behaviour of component 'mux_915' model 'mux' + mux_915 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_916' model 'mux' + mux_916 <= + (repeat(32, sig_1617) and mux_917); + + -- Behaviour of component 'mux_933' model 'mux' + mux_933 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_940' model 'mux' + mux_940 <= + (repeat(32, sig_1617) and mux_941); + + -- Behaviour of component 'mux_942' model 'mux' + mux_942 <= + (repeat(32, sig_1617) and mux_943); + + -- Behaviour of component 'and_867' model 'and' + and_867 <= + sig_1670 and + sig_1594; + + -- Behaviour of component 'mux_909' model 'mux' + mux_909 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_910' model 'mux' + mux_910 <= + (repeat(32, sig_1617) and mux_911); + + -- Behaviour of component 'mux_911' model 'mux' + mux_911 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_920' model 'mux' + mux_920 <= + (repeat(32, sig_1617) and mux_921); + + -- Behaviour of component 'mux_921' model 'mux' + mux_921 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_926' model 'mux' + mux_926 <= + (repeat(32, sig_1617) and mux_927); + + -- Behaviour of component 'mux_927' model 'mux' + mux_927 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_943' model 'mux' + mux_943 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_886' model 'mux' + mux_886 <= + (sig_1601 and read_byte(0)) or + (sig_1602 and read_byte(0)); + + -- Behaviour of component 'mux_922' model 'mux' + mux_922 <= + (repeat(32, sig_1617) and mux_923); + + -- Behaviour of component 'mux_923' model 'mux' + mux_923 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_930' model 'mux' + mux_930 <= + (repeat(32, sig_1617) and mux_931); + + -- Behaviour of component 'mux_987' model 'mux' + mux_987 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'and_860' model 'and' + and_860 <= + sig_1637 and + buf_getv; + + -- Behaviour of component 'and_881' model 'and' + and_881 <= + sig_1637 and + sig_1643; + + -- Behaviour of component 'and_884' model 'and' + and_884 <= + "00000000000000000000000000010000" and + "000000000000000000000000" & read_byte; + + -- Behaviour of component 'mux_890' model 'mux' + mux_890 <= + (repeat(32, sig_1617) and mux_891); + + -- Behaviour of component 'mux_912' model 'mux' + mux_912 <= + (repeat(32, sig_1617) and mux_913); + + -- Behaviour of component 'mux_919' model 'mux' + mux_919 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_948' model 'mux' + mux_948 <= + (repeat(32, sig_1617) and mux_949); + + -- Behaviour of component 'mux_949' model 'mux' + mux_949 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_950' model 'mux' + mux_950 <= + (repeat(32, sig_1617) and mux_951); + + -- Behaviour of component 'and_862' model 'and' + and_862 <= + sig_1595 and + sig_1614(16); + + -- Behaviour of component 'mux_953' model 'mux' + mux_953 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_954' model 'mux' + mux_954 <= + (repeat(32, sig_1617) and mux_955); + + -- Behaviour of component 'mux_955' model 'mux' + mux_955 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_951' model 'mux' + mux_951 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_952' model 'mux' + mux_952 <= + (repeat(32, sig_1617) and mux_953); + + -- Behaviour of component 'mux_959' model 'mux' + mux_959 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_960' model 'mux' + mux_960 <= + (repeat(32, sig_1617) and mux_961); + + -- Behaviour of component 'mux_961' model 'mux' + mux_961 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_965' model 'mux' + mux_965 <= + (repeat(32, sig_1617) and mux_966); + + -- Behaviour of component 'mux_966' model 'mux' + mux_966 <= + (repeat(32, sig_1622) and yuvtorgb_r) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'and_876' model 'and' + and_876 <= + "00001111" and + "0000" & read_byte(7 downto 4); + + -- Behaviour of component 'mux_956' model 'mux' + mux_956 <= + (repeat(32, sig_1617) and mux_957); + + -- Behaviour of component 'mux_957' model 'mux' + mux_957 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_947' model 'mux' + mux_947 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_968' model 'mux' + mux_968 <= + (repeat(32, sig_1593) and yuvtorgb_b) or + (repeat(32, sig_1591) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_969' model 'mux' + mux_969 <= + (repeat(32, sig_1597) and mux_970); + + -- Behaviour of component 'mux_970' model 'mux' + mux_970 <= + (repeat(32, sig_1586) and yuvtorgb_g) or + (repeat(32, sig_1589) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_980' model 'mux' + mux_980 <= + (repeat(32, sig_1617) and mux_981); + + -- Behaviour of component 'mux_981' model 'mux' + mux_981 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of component 'mux_958' model 'mux' + mux_958 <= + (repeat(32, sig_1617) and mux_959); + + -- Behaviour of component 'and_963' model 'and' + and_963 <= + sig_1615 and + sig_991; + + -- Behaviour of component 'mux_986' model 'mux' + mux_986 <= + (repeat(32, sig_1617) and mux_987); + + -- Behaviour of component 'mux_988' model 'mux' + mux_988 <= + (repeat(32, sig_1617) and mux_989); + + -- Behaviour of component 'mux_989' model 'mux' + mux_989 <= + (repeat(32, sig_1622) and sig_1642) or + (repeat(32, sig_1625) and "00000000000000000000000011111111"); + + -- Behaviour of all components of model 'reg' + -- Registers with clock = sig_clock and no reset + process(sig_clock) + begin + if rising_edge(sig_clock) then + if sig_1437 = '1' then + izigzagmatrix_i <= mux_768; + end if; + if sig_1437 = '1' then + izigzagmatrix_out_idx <= mux_766; + end if; + if sig_1072 = '1' then + iquantize_qidx <= sig_1610(1 downto 0); + end if; + if sig_1061 = '1' then + write8_u8 <= mux_757; + end if; + if sig_1206 = '1' then + p_jinfo_image_height <= read_word; + end if; + if sig_1207 = '1' then + p_jinfo_image_width <= read_word; + end if; + if sig_1204 = '1' then + p_jinfo_num_components <= read_byte; + end if; + if sig_1219 = '1' then + p_jinfo_smp_fact <= mux_872; + end if; + if sig_1307 = '1' then + p_jinfo_mcuwidth <= sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17) & sig_1612(17 downto 0); + end if; + if sig_1307 = '1' then + p_jinfo_mcuheight <= sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17) & sig_1609(17 downto 0); + end if; + if sig_1100 = '1' then + p_jinfo_nummcu <= sig_1628(31 downto 0); + end if; + if sig_1273 = '1' then + i_jinfo_jpeg_data <= readbuf_idx; + end if; + if sig_1583 = '1' then + curhuffreadbuf_idx <= mux_671; + end if; + if sig_1042 = '1' then + outdata_image_width <= p_jinfo_image_width(7 downto 0); + end if; + if sig_1042 = '1' then + outdata_image_height <= p_jinfo_image_height(7 downto 0); + end if; + if sig_1340 = '1' then + readbuf_idx <= mux_648; + end if; + if sig_1053 = '1' then + read_byte <= sig_1644; + end if; + if sig_1249 = '1' then + read_word <= read_word_c & sig_1644; + end if; + if sig_1248 = '1' then + read_word_c <= sig_1644; + end if; + if sig_1205 = '1' then + next_marker <= next_marker_c; + end if; + if sig_1203 = '1' then + next_marker_c <= read_byte; + end if; + if sig_1210 = '1' then + get_sof_ci <= mux_633; + end if; + if sig_1208 = '1' then + get_sof_i_comp_info_id <= get_sof_ci(1 downto 0); + end if; + if sig_1208 = '1' then + get_sof_i_comp_info_h_samp_factor <= get_sof_ci(1 downto 0); + end if; + if sig_1208 = '1' then + get_sof_i_comp_info_quant_tbl_no <= get_sof_ci(1 downto 0); + end if; + if sig_1224 = '1' then + get_sos_num_comp <= read_byte; + end if; + if sig_1250 = '1' then + get_sos_i <= mux_622; + end if; + if sig_1272 = '1' then + get_sos_c <= read_byte(4); + end if; + if sig_1242 = '1' then + get_sos_cc <= read_byte; + end if; + if sig_1253 = '1' then + get_sos_ci <= mux_616; + end if; + if sig_1286 = '1' then + get_sos_j <= mux_614; + end if; + if sig_1243 = '1' then + get_sos_i_comp_info_dc_tbl_no <= get_sos_ci(1 downto 0); + end if; + if sig_1312 = '1' then + get_dht_length <= sig_1614(31 downto 0); + end if; + if sig_1199 = '1' then + get_dht_index <= mux_886; + end if; + if sig_1541 = '1' then + get_dht_i <= mux_602; + end if; + if sig_1456 = '1' then + get_dht_count <= mux_600; + end if; + if sig_1199 = '1' then + get_dht_is_ac <= sig_1602; + end if; + if sig_1316 = '1' then + get_dqt_length <= mux_593; + end if; + if sig_1302 = '1' then + get_dqt_prec <= read_byte(7 downto 4); + end if; + if sig_1302 = '1' then + get_dqt_num <= read_byte(1 downto 0); + end if; + if sig_1333 = '1' then + get_dqt_i <= mux_587; + end if; + if sig_1338 = '1' then + get_dqt_tmp <= mux_585; + end if; + if sig_1347 = '1' then + read_markers_unread_marker <= mux_580; + end if; + if sig_1352 = '1' then + read_markers_sow_soi <= sig_1353; + end if; + if sig_1447 = '1' then + chenidct_i <= mux_555; + end if; + if sig_1476 = '1' then + chenidct_aidx <= mux_553; + end if; + if sig_1462 = '1' then + chenidct_a0 <= mux_551; + end if; + if sig_1439 = '1' then + chenidct_a1 <= mux_549; + end if; + if sig_1584 = '1' then + chenidct_a2 <= mux_547; + end if; + if sig_1465 = '1' then + chenidct_a3 <= mux_545; + end if; + if sig_1459 = '1' then + chenidct_b0 <= mux_543; + end if; + if sig_1356 = '1' then + chenidct_b1 <= mux_541; + end if; + if sig_1478 = '1' then + chenidct_b2 <= mux_539; + end if; + if sig_1460 = '1' then + chenidct_b3 <= mux_537; + end if; + if sig_1461 = '1' then + chenidct_c0 <= mux_535; + end if; + if sig_1394 = '1' then + chenidct_c1 <= mux_533; + end if; + if sig_1394 = '1' then + chenidct_c2 <= mux_531; + end if; + if sig_1461 = '1' then + chenidct_c3 <= mux_529; + end if; + if sig_1494 = '1' then + current_read_byte <= mux_521; + end if; + if sig_1424 = '1' then + pgetc <= mux_517; + end if; + if sig_1442 = '1' then + pgetc_temp <= sig_1644; + end if; + if sig_1483 = '1' then + buf_getb <= sig_1481; + end if; + if sig_1495 = '1' then + buf_getv <= mux_507; + end if; + if sig_1200 = '1' then + buf_getv_n <= mux_505; + end if; + if sig_1490 = '1' then + buf_getv_p <= sig_1614(31 downto 0); + end if; + if sig_1488 = '1' then + buf_getv_rv <= mux_501; + end if; + if sig_1521 = '1' then + huff_make_dhuff_tb_ac <= huff_make_dhuff_tb_ac_p_dhtbl_ml; + end if; + if sig_1187 = '1' then + huff_make_dhuff_tb_ac_tbl_no <= sig_1184; + end if; + if sig_1543 = '1' then + huff_make_dhuff_tb_ac_p_dhtbl_ml <= mux_492; + end if; + if sig_1506 = '1' then + huff_make_dhuff_tb_ac_i_c0 <= mux_490; + end if; + if sig_1503 = '1' then + huff_make_dhuff_tb_ac_j <= mux_488; + end if; + if sig_1545 = '1' then + huff_make_dhuff_tb_ac_p <= mux_486; + end if; + if sig_1282 = '1' then + huff_make_dhuff_tb_ac_code <= mux_484; + end if; + if sig_1557 = '1' then + huff_make_dhuff_tb_ac_size <= mux_482; + end if; + if sig_1524 = '1' then + huff_make_dhuff_tb_ac_l <= mux_480; + end if; + if sig_1559 = '1' then + huff_make_dhuff_tb_dc <= huff_make_dhuff_tb_dc_p_dhtbl_ml; + end if; + if sig_1306 = '1' then + huff_make_dhuff_tb_dc_tbl_no <= sig_1189; + end if; + if sig_1539 = '1' then + huff_make_dhuff_tb_dc_p_dhtbl_ml <= mux_459; + end if; + if sig_1535 = '1' then + huff_make_dhuff_tb_dc_i_c0 <= mux_457; + end if; + if sig_1532 = '1' then + huff_make_dhuff_tb_dc_j <= mux_455; + end if; + if sig_1538 = '1' then + huff_make_dhuff_tb_dc_p <= mux_453; + end if; + if sig_1067 = '1' then + huff_make_dhuff_tb_dc_code <= mux_451; + end if; + if sig_1069 = '1' then + huff_make_dhuff_tb_dc_size <= mux_449; + end if; + if sig_1562 = '1' then + huff_make_dhuff_tb_dc_l <= mux_447; + end if; + if sig_1572 = '1' then + decodehuffman_ac <= mux_430; + end if; + if sig_1452 = '1' then + decodehuffman_ac_tbl_no <= decodehuffmcu_tbl_no; + end if; + if sig_1452 = '1' then + decodehuffman_ac_dhuff_ml <= sig_1652(5 downto 0); + end if; + if sig_1566 = '1' then + decodehuffman_ac_code <= mux_424; + end if; + if sig_1566 = '1' then + decodehuffman_ac_l <= mux_422; + end if; + if sig_1288 = '1' then + decodehuffman_ac_p <= sig_1614(8 downto 0); + end if; + if sig_1580 = '1' then + decodehuffman_dc <= mux_416; + end if; + if sig_1509 = '1' then + decodehuffman_dc_tbl_no <= sig_1662; + end if; + if sig_1169 = '1' then + decodehuffman_dc_dhuff_ml <= sig_1656(5 downto 0); + end if; + if sig_1573 = '1' then + decodehuffman_dc_code <= mux_410; + end if; + if sig_1573 = '1' then + decodehuffman_dc_l <= mux_408; + end if; + if sig_1290 = '1' then + decodehuffman_dc_p <= sig_1614(8 downto 0); + end if; + if sig_1509 = '1' then + decodehuffmcu_bufdim1 <= decode_block_in_buf_idx; + end if; + if sig_1578 = '1' then + decodehuffmcu_s <= mux_400; + end if; + if sig_1343 = '1' then + decodehuffmcu_diff <= mux_398; + end if; + if sig_1509 = '1' then + decodehuffmcu_tbl_no <= sig_1662; + end if; + if sig_1444 = '1' then + decodehuffmcu_i <= mux_394; + end if; + if sig_1467 = '1' then + decodehuffmcu_k <= mux_392; + end if; + if sig_1029 = '1' then + decodehuffmcu_n <= and_983; + end if; + if sig_1195 = '1' then + writeoneblock_outidx <= mux_375; + end if; + if sig_1195 = '1' then + writeoneblock_indim1 <= mux_373; + end if; + if sig_1195 = '1' then + writeoneblock_width <= p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width(15) & p_jinfo_image_width; + end if; + if sig_1195 = '1' then + writeoneblock_height <= p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height(15) & p_jinfo_image_height; + end if; + if sig_1195 = '1' then + writeoneblock_voffs <= mux_367; + end if; + if sig_1195 = '1' then + writeoneblock_hoffs <= mux_365; + end if; + if sig_1064 = '1' then + writeoneblock_i <= mux_363; + end if; + if sig_1080 = '1' then + writeoneblock_e <= mux_361; + end if; + if sig_1066 = '1' then + writeoneblock_inidx <= mux_359; + end if; + if sig_1082 = '1' then + writeoneblock_diff <= sig_1628(12 downto 0); + end if; + if sig_996 = '1' then + writeblock_i <= decode_start_i(1 downto 0); + end if; + if sig_1191 = '1' then + write4blocks_i <= decode_start_i(1 downto 0); + end if; + if sig_1193 = '1' then + write4blocks_voffs <= mux_347; + end if; + if sig_1192 = '1' then + write4blocks_hoffs <= mux_345; + end if; + if sig_998 = '1' then + yuvtorgb_p <= mux_343; + end if; + if sig_998 = '1' then + yuvtorgb_yidx <= mux_341; + end if; + if sig_998 = '1' then + yuvtorgb_uidx <= mux_339; + end if; + if sig_998 = '1' then + yuvtorgb_vidx <= mux_337; + end if; + if sig_1218 = '1' then + yuvtorgb_r <= mux_335; + end if; + if sig_1218 = '1' then + yuvtorgb_g <= mux_333; + end if; + if sig_1218 = '1' then + yuvtorgb_b <= mux_331; + end if; + if sig_1298 = '1' then + yuvtorgb_y <= sig_1642(23 downto 0); + end if; + if sig_1298 = '1' then + yuvtorgb_u <= sig_1624(30 downto 0); + end if; + if sig_1298 = '1' then + yuvtorgb_v <= sig_1614(31 downto 0); + end if; + if sig_1233 = '1' then + yuvtorgb_i <= mux_320; + end if; + if sig_1044 = '1' then + decode_block_comp_no <= mux_317; + end if; + if sig_1044 = '1' then + decode_block_out_buf_idx <= mux_308; + end if; + if sig_1044 = '1' then + decode_block_in_buf_idx <= mux_294; + end if; + if sig_1430 = '1' then + decode_start_i <= mux_292; + end if; + if sig_1182 = '1' then + decode_start_currentmcu <= mux_286; + end if; + if sig_1055 = '1' then + jpeg2bmp_main_i <= mux_262; + end if; + if sig_1058 = '1' then + jpeg2bmp_main_j <= mux_257; + end if; + if sig_1178 = '1' then + read8_ret0_195 <= stdin_data; + end if; + end if; + end process; + -- Registers with clock = sig_clock and reset = sig_reset active '1' + process(sig_clock, sig_reset) + begin + if sig_reset = '1' then + read_position <= "11111111111111111111111111111111"; + else + if rising_edge(sig_clock) then + if sig_1496 = '1' then + read_position <= mux_519; + end if; + end if; + end if; + end process; + + -- Remaining signal assignments + -- Those who are not assigned by component instantiation + + sig_clock <= clock; + sig_reset <= reset; + augh_test_159 <= sig_1615; + augh_test_26 <= sig_1616; + augh_test_49 <= sig_1616; + augh_test_52 <= sig_1616; + augh_test_53 <= and_867; + augh_test_67 <= sig_1618; + augh_test_72 <= sig_1615; + augh_test_77 <= sig_1616; + augh_test_83 <= sig_1618; + augh_test_89 <= sig_1615; + augh_test_90 <= sig_1669; + augh_test_105 <= sig_1615; + augh_test_106 <= sig_1615; + augh_test_107 <= sig_1615; + augh_test_111 <= sig_1616; + augh_test_114 <= sig_1618; + augh_test_115 <= sig_1618; + augh_test_119 <= sig_1615; + augh_test_120 <= sig_1615; + augh_test_122 <= and_963; + augh_test_125 <= sig_1615; + augh_test_127 <= sig_1615; + augh_test_128 <= sig_1615; + augh_test_130 <= and_976; + augh_test_133 <= sig_1615; + augh_test_136 <= sig_1618; + augh_test_138 <= sig_1616; + augh_test_142 <= sig_1618; + augh_test_144 <= sig_1616; + augh_test_151 <= sig_1615; + augh_test_152 <= sig_1615; + augh_test_155 <= sig_1618; + augh_test_165 <= sig_1616; + augh_test_166 <= sig_1616; + augh_test_167 <= sig_1616; + augh_test_168 <= sig_1616; + sig_start <= start; + augh_test_171 <= sig_1615; + augh_test_178 <= sig_1615; + augh_test_179 <= sig_1615; + augh_test_182 <= sig_1616; + augh_test_183 <= sig_1615; + augh_test_184 <= sig_1615; + augh_test_186 <= sig_1616; + augh_test_187 <= sig_1615; + augh_test_188 <= sig_1615; + augh_test_189 <= sig_1615; + sig_1671 <= "000000000000000000000000" & pgetc_temp; + sig_1672 <= "000000000000000000000000000000" & p_jinfo_smp_fact; + sig_1673 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g; + sig_1674 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g; + sig_1675 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b; + sig_1676 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b; + sig_1677 <= "000000000000000000000000" & next_marker_c; + sig_1678 <= "000000000000000000000000" & pgetc_temp; + sig_1679 <= yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g(31) & yuvtorgb_g; + sig_1680 <= "000000000000000000000000" & read_byte; + sig_1681 <= "000000000000000000000000" & next_marker_c; + sig_1682 <= "0000000000000000000000000000" & get_dqt_prec; + sig_1683 <= "000000000000000000000000" & read_markers_unread_marker; + sig_1684 <= "000000000000000000000000" & read_markers_unread_marker; + sig_1685 <= "0000000000000000000000000000000" & get_dht_is_ac; + sig_1686 <= "0000000000000000000000000000000" & get_dht_is_ac; + sig_1687 <= "0000" & decodehuffmcu_n; + sig_1688 <= sig_1612(23 downto 0) & sig_1667(7); + sig_1689 <= yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b(31) & yuvtorgb_b; + sig_1690 <= "00000000000000000000000" & mux_313; + sig_1691 <= writeoneblock_indim1 & writeoneblock_outidx & writeoneblock_inidx(5 downto 0); + sig_1692 <= yuvtorgb_uidx & yuvtorgb_i(5 downto 0); + sig_1693 <= jpeg2bmp_main_i(1 downto 0) & jpeg2bmp_main_j(12 downto 0); + sig_1694 <= writeoneblock_outidx & sig_1610(12 downto 0); + sig_1695 <= decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0); + sig_1696 <= huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0); + sig_1697 <= decodehuffman_ac_tbl_no & decodehuffman_ac_l(5 downto 0); + sig_1698 <= huff_make_dhuff_tb_ac_tbl_no & huff_make_dhuff_tb_ac_l(5 downto 0); + sig_1699 <= decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0); + sig_1700 <= huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0); + sig_1701 <= decodehuffman_dc_tbl_no & decodehuffman_dc_l(5 downto 0); + sig_1702 <= huff_make_dhuff_tb_dc_tbl_no & huff_make_dhuff_tb_dc_l(5 downto 0); + sig_1703 <= get_dht_index & get_dht_i(8 downto 0); + sig_1704 <= get_dht_index & get_dht_i(5 downto 0); + sig_1705 <= get_dht_index & get_dht_i(8 downto 0); + sig_1706 <= get_dht_index & get_dht_i(5 downto 0); + sig_1707 <= sig_1610(1 downto 0) & sig_1645; + sig_1708 <= "0000000000000000" & get_dqt_tmp; + sig_1709 <= "000000000000000000000000" & read_markers_unread_marker; + sig_1710 <= "000000000000000000000000" & read_markers_unread_marker; + sig_1711 <= "000000000000000000000000" & read_markers_unread_marker; + sig_1712 <= "00000000000000000000000011" & mux_759; + sig_1713 <= "00000000000000000000000" & mux_761; + sig_1714 <= "0000000000000000000000000000000" & read_markers_sow_soi; + sig_1715 <= "0000000000000000000000000000" & get_dqt_prec; + sig_1716 <= "000000000000000000000000" & read_markers_unread_marker; + + -- Remaining top-level ports assignments + -- Those who are not assigned by component instantiation + + stdout_data <= mux_773; + stdin_rdy <= sig_1178; + +end architecture; diff --git a/testsuite/gna/bug040/zigzag_index.vhd b/testsuite/gna/bug040/zigzag_index.vhd new file mode 100644 index 000000000..3426fe6cb --- /dev/null +++ b/testsuite/gna/bug040/zigzag_index.vhd @@ -0,0 +1,55 @@ +library ieee; +use ieee.std_logic_1164.all; + + +library ieee; +use ieee.numeric_std.all; + +entity zigzag_index is + port ( + clk : in std_logic; + ra0_addr : in std_logic_vector(5 downto 0); + ra0_data : out std_logic_vector(5 downto 0) + ); +end zigzag_index; +architecture augh of zigzag_index is + + -- Embedded RAM + + type ram_type is array (0 to 63) of std_logic_vector(5 downto 0); + signal ram : ram_type := ( + "000000", "000001", "000101", "000110", "001110", "001111", "011011", "011100", "000010", "000100", "000111", "001101", + "010000", "011010", "011101", "101010", "000011", "001000", "001100", "010001", "011001", "011110", "101001", "101011", + "001001", "001011", "010010", "011000", "011111", "101000", "101100", "110101", "001010", "010011", "010111", "100000", + "100111", "101101", "110100", "110110", "010100", "010110", "100001", "100110", "101110", "110011", "110111", "111100", + "010101", "100010", "100101", "101111", "110010", "111000", "111011", "111101", "100011", "100100", "110000", "110001", + "111001", "111010", "111110", "111111" + ); + + + -- Little utility functions to make VHDL syntactically correct + -- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic. + -- This happens when accessing arrays with <= 2 cells, for example. + + function to_integer(B: std_logic) return integer is + variable V: std_logic_vector(0 to 0); + begin + V(0) := B; + return to_integer(unsigned(V)); + end; + + function to_integer(V: std_logic_vector) return integer is + begin + return to_integer(unsigned(V)); + end; + +begin + + -- The component is a ROM. + -- There is no Write side. + + -- The Read side (the outputs) + + ra0_data <= ram( to_integer(ra0_addr) ); + +end architecture; |