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authorTristan Gingold <tgingold@free.fr>2021-08-29 07:31:45 +0200
committerTristan Gingold <tgingold@free.fr>2021-08-29 11:50:18 +0200
commitf1d4115c862659824a9ebb645bae01b5d1fa2866 (patch)
treebc7c1eddb359b30965b11288e9d5771bece78d3d /testsuite
parentf6451e539e5205105d2356c30a638e29305a493e (diff)
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testsuite/gna: add a test for Wuseless warning. For #1832
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/gna/issue1832/psl.vhdl21
-rwxr-xr-xtestsuite/gna/issue1832/testsuite.sh5
2 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/gna/issue1832/psl.vhdl b/testsuite/gna/issue1832/psl.vhdl
new file mode 100644
index 000000000..4d005d5ef
--- /dev/null
+++ b/testsuite/gna/issue1832/psl.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+ use ieee.std_logic_1164.all;
+
+
+entity issue is
+ port (
+ clk : in std_logic;
+ a, b : in std_logic
+ );
+end entity issue;
+
+
+architecture psl of issue is
+begin
+
+ -- All is sensitive to rising edge of clk
+ default clock is rising_edge(clk);
+
+ -- This assertion should hold
+ INF_a : assert always {a} |=> {not b[*0 to inf]; b};
+end architecture psl;
diff --git a/testsuite/gna/issue1832/testsuite.sh b/testsuite/gna/issue1832/testsuite.sh
index 197a21ff9..458947150 100755
--- a/testsuite/gna/issue1832/testsuite.sh
+++ b/testsuite/gna/issue1832/testsuite.sh
@@ -3,6 +3,11 @@
. ../../testenv.sh
export GHDL_STD_FLAGS=--std=08
+analyze_failure -Werror psl.vhdl
+analyze psl.vhdl
+
+clean
+
analyze issue.vhdl
elab_simulate issue