From f1d4115c862659824a9ebb645bae01b5d1fa2866 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Sun, 29 Aug 2021 07:31:45 +0200
Subject: testsuite/gna: add a test for Wuseless warning.  For #1832

---
 testsuite/gna/issue1832/psl.vhdl     | 21 +++++++++++++++++++++
 testsuite/gna/issue1832/testsuite.sh |  5 +++++
 2 files changed, 26 insertions(+)
 create mode 100644 testsuite/gna/issue1832/psl.vhdl

(limited to 'testsuite')

diff --git a/testsuite/gna/issue1832/psl.vhdl b/testsuite/gna/issue1832/psl.vhdl
new file mode 100644
index 000000000..4d005d5ef
--- /dev/null
+++ b/testsuite/gna/issue1832/psl.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+entity issue is
+  port (
+    clk : in std_logic;
+    a, b : in std_logic
+  );
+end entity issue;
+
+
+architecture psl of issue is
+begin
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion should hold
+  INF_a : assert always {a} |=> {not b[*0 to inf]; b};
+end architecture psl;
diff --git a/testsuite/gna/issue1832/testsuite.sh b/testsuite/gna/issue1832/testsuite.sh
index 197a21ff9..458947150 100755
--- a/testsuite/gna/issue1832/testsuite.sh
+++ b/testsuite/gna/issue1832/testsuite.sh
@@ -3,6 +3,11 @@
 . ../../testenv.sh
 
 export GHDL_STD_FLAGS=--std=08
+analyze_failure -Werror psl.vhdl
+analyze psl.vhdl
+
+clean
+
 analyze issue.vhdl
 elab_simulate issue
 
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