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Diffstat (limited to 'testsuite/gna/issue1832/psl.vhdl')
-rw-r--r-- | testsuite/gna/issue1832/psl.vhdl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/gna/issue1832/psl.vhdl b/testsuite/gna/issue1832/psl.vhdl new file mode 100644 index 000000000..4d005d5ef --- /dev/null +++ b/testsuite/gna/issue1832/psl.vhdl @@ -0,0 +1,21 @@ +library ieee; + use ieee.std_logic_1164.all; + + +entity issue is + port ( + clk : in std_logic; + a, b : in std_logic + ); +end entity issue; + + +architecture psl of issue is +begin + + -- All is sensitive to rising edge of clk + default clock is rising_edge(clk); + + -- This assertion should hold + INF_a : assert always {a} |=> {not b[*0 to inf]; b}; +end architecture psl; |