testsuite/synth: add more tests for subtraction in std_logic_unsigned

9 files changed, 163 insertions, 0 deletions

diff --git a/testsuite/synth/issue1951/sub01.vhdl b/testsuite/synth/issue1951/sub01.vhdl
new file mode 100644
index 000000000..3b09d23dc
--- /dev/null
+++ b/testsuite/synth/issue1951/sub01.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity sub01 is
+  port (i : std_logic_vector (3 downto 0);
+        o : out std_logic_vector (3 downto 0));
+end entity;
+
+architecture arch of sub01 is
+begin
+  o <= i - (-1);
+end arch;
diff --git a/testsuite/synth/issue1951/sub02.vhdl b/testsuite/synth/issue1951/sub02.vhdl
new file mode 100644
index 000000000..ebe9be1f9
--- /dev/null
+++ b/testsuite/synth/issue1951/sub02.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity sub02 is
+  port (i : std_logic_vector (3 downto 0);
+        o : out std_logic_vector (3 downto 0));
+end entity;
+
+architecture arch of sub02 is
+begin
+  o <= i - (-7);
+end arch;
diff --git a/testsuite/synth/issue1951/sub03.vhdl b/testsuite/synth/issue1951/sub03.vhdl
new file mode 100644
index 000000000..10e743047
--- /dev/null
+++ b/testsuite/synth/issue1951/sub03.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity sub03 is
+  port (i : std_logic_vector (3 downto 0);
+        o : out std_logic_vector (3 downto 0));
+end entity;
+
+architecture arch of sub03 is
+begin
+  o <= i - (-8);
+end arch;
diff --git a/testsuite/synth/issue1951/sub04.vhdl b/testsuite/synth/issue1951/sub04.vhdl
new file mode 100644
index 000000000..827a5a11e
--- /dev/null
+++ b/testsuite/synth/issue1951/sub04.vhdl
@@ -0,0 +1,13 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity sub04 is
+  port (i : std_logic_vector (3 downto 0);
+        o : out std_logic_vector (3 downto 0));
+end entity;
+
+architecture arch of sub04 is
+begin
+  o <= i - (-9);
+end arch;
diff --git a/testsuite/synth/issue1951/tb_sub01.vhdl b/testsuite/synth/issue1951/tb_sub01.vhdl
new file mode 100644
index 000000000..f47abe5de
--- /dev/null
+++ b/testsuite/synth/issue1951/tb_sub01.vhdl
@@ -0,0 +1,20 @@
+entity tb_sub01 is
+end tb_sub01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_sub01 is
+  signal i, o : std_logic_vector(3 downto 0) := x"0";
+begin
+  dut: entity work.sub01
+    port map (i => i, o => o);
+
+  process
+  begin
+    i <= x"0";
+    wait for 1 ns;
+    assert o = x"1" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1951/tb_sub02.vhdl b/testsuite/synth/issue1951/tb_sub02.vhdl
new file mode 100644
index 000000000..941c6ba99
--- /dev/null
+++ b/testsuite/synth/issue1951/tb_sub02.vhdl
@@ -0,0 +1,29 @@
+entity tb_sub02 is
+end tb_sub02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_sub02 is
+  signal i, o : std_logic_vector(3 downto 0) := x"0";
+begin
+  dut: entity work.sub02
+    port map (i => i, o => o);
+
+  process
+  begin
+    i <= x"0";
+    wait for 1 ns;
+    assert o = x"7" severity failure;
+
+    i <= x"8";
+    wait for 1 ns;
+    assert o = x"f" severity failure;
+
+    i <= x"9";
+    wait for 1 ns;
+    assert o = x"0" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1951/tb_sub03.vhdl b/testsuite/synth/issue1951/tb_sub03.vhdl
new file mode 100644
index 000000000..732f00f20
--- /dev/null
+++ b/testsuite/synth/issue1951/tb_sub03.vhdl
@@ -0,0 +1,29 @@
+entity tb_sub03 is
+end tb_sub03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_sub03 is
+  signal i, o : std_logic_vector(3 downto 0) := x"0";
+begin
+  dut: entity work.sub03
+    port map (i => i, o => o);
+
+  process
+  begin
+    i <= x"0";
+    wait for 1 ns;
+    assert o = x"8" severity failure;
+
+    i <= x"8";
+    wait for 1 ns;
+    assert o = x"0" severity failure;
+
+    i <= x"9";
+    wait for 1 ns;
+    assert o = x"1" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1951/tb_sub04.vhdl b/testsuite/synth/issue1951/tb_sub04.vhdl
new file mode 100644
index 000000000..ca9159dff
--- /dev/null
+++ b/testsuite/synth/issue1951/tb_sub04.vhdl
@@ -0,0 +1,29 @@
+entity tb_sub04 is
+end tb_sub04;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_sub04 is
+  signal i, o : std_logic_vector(3 downto 0) := x"0";
+begin
+  dut: entity work.sub04
+    port map (i => i, o => o);
+
+  process
+  begin
+    i <= x"0";
+    wait for 1 ns;
+    assert o = x"9" severity failure;
+
+    i <= x"8";
+    wait for 1 ns;
+    assert o = x"1" severity failure;
+
+    i <= x"9";
+    wait for 1 ns;
+    assert o = x"2" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1951/testsuite.sh b/testsuite/synth/issue1951/testsuite.sh
index f8d05daef..00865f1ec 100755
--- a/testsuite/synth/issue1951/testsuite.sh
+++ b/testsuite/synth/issue1951/testsuite.sh
@@ -5,4 +5,8 @@
 GHDL_STD_FLAGS=-fsynopsys
 synth_only ent
 
+for f in sub01 sub02 sub03 sub04; do
+    synth_tb $f
+done
+
 echo "Test successful"