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-rw-r--r--testsuite/synth/issue1951/sub02.vhdl13
1 files changed, 13 insertions, 0 deletions
diff --git a/testsuite/synth/issue1951/sub02.vhdl b/testsuite/synth/issue1951/sub02.vhdl
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+++ b/testsuite/synth/issue1951/sub02.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity sub02 is
+ port (i : std_logic_vector (3 downto 0);
+ o : out std_logic_vector (3 downto 0));
+end entity;
+
+architecture arch of sub02 is
+begin
+ o <= i - (-7);
+end arch;