aboutsummaryrefslogtreecommitdiffstats
path: root/testsuite
diff options
context:
space:
mode:
authorTristan Gingold <tgingold@free.fr>2022-01-15 17:03:26 +0100
committerTristan Gingold <tgingold@free.fr>2022-01-15 17:03:26 +0100
commita002d9d0b039afefc5651d3cc691f12ea339baed (patch)
tree162f26ff726c64f440618571f944eb9517a7230b /testsuite
parentea28fa56f21afb8a40a84151bdaba3f33ddb145d (diff)
downloadghdl-a002d9d0b039afefc5651d3cc691f12ea339baed.tar.gz
ghdl-a002d9d0b039afefc5651d3cc691f12ea339baed.tar.bz2
ghdl-a002d9d0b039afefc5651d3cc691f12ea339baed.zip
testsuite/synth: add tests for generic types in entities
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/synth/gen01/dly1.vhdl23
-rw-r--r--testsuite/synth/gen01/dly2.vhdl23
-rw-r--r--testsuite/synth/gen01/dly3.vhdl24
-rwxr-xr-xtestsuite/synth/gen01/testsuite.sh10
4 files changed, 80 insertions, 0 deletions
diff --git a/testsuite/synth/gen01/dly1.vhdl b/testsuite/synth/gen01/dly1.vhdl
new file mode 100644
index 000000000..69ac5a3e1
--- /dev/null
+++ b/testsuite/synth/gen01/dly1.vhdl
@@ -0,0 +1,23 @@
+entity gen_delay is
+ generic (type T);
+
+ port (i : in T;
+ o : out T);
+end gen_delay;
+
+architecture arch of gen_delay is
+begin
+ o <= i;
+end arch;
+
+entity dly1 is
+ port (i : in bit;
+ o : out bit);
+end dly1;
+
+architecture struct of dly1 is
+begin
+ inst: entity work.gen_delay
+ generic map (T => bit)
+ port map (i => i, o => o);
+end struct;
diff --git a/testsuite/synth/gen01/dly2.vhdl b/testsuite/synth/gen01/dly2.vhdl
new file mode 100644
index 000000000..10bcba383
--- /dev/null
+++ b/testsuite/synth/gen01/dly2.vhdl
@@ -0,0 +1,23 @@
+entity gen_delay is
+ generic (type T);
+
+ port (i : in T;
+ o : out T);
+end gen_delay;
+
+architecture arch of gen_delay is
+begin
+ o <= i;
+end arch;
+
+entity dly2 is
+ port (i : in bit_vector(7 downto 0);
+ o : out bit_vector(7 downto 0));
+end dly2;
+
+architecture struct of dly2 is
+begin
+ inst: entity work.gen_delay
+ generic map (T => bit_vector(7 downto 0))
+ port map (i => i, o => o);
+end struct;
diff --git a/testsuite/synth/gen01/dly3.vhdl b/testsuite/synth/gen01/dly3.vhdl
new file mode 100644
index 000000000..2c5f199cf
--- /dev/null
+++ b/testsuite/synth/gen01/dly3.vhdl
@@ -0,0 +1,24 @@
+entity gen_delay is
+ generic (type T);
+
+ port (i : in T;
+ o : out T);
+end gen_delay;
+
+architecture arch of gen_delay is
+begin
+ o <= i;
+end arch;
+
+entity dly3 is
+ port (i : in bit_vector(7 downto 0);
+ o : out bit_vector(7 downto 0));
+end dly3;
+
+architecture struct of dly3 is
+ subtype t_vect is bit_vector(7 downto 0);
+begin
+ inst: entity work.gen_delay
+ generic map (T => t_vect)
+ port map (i => i, o => o);
+end struct;
diff --git a/testsuite/synth/gen01/testsuite.sh b/testsuite/synth/gen01/testsuite.sh
new file mode 100755
index 000000000..16e9f52c9
--- /dev/null
+++ b/testsuite/synth/gen01/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth_only dly1
+synth_only dly2
+synth_only dly3
+
+echo "Test successful"