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author | Tristan Gingold <tgingold@free.fr> | 2019-05-22 06:43:52 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-22 06:43:52 +0200 |
commit | 1b761905bb2eeb243e60d2846cfb04aad7388d1a (patch) | |
tree | 50c240d6f4833426ed411acec32442f625e4e00f /testsuite/synth/dff01/dff08.vhdl | |
parent | 1f63ad0215f932c3776057e14946e2d3202c5779 (diff) | |
download | ghdl-1b761905bb2eeb243e60d2846cfb04aad7388d1a.tar.gz ghdl-1b761905bb2eeb243e60d2846cfb04aad7388d1a.tar.bz2 ghdl-1b761905bb2eeb243e60d2846cfb04aad7388d1a.zip |
synth: add testcase for falling edge.
Diffstat (limited to 'testsuite/synth/dff01/dff08.vhdl')
-rw-r--r-- | testsuite/synth/dff01/dff08.vhdl | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/synth/dff01/dff08.vhdl b/testsuite/synth/dff01/dff08.vhdl new file mode 100644 index 000000000..7cdb79a84 --- /dev/null +++ b/testsuite/synth/dff01/dff08.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff08 is + port (q : out std_logic; + d : std_logic; + clk : std_logic); +end dff08; + +architecture behav of dff08 is +begin + process (clk) is + begin + if falling_edge (clk) then + q <= d; + end if; + end process; +end behav; |