From 1b761905bb2eeb243e60d2846cfb04aad7388d1a Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Wed, 22 May 2019 06:43:52 +0200
Subject: synth: add testcase for falling edge.

---
 testsuite/synth/dff01/dff08.vhdl | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 testsuite/synth/dff01/dff08.vhdl

(limited to 'testsuite/synth/dff01/dff08.vhdl')

diff --git a/testsuite/synth/dff01/dff08.vhdl b/testsuite/synth/dff01/dff08.vhdl
new file mode 100644
index 000000000..7cdb79a84
--- /dev/null
+++ b/testsuite/synth/dff01/dff08.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dff08 is
+  port (q : out std_logic;
+        d : std_logic;
+        clk : std_logic);
+end dff08;
+
+architecture behav of dff08 is
+begin
+  process (clk) is
+  begin
+    if falling_edge (clk) then
+      q <= d;
+    end if;
+  end process;
+end behav;
-- 
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