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authorTristan Gingold <tgingold@free.fr>2021-11-12 18:52:18 +0100
committerTristan Gingold <tgingold@free.fr>2021-11-12 18:52:58 +0100
commit56735b0d1e92b4246ef53442236e89afe07aacdc (patch)
tree7b0c825edbc6021b269e89d187bc06fb93e997ad /testsuite/synth/blackbox01/blackbox1_adder.vhdl
parentc2b6b4fe03c879753c76f5bee9f0ffe3b0e73f52 (diff)
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testsuite/synth: add a test for black boxes
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-rw-r--r--testsuite/synth/blackbox01/blackbox1_adder.vhdl13
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diff --git a/testsuite/synth/blackbox01/blackbox1_adder.vhdl b/testsuite/synth/blackbox01/blackbox1_adder.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity blackbox1_adder is
+ port (a, b : in std_logic_vector(7 downto 0);
+ r : out std_logic_vector(7 downto 0));
+end blackbox1_adder;
+
+architecture behav of blackbox1_adder is
+begin
+ r <= std_logic_vector(unsigned(a) + unsigned(b));
+end behav;