From f0900d17ff6ac00d3653e7aea5af166b603b155a Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 18 Sep 2022 08:57:27 +0200 Subject: synth-vhdl_stmts: minor renaming --- src/simul/simul-vhdl_simul.adb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/simul') diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index b5f14a067..4a8ef443f 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -758,7 +758,7 @@ package body Simul.Vhdl_Simul is pragma Assert (Obj = Null_Node); Sub_Inst := Synth_Subprogram_Call_Instance (Inst, Imp, Imp); - Synth_Subprogram_Association + Synth_Subprogram_Associations (Sub_Inst, Inst, Inter_Chain, Assoc_Chain); Synth.Vhdl_Static_Proc.Synth_Static_Procedure @@ -791,7 +791,7 @@ package body Simul.Vhdl_Simul is -- Note: in fact the uninstantiated scope is the instantiated -- one! Set_Uninstantiated_Scope (Sub_Inst, Imp); - Synth_Subprogram_Association + Synth_Subprogram_Associations (Sub_Inst, Inst, Inter_Chain, Assoc_Chain); Process.Instance := Sub_Inst; -- cgit v1.2.3