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authorTristan Gingold <tgingold@free.fr>2022-12-27 08:53:00 +0100
committerTristan Gingold <tgingold@free.fr>2022-12-31 13:54:49 +0100
commitb7a9e4b9b5ac2c195da6f3549dd06b5c6e999a0f (patch)
treeab341f364e81544b1445d262708df16300198aa8 /src/simul
parentd6343a0bf74d25973c5ed170b8e037b42bd08a7f (diff)
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synth: add statement in context, adjust path/instance name attributes
Diffstat (limited to 'src/simul')
-rw-r--r--src/simul/simul-vhdl_elab.adb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 36bc1df23..3f4d0af4f 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -1077,7 +1077,7 @@ package body Simul.Vhdl_Elab is
Proc := Processes_Table.Table (I).Proc;
if Get_Kind (Proc) in Iir_Kinds_Process_Statement then
Proc_Inst := Make_Elab_Instance (Processes_Table.Table (I).Inst,
- Proc, Null_Node);
+ Proc, Proc, Null_Node);
Processes_Table.Table (I).Inst := Proc_Inst;
Set_Instance_Const (Proc_Inst, True);
Synth.Vhdl_Decls.Synth_Declarations