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authorTristan Gingold <tgingold@free.fr>2022-12-27 08:53:00 +0100
committerTristan Gingold <tgingold@free.fr>2022-12-31 13:54:49 +0100
commitb7a9e4b9b5ac2c195da6f3549dd06b5c6e999a0f (patch)
treeab341f364e81544b1445d262708df16300198aa8 /src
parentd6343a0bf74d25973c5ed170b8e037b42bd08a7f (diff)
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synth: add statement in context, adjust path/instance name attributes
Diffstat (limited to 'src')
-rw-r--r--src/simul/simul-vhdl_elab.adb2
-rw-r--r--src/synth/elab-vhdl_context.adb25
-rw-r--r--src/synth/elab-vhdl_context.ads29
-rw-r--r--src/synth/elab-vhdl_debug.adb4
-rw-r--r--src/synth/elab-vhdl_expr.adb47
-rw-r--r--src/synth/elab-vhdl_insts.adb13
-rw-r--r--src/synth/elab-vhdl_stmts.adb4
-rw-r--r--src/synth/synth-vhdl_context.adb2
-rw-r--r--src/synth/synth-vhdl_decls.adb2
-rw-r--r--src/synth/synth-vhdl_stmts.adb7
10 files changed, 92 insertions, 43 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 36bc1df23..3f4d0af4f 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -1077,7 +1077,7 @@ package body Simul.Vhdl_Elab is
Proc := Processes_Table.Table (I).Proc;
if Get_Kind (Proc) in Iir_Kinds_Process_Statement then
Proc_Inst := Make_Elab_Instance (Processes_Table.Table (I).Inst,
- Proc, Null_Node);
+ Proc, Proc, Null_Node);
Processes_Table.Table (I).Inst := Proc_Inst;
Set_Instance_Const (Proc_Inst, True);
Synth.Vhdl_Decls.Synth_Declarations
diff --git a/src/synth/elab-vhdl_context.adb b/src/synth/elab-vhdl_context.adb
index 56de0563e..cfc41aacc 100644
--- a/src/synth/elab-vhdl_context.adb
+++ b/src/synth/elab-vhdl_context.adb
@@ -58,6 +58,7 @@ package body Elab.Vhdl_Context is
Block_Scope => Global_Info,
Up_Block => null,
Uninst_Scope => null,
+ Stmt => Null_Node,
Source_Scope => Null_Node,
Caller => null,
Config => Null_Node,
@@ -75,22 +76,17 @@ package body Elab.Vhdl_Context is
null;
end Free_Base_Instance;
- function Make_Elab_Instance
- (Parent : Synth_Instance_Acc; Blk : Node; Config : Node)
+ function Make_Elab_Instance (Parent : Synth_Instance_Acc;
+ Stmt : Node;
+ Blk : Node;
+ Config : Node)
return Synth_Instance_Acc
is
Info : constant Sim_Info_Acc := Get_Info (Blk);
- Scope : Sim_Info_Acc;
+ Scope : constant Sim_Info_Acc := Get_Info_Scope (Blk);
Nbr_Objs : Object_Slot_Type;
Res : Synth_Instance_Acc;
begin
- if Get_Kind (Blk) = Iir_Kind_Architecture_Body then
- -- Architectures are extensions of entities.
- Scope := Get_Info (Vhdl.Utils.Get_Entity (Blk));
- else
- Scope := Info;
- end if;
-
if Scope = null then
-- Foreign modules are not annotated.
pragma Assert (Get_Kind (Blk) = Iir_Kind_Foreign_Module);
@@ -107,6 +103,7 @@ package body Elab.Vhdl_Context is
Block_Scope => Scope,
Up_Block => Parent,
Uninst_Scope => null,
+ Stmt => Stmt,
Source_Scope => Blk,
Caller => null,
Config => Config,
@@ -149,6 +146,7 @@ package body Elab.Vhdl_Context is
Block_Scope => Info,
Up_Block => Parent,
Uninst_Scope => null,
+ Stmt => Blk, -- TBC.
Source_Scope => Blk,
Caller => null,
Config => Config,
@@ -190,6 +188,11 @@ package body Elab.Vhdl_Context is
return Inst.Source_Scope;
end Get_Source_Scope;
+ function Get_Statement_Scope (Inst : Synth_Instance_Acc) return Node is
+ begin
+ return Inst.Stmt;
+ end Get_Statement_Scope;
+
function Get_Instance_Parent (Inst : Synth_Instance_Acc)
return Synth_Instance_Acc is
begin
@@ -462,7 +465,7 @@ package body Elab.Vhdl_Context is
is
Syn_Inst : Synth_Instance_Acc;
begin
- Syn_Inst := Make_Elab_Instance (Parent_Inst, Pkg, Null_Node);
+ Syn_Inst := Make_Elab_Instance (Parent_Inst, Null_Node, Pkg, Null_Node);
if Get_Kind (Get_Parent (Pkg)) = Iir_Kind_Design_Unit then
-- Global package.
Create_Package_Object (Parent_Inst, Pkg, Syn_Inst, True);
diff --git a/src/synth/elab-vhdl_context.ads b/src/synth/elab-vhdl_context.ads
index 3a85cd089..13fe8bb49 100644
--- a/src/synth/elab-vhdl_context.ads
+++ b/src/synth/elab-vhdl_context.ads
@@ -54,9 +54,10 @@ package Elab.Vhdl_Context is
procedure Free_Base_Instance;
-- Create and free the corresponding synth instance.
- function Make_Elab_Instance
- (Parent : Synth_Instance_Acc; Blk : Node; Config : Node)
- return Synth_Instance_Acc;
+ function Make_Elab_Instance (Parent : Synth_Instance_Acc;
+ Stmt : Node;
+ Blk : Node;
+ Config : Node) return Synth_Instance_Acc;
procedure Free_Elab_Instance (Synth_Inst : in out Synth_Instance_Acc);
@@ -82,6 +83,9 @@ package Elab.Vhdl_Context is
-- Get the corresponding source for the scope of the instance.
function Get_Source_Scope (Inst : Synth_Instance_Acc) return Node;
+ -- Return the statement that created the scope.
+ function Get_Statement_Scope (Inst : Synth_Instance_Acc) return Node;
+
-- Get parent_instance.
function Get_Instance_Parent (Inst : Synth_Instance_Acc)
return Synth_Instance_Acc;
@@ -278,7 +282,26 @@ private
-- Used only fo debugging purpose.
Caller : Synth_Instance_Acc;
+ -- Statement that created the scope. One of:
+ -- * Subprogram call statement
+ -- * Component instantiation
+ -- * Block
+ -- * Process
+ -- * Generate body
+ -- * Block
+ -- * Protected object
+ -- * Null_Node for Root_Instance, package, vunit.
+ Stmt : Node;
+
-- Source construct corresponding to this instance.
+ -- * Architecture body
+ -- * Component declaration
+ -- * Foreign Module
+ -- * Subprogram
+ -- * Process
+ -- * Generate body
+ -- * Block
+ -- * ...
Source_Scope : Node;
-- Block configuration (unless the instance is for a package).
diff --git a/src/synth/elab-vhdl_debug.adb b/src/synth/elab-vhdl_debug.adb
index e5e40011e..2cea530d7 100644
--- a/src/synth/elab-vhdl_debug.adb
+++ b/src/synth/elab-vhdl_debug.adb
@@ -1199,6 +1199,8 @@ package body Elab.Vhdl_Debug is
| Iir_Kind_For_Generate_Statement =>
Open_Declarative_Region;
Add_Name (Get_Parameter_Specification (N));
+ when Iir_Kind_If_Generate_Statement =>
+ Open_Declarative_Region;
when Iir_Kind_Block_Statement =>
declare
Header : constant Iir := Get_Block_Header (N);
@@ -1216,7 +1218,7 @@ package body Elab.Vhdl_Debug is
Add_Declarations (Get_Declaration_Chain (N), False);
Add_Declarations_Of_Concurrent_Statement (N);
when others =>
- Vhdl.Errors.Error_Kind ("enter_scope(2)", N);
+ Vhdl.Errors.Error_Kind ("add_decls_for", N);
end case;
end Add_Decls_For;
diff --git a/src/synth/elab-vhdl_expr.adb b/src/synth/elab-vhdl_expr.adb
index d9ad9f27d..86b2e5d24 100644
--- a/src/synth/elab-vhdl_expr.adb
+++ b/src/synth/elab-vhdl_expr.adb
@@ -469,7 +469,7 @@ package body Elab.Vhdl_Expr is
Get_Path_Instance_Name_Suffix (Attr);
Instance, Parent : Synth_Instance_Acc;
Rstr : Rstring;
- Label : Node;
+ Label, Stmt : Node;
begin
if Name.Path_Instance = Null_Iir then
return String_To_Memtyp (Name.Suffix, Str_Typ);
@@ -484,6 +484,7 @@ package body Elab.Vhdl_Expr is
Parent := null;
end if;
Label := Get_Source_Scope (Instance);
+ Stmt := Get_Statement_Scope (Instance);
case Get_Kind (Label) is
when Iir_Kind_Entity_Declaration =>
@@ -508,27 +509,45 @@ package body Elab.Vhdl_Expr is
when Iir_Kind_Block_Statement =>
Prepend (Rstr, Image (Get_Label (Label)));
Prepend (Rstr, ':');
- when Iir_Kind_Iterator_Declaration =>
+ when Iir_Kind_Generate_Statement_Body =>
declare
- Val : Valtyp;
+ Gen : constant Node := Get_Parent (Label);
begin
- Val := Get_Value (Instance, Label);
- Prepend (Rstr, ')');
- Prepend (Rstr,
- Synth_Image_Attribute_Str (Val, Get_Type (Label)));
- Prepend (Rstr, '(');
+ case Iir_Kinds_Generate_Statement (Get_Kind (Gen)) is
+ when Iir_Kind_For_Generate_Statement =>
+ declare
+ It : constant Node :=
+ Get_Parameter_Specification (Gen);
+ Val : Valtyp;
+ begin
+ Val := Get_Value (Instance, It);
+ Prepend (Rstr, ')');
+ Prepend
+ (Rstr,
+ Synth_Image_Attribute_Str (Val, Get_Type (It)));
+ Prepend (Rstr, '(');
+ end;
+
+ -- Skip the for generate instance.
+ Parent := Get_Instance_Parent (Parent);
+
+ when Iir_Kind_If_Generate_Statement
+ | Iir_Kind_Case_Generate_Statement =>
+ null;
+ end case;
+
+ Prepend (Rstr, Image (Get_Label (Gen)));
+ Prepend (Rstr, ':');
end;
- when Iir_Kind_Generate_Statement_Body =>
- Prepend (Rstr, Image (Get_Label (Get_Parent (Label))));
- Prepend (Rstr, ':');
- when Iir_Kind_Component_Instantiation_Statement =>
+
+ when Iir_Kind_Component_Declaration =>
if Is_Instance then
Prepend (Rstr, '@');
end if;
- Prepend (Rstr, Image (Get_Label (Label)));
+ Prepend (Rstr, Image (Get_Label (Stmt)));
Prepend (Rstr, ':');
when others =>
- Error_Kind ("Execute_Path_Instance_Name_Attribute",
+ Error_Kind ("Exec_Path_Instance_Name_Attribute",
Label);
end case;
Instance := Parent;
diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb
index 389a816a4..e6ebb707e 100644
--- a/src/synth/elab-vhdl_insts.adb
+++ b/src/synth/elab-vhdl_insts.adb
@@ -461,7 +461,8 @@ package body Elab.Vhdl_Insts is
begin
Elab_Dependencies (Root_Instance, Get_Design_Unit (Unit));
- Unit_Inst := Make_Elab_Instance (Syn_Inst, Unit, Config => Null_Node);
+ Unit_Inst := Make_Elab_Instance
+ (Syn_Inst, Null_Node, Unit, Config => Null_Node);
Add_Extra_Instance (Syn_Inst, Unit_Inst);
Apply_Block_Configuration
@@ -686,7 +687,7 @@ package body Elab.Vhdl_Insts is
Sub_Inst : Synth_Instance_Acc;
begin
-- Elaborate generic + map aspect
- Sub_Inst := Make_Elab_Instance (Syn_Inst, Arch, Config);
+ Sub_Inst := Make_Elab_Instance (Syn_Inst, Stmt, Arch, Config);
Create_Sub_Instance (Syn_Inst, Stmt, Sub_Inst);
@@ -735,7 +736,7 @@ package body Elab.Vhdl_Insts is
-- Create the sub-instance for the component
-- Elaborate generic + map aspect
- Comp_Inst := Make_Elab_Instance (Syn_Inst, Component, Config);
+ Comp_Inst := Make_Elab_Instance (Syn_Inst, Stmt, Component, Config);
Create_Sub_Instance (Syn_Inst, Stmt, Comp_Inst);
pragma Assert (Is_Expr_Pool_Empty);
@@ -796,7 +797,7 @@ package body Elab.Vhdl_Insts is
end case;
if Get_Kind (Ent) = Iir_Kind_Foreign_Module then
- Sub_Inst := Make_Elab_Instance (Comp_Inst, Ent, Null_Node);
+ Sub_Inst := Make_Elab_Instance (Comp_Inst, Stmt, Ent, Null_Node);
Create_Component_Instance (Comp_Inst, Sub_Inst);
Elab_Foreign_Instance (Sub_Inst, Comp_Inst, Bind, Ent);
@@ -818,7 +819,7 @@ package body Elab.Vhdl_Insts is
Elab_Dependencies (Root_Instance, Get_Design_Unit (Arch));
-- Elaborate generic + map aspect for the entity instance.
- Sub_Inst := Make_Elab_Instance (Comp_Inst, Arch, Sub_Config);
+ Sub_Inst := Make_Elab_Instance (Comp_Inst, Stmt, Arch, Sub_Config);
Create_Component_Instance (Comp_Inst, Sub_Inst);
Elab_Generics_Association (Sub_Inst, Comp_Inst,
@@ -891,7 +892,7 @@ package body Elab.Vhdl_Insts is
Make_Root_Instance;
Top_Inst := Make_Elab_Instance
- (Root_Instance, Arch, Get_Block_Configuration (Config));
+ (Root_Instance, Null_Node, Arch, Get_Block_Configuration (Config));
-- Save the current architecture, so that files can be open using a
-- path relative to the architecture filename.
diff --git a/src/synth/elab-vhdl_stmts.adb b/src/synth/elab-vhdl_stmts.adb
index def7e9218..7d6b6f01d 100644
--- a/src/synth/elab-vhdl_stmts.adb
+++ b/src/synth/elab-vhdl_stmts.adb
@@ -40,7 +40,7 @@ package body Elab.Vhdl_Stmts is
Decls_Chain : constant Node := Get_Declaration_Chain (Bod);
Bod_Inst : Synth_Instance_Acc;
begin
- Bod_Inst := Make_Elab_Instance (Syn_Inst, Bod, Config);
+ Bod_Inst := Make_Elab_Instance (Syn_Inst, Bod, Bod, Config);
if Iterator /= Null_Node then
-- Add the iterator (for for-generate).
@@ -205,7 +205,7 @@ package body Elab.Vhdl_Stmts is
Apply_Block_Configuration
(Get_Block_Block_Configuration (Blk), Blk);
- Blk_Inst := Make_Elab_Instance (Syn_Inst, Blk, Null_Iir);
+ Blk_Inst := Make_Elab_Instance (Syn_Inst, Blk, Blk, Null_Iir);
Create_Sub_Instance (Syn_Inst, Blk, Blk_Inst);
if Guard /= Null_Node then
diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb
index 7d05e203a..55f9f795d 100644
--- a/src/synth/synth-vhdl_context.adb
+++ b/src/synth/synth-vhdl_context.adb
@@ -90,7 +90,7 @@ package body Synth.Vhdl_Context is
is
Res : Synth_Instance_Acc;
begin
- Res := Make_Elab_Instance (Parent, Blk, Null_Node);
+ Res := Make_Elab_Instance (Parent, Null_Node, Blk, Null_Node);
Set_Extra (Res, Parent, Name);
return Res;
end Make_Instance;
diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb
index de10c01b6..fd0e9b5f5 100644
--- a/src/synth/synth-vhdl_decls.adb
+++ b/src/synth/synth-vhdl_decls.adb
@@ -407,7 +407,7 @@ package body Synth.Vhdl_Decls is
Res : Valtyp;
begin
Parent := Get_Instance_By_Scope (Inst, Get_Parent_Scope (Bod));
- Obj_Inst := Make_Elab_Instance (Parent, Bod, Null_Node);
+ Obj_Inst := Make_Elab_Instance (Parent, Decl, Bod, Null_Node);
Obj_Hand := Elab.Vhdl_Prot.Create (Obj_Inst);
Instance_Pool := Global_Pool'Access;
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index bba8c823b..a72a3ac09 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -2536,7 +2536,7 @@ package body Synth.Vhdl_Stmts is
Up_Inst : Synth_Instance_Acc;
begin
Up_Inst := Get_Instance_By_Scope (Inst, Get_Parent_Scope (Imp));
- Res := Make_Elab_Instance (Up_Inst, Bod, Config => Null_Node);
+ Res := Make_Elab_Instance (Up_Inst, Null_Node, Bod, Config => Null_Node);
Set_Caller_Instance (Res, Inst);
return Res;
end Synth_Subprogram_Call_Instance;
@@ -2577,7 +2577,8 @@ package body Synth.Vhdl_Stmts is
Idx := Read_Protected (Obj_Info.Obj.Val.Mem);
Obj_Inst := Elab.Vhdl_Prot.Get (Idx);
- Res := Make_Elab_Instance (Obj_Inst, Bod, Config => Null_Node);
+ Res := Make_Elab_Instance (Obj_Inst,
+ Null_Node, Bod, Config => Null_Node);
Set_Caller_Instance (Res, Inst);
return Res;
end Synth_Protected_Call_Instance;
@@ -2718,7 +2719,7 @@ package body Synth.Vhdl_Stmts is
Sub_Inst : Synth_Instance_Acc;
begin
Areapools.Mark (Area_Mark, Instance_Pool.all);
- Sub_Inst := Make_Elab_Instance (Syn_Inst, Imp, Null_Node);
+ Sub_Inst := Make_Elab_Instance (Syn_Inst, Call, Imp, Null_Node);
if Ctxt /= null then
Set_Extra (Sub_Inst, Syn_Inst, New_Internal_Name (Ctxt));
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-01 23:43:41 +0000