From b3b31cc9b74b3f1bc07b15ada32ba2925eb490df Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sun, 18 Sep 2022 05:33:29 +0200 Subject: simul: handle individual port associations with expressions --- src/simul/simul-vhdl_elab.adb | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/simul') diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index b400a8106..b00cba063 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -629,8 +629,12 @@ package body Simul.Vhdl_Elab is null; when Iir_Kind_Association_Element_By_Expression => Inter := Get_Association_Interface (Assoc, Assoc_Inter); + Formal := Get_Formal (Assoc); + if Formal = Null_Iir then + Formal := Inter; + end if; Synth_Assignment_Prefix - (Port_Inst, Inter, Formal_Base, Typ, Off); + (Port_Inst, Formal, Formal_Base, Typ, Off); Formal_Sig := Formal_Base.Val.S; Formal_Ep := (Formal_Sig, Off, Typ); -- cgit v1.2.3