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-rw-r--r--src/simul/simul-vhdl_elab.adb6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index b400a8106..b00cba063 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -629,8 +629,12 @@ package body Simul.Vhdl_Elab is
null;
when Iir_Kind_Association_Element_By_Expression =>
Inter := Get_Association_Interface (Assoc, Assoc_Inter);
+ Formal := Get_Formal (Assoc);
+ if Formal = Null_Iir then
+ Formal := Inter;
+ end if;
Synth_Assignment_Prefix
- (Port_Inst, Inter, Formal_Base, Typ, Off);
+ (Port_Inst, Formal, Formal_Base, Typ, Off);
Formal_Sig := Formal_Base.Val.S;
Formal_Ep := (Formal_Sig, Off, Typ);