diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-08-09 08:24:22 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-08-09 08:24:22 +0000 |
| commit | 8ca210a4af9fd039e290cfcc309adde543999c1f (patch) | |
| tree | 1aa594d5e65d5ebabdd358acbe8d3a9ac29f2070 /os/hal/platforms/SPC5xx/eMIOS_v1 | |
| parent | cb453a3a12464dd71856b1354d083b5b02260870 (diff) | |
| download | ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.tar.gz ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.tar.bz2 ChibiOS-8ca210a4af9fd039e290cfcc309adde543999c1f.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6108 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/SPC5xx/eMIOS_v1')
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c | 783 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h | 382 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c | 1759 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h | 420 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c | 195 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h | 169 |
6 files changed, 0 insertions, 3708 deletions
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c deleted file mode 100644 index a8167c69c..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c +++ /dev/null @@ -1,783 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/icu_lld.c
- * @brief SPC5xx low level ICU driver code.
- *
- * @addtogroup ICU
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief ICUD1 driver identifier.
- * @note The driver ICUD1 allocates the unified channel eMIOS0_CH0
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH0 || defined(__DOXYGEN__)
-ICUDriver ICUD1;
-#endif
-
-/**
- * @brief ICUD2 driver identifier.
- * @note The driver ICUD2 allocates the unified channel eMIOS0_CH1
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH1 || defined(__DOXYGEN__)
-ICUDriver ICUD2;
-#endif
-
-/**
- * @brief ICUD3 driver identifier.
- * @note The driver ICUD3 allocates the unified channel eMIOS0_CH2
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH2 || defined(__DOXYGEN__)
-ICUDriver ICUD3;
-#endif
-
-/**
- * @brief ICUD4 driver identifier.
- * @note The driver ICUD4 allocates the unified channel eMIOS0_CH3
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH3 || defined(__DOXYGEN__)
-ICUDriver ICUD4;
-#endif
-
-/**
- * @brief ICUD5 driver identifier.
- * @note The driver ICUD5 allocates the unified channel eMIOS0_CH4
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH4 || defined(__DOXYGEN__)
-ICUDriver ICUD5;
-#endif
-
-/**
- * @brief ICUD6 driver identifier.
- * @note The driver ICUD6 allocates the unified channel eMIOS0_CH5
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH5 || defined(__DOXYGEN__)
-ICUDriver ICUD6;
-#endif
-
-/**
- * @brief ICUD7 driver identifier.
- * @note The driver ICUD7 allocates the unified channel eMIOS0_CH6
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH6 || defined(__DOXYGEN__)
-ICUDriver ICUD7;
-#endif
-
-/**
- * @brief ICUD8 driver identifier.
- * @note The driver ICUD8 allocates the unified channel eMIOS0_CH7
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH7 || defined(__DOXYGEN__)
-ICUDriver ICUD8;
-#endif
-
-/**
- * @brief ICUD9 driver identifier.
- * @note The driver ICUD9 allocates the unified channel eMIOS0_CH24
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS0_CH24 || defined(__DOXYGEN__)
-ICUDriver ICUD9;
-#endif
-
-/**
- * @brief ICUD10 driver identifier.
- * @note The driver ICUD10 allocates the unified channel eMIOS1_CH24
- * when enabled.
- */
-#if SPC5_ICU_USE_EMIOS1_CH24 || defined(__DOXYGEN__)
-ICUDriver ICUD10;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Width and Period registers.
- */
-int16_t width;
-int16_t period;
-
-/**
- * @brief A2 temp registers.
- */
-uint16_t A2_1, A2_2, A2_3;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief ICU IRQ handler.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- */
-static void icu_lld_serve_interrupt(ICUDriver *icup) {
- uint32_t gfr = icup->emiosp->GFR.R;
-
- if (gfr && (1 << icup->ch_number)) {
- uint32_t sr = icup->emiosp->CH[icup->ch_number].CSR.R;
-
- if(sr && EMIOSS_OVFL && icup->config->overflow_cb != NULL){
- icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC;
- _icu_isr_invoke_overflow_cb(icup);
- }
- if (sr && EMIOSS_FLAG){
- icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC;
- if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {
- if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \
- icup->config->period_cb != NULL) {
- A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
- period = A2_3 - A2_1;
- _icu_isr_invoke_period_cb(icup);
- A2_1 = A2_3;
- } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \
- icup->config->width_cb != NULL) {
- A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
- width = A2_2 - A2_1;
- _icu_isr_invoke_width_cb(icup);
- }
- } else if (icup->config->mode == ICU_INPUT_ACTIVE_LOW) {
- if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U && \
- icup->config->width_cb != NULL) {
- A2_2 = icup->emiosp->CH[icup->ch_number].CADR.R;
- width = A2_2 - A2_1;
- _icu_isr_invoke_width_cb(icup);
- } else if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 0 && \
- icup->config->period_cb != NULL) {
- A2_3 = icup->emiosp->CH[icup->ch_number].CADR.R;
- period = A2_3 - A2_1;
- _icu_isr_invoke_period_cb(icup);
- A2_1 = A2_3;
- }
- }
- }
- if(sr && EMIOSS_OVR){
- icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC;
- }
-
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_EMIOS0_CH0 || SPC5_ICU_USE_EMIOS0_CH1
-#if !defined(SPC5_EMIOS0_GFR_F0F1_HANDLER)
-#error "SPC5_EMIOS0_GFR_F0F1_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 0 and 1 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F0F1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH0
- icu_lld_serve_interrupt(&ICUD1);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH1
- icu_lld_serve_interrupt(&ICUD2);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 || SPC5_ICU_USE_EMIOS0_CH1 */
-
-#if SPC5_ICU_USE_EMIOS0_CH2 || SPC5_ICU_USE_EMIOS0_CH3
-#if !defined(SPC5_EMIOS0_GFR_F2F3_HANDLER)
-#error "SPC5_EMIOS0_GFR_F2F3_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 2 and 3 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F2F3_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH2
- icu_lld_serve_interrupt(&ICUD3);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH3
- icu_lld_serve_interrupt(&ICUD4);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 || SPC5_ICU_USE_EMIOS0_CH3 */
-
-#if SPC5_ICU_USE_EMIOS0_CH4 || SPC5_ICU_USE_EMIOS0_CH5
-#if !defined(SPC5_EMIOS0_GFR_F4F5_HANDLER)
-#error "SPC5_EMIOS0_GFR_F4F5_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 4 and 5 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F4F5_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH4
- icu_lld_serve_interrupt(&ICUD5);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH5
- icu_lld_serve_interrupt(&ICUD6);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 || SPC5_ICU_USE_EMIOS0_CH5 */
-
-#if SPC5_ICU_USE_EMIOS0_CH6 || SPC5_ICU_USE_EMIOS0_CH7
-
-#if !defined(SPC5_EMIOS0_GFR_F6F7_HANDLER)
-#error "SPC5_EMIOS0_GFR_F6F7_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 6 and 7 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F6F7_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH6
- icu_lld_serve_interrupt(&ICUD7);
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH7
- icu_lld_serve_interrupt(&ICUD8);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 || SPC5_ICU_USE_EMIOS0_CH7 */
-
-#if SPC5_ICU_USE_EMIOS0_CH24
-#if !defined(SPC5_EMIOS0_GFR_F24F25_HANDLER)
-#error "SPC5_EMIOS0_GFR_F24F25_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 24 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F24F25_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS0_CH24
- icu_lld_serve_interrupt(&ICUD9);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-
-#if SPC5_ICU_USE_EMIOS1_CH24
-#if !defined(SPC5_EMIOS1_GFR_F24F25_HANDLER)
-#error "SPC5_EMIOS1_GFR_F24F25_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 24 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F24F25_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
-#if SPC5_ICU_USE_EMIOS1_CH24
- icu_lld_serve_interrupt(&ICUD10);
-#endif
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ICU driver initialization.
- *
- * @notapi
- */
-void icu_lld_init(void) {
-
- /* Initialize A2 temp registers.*/
- A2_1 = 0U;
- A2_2 = 0U;
- A2_3 = 0U;
-
- /* eMIOSx channels initially all not in use.*/
- reset_emios0_active_channels();
- reset_emios1_active_channels();
-
-#if SPC5_ICU_USE_EMIOS0_CH0
- /* Driver initialization.*/
- icuObjectInit(&ICUD1);
- ICUD1.emiosp = &EMIOS_0;
- ICUD1.ch_number = 0U;
- ICUD1.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
-
-#if SPC5_ICU_USE_EMIOS0_CH1
- /* Driver initialization.*/
- icuObjectInit(&ICUD2);
- ICUD2.emiosp = &EMIOS_0;
- ICUD2.ch_number = 1U;
- ICUD2.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
-
-#if SPC5_ICU_USE_EMIOS0_CH2
- /* Driver initialization.*/
- icuObjectInit(&ICUD3);
- ICUD3.emiosp = &EMIOS_0;
- ICUD3.ch_number = 2U;
- ICUD3.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
-
-#if SPC5_ICU_USE_EMIOS0_CH3
- /* Driver initialization.*/
- icuObjectInit(&ICUD4);
- ICUD4.emiosp = &EMIOS_0;
- ICUD4.ch_number = 3U;
- ICUD4.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
-
-#if SPC5_ICU_USE_EMIOS0_CH4
- /* Driver initialization.*/
- icuObjectInit(&ICUD5);
- ICUD5.emiosp = &EMIOS_0;
- ICUD5.ch_number = 4U;
- ICUD5.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
-
-#if SPC5_ICU_USE_EMIOS0_CH5
- /* Driver initialization.*/
- icuObjectInit(&ICUD6);
- ICUD6.emiosp = &EMIOS_0;
- ICUD6.ch_number = 5U;
- ICUD6.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
-
-#if SPC5_ICU_USE_EMIOS0_CH6
- /* Driver initialization.*/
- icuObjectInit(&ICUD7);
- ICUD7.emiosp = &EMIOS_0;
- ICUD7.ch_number = 6U;
- ICUD7.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
-
-#if SPC5_ICU_USE_EMIOS0_CH7
- /* Driver initialization.*/
- icuObjectInit(&ICUD8);
- ICUD8.emiosp = &EMIOS_0;
- ICUD8.ch_number = 7U;
- ICUD8.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
-
-#if SPC5_ICU_USE_EMIOS0_CH24
- /* Driver initialization.*/
- icuObjectInit(&ICUD9);
- ICUD9.emiosp = &EMIOS_0;
- ICUD9.ch_number = 24U;
- ICUD9.clock = SPC5_EMIOS0_CLK;
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-
-#if SPC5_ICU_USE_EMIOS1_CH24
- /* Driver initialization.*/
- icuObjectInit(&ICUD10);
- ICUD10.emiosp = &EMIOS_1;
- ICUD10.ch_number = 24U;
- ICUD10.clock = SPC5_EMIOS1_CLK;
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
-#if SPC5_ICU_USE_EMIOS0
-
- INTC.PSR[SPC5_EMIOS0_GFR_F0F1_NUMBER].R = SPC5_EMIOS0_GFR_F0F1_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F2F3_NUMBER].R = SPC5_EMIOS0_GFR_F2F3_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F4F5_NUMBER].R = SPC5_EMIOS0_GFR_F4F5_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F6F7_NUMBER].R = SPC5_EMIOS0_GFR_F6F7_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F24F25_NUMBER].R = SPC5_EMIOS0_GFR_F24F25_PRIORITY;
-
-#endif
-
-#if SPC5_ICU_USE_EMIOS1
-
- INTC.PSR[SPC5_EMIOS1_GFR_F24F25_NUMBER].R = SPC5_EMIOS1_GFR_F24F25_PRIORITY;
-
-#endif
-}
-
-/**
- * @brief Configures and activates the ICU peripheral.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_start(ICUDriver *icup) {
-
- //uint32_t emios0_active_channels = get_emios0_active_channels();
- //uint32_t emios1_active_channels = get_emios1_active_channels();
-
- chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_start(), #1",
- "too many channels");
-
- chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_start(), #2",
- "too many channels");
-
- if (icup->state == ICU_STOP) {
- /* Enables the peripheral.*/
-#if SPC5_ICU_USE_EMIOS0_CH0
- if (&ICUD1 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
-#if SPC5_ICU_USE_EMIOS0_CH1
- if (&ICUD2 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
-#if SPC5_ICU_USE_EMIOS0_CH2
- if (&ICUD3 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
-#if SPC5_ICU_USE_EMIOS0_CH3
- if (&ICUD4 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
-#if SPC5_ICU_USE_EMIOS0_CH4
- if (&ICUD5 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
-#if SPC5_ICU_USE_EMIOS0_CH5
- if (&ICUD6 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
-#if SPC5_ICU_USE_EMIOS0_CH6
- if (&ICUD7 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
-#if SPC5_ICU_USE_EMIOS0_CH7
- if (&ICUD8 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
-#if SPC5_ICU_USE_EMIOS0_CH24
- if (&ICUD9 == icup)
- increase_emios0_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-#if SPC5_ICU_USE_EMIOS1_CH24
- if (&ICUD10 == icup)
- increase_emios1_active_channels();
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
- /* Set eMIOS0 Clock.*/
-#if SPC5_ICU_USE_EMIOS0
- active_emios0_clock(icup, NULL);
-#endif
-
- /* Set eMIOS1 Clock.*/
-#if SPC5_ICU_USE_EMIOS1
- active_emios1_clock(icup, NULL);
-#endif
-
- }
- /* Configures the peripheral.*/
-
- /* Channel enables.*/
- icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
-
- /* Clear pending IRQs (if any).*/
- icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Set clock prescaler and control register.*/
- uint32_t psc = (icup->clock / icup->config->frequency);
- chDbgAssert((psc <= 0xFFFF) &&
- (((psc) * icup->config->frequency) == icup->clock) &&
- ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
- "icu_lld_start(), #1", "invalid frequency");
-
- //icup->emiosp->MCR.B.GPREN = 0;
- icup->emiosp->CH[icup->ch_number].CCR.B.UCPEN = 0;
- icup->emiosp->CH[icup->ch_number].CCR.R |=
- EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) |
- EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC;
- icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1;
- icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN;
- /*
- if (icup->emiosp == &EMIOS_0) {
- icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
- } else if (icup->emiosp == &EMIOS_1) {
- icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
- }
- icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- icup->emiosp->MCR.B.GTBE = 1U;
- */
-
- /* Set source polarity.*/
- if(icup->config->mode == ICU_INPUT_ACTIVE_HIGH){
- icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_EDPOL;
- } else {
- icup->emiosp->CH[icup->ch_number].CCR.R &= ~EMIOSC_EDPOL;
- }
-
- /* Direct pointers to the period and width registers in order to make
- reading data faster from within callbacks.*/
- icup->pccrp = .
- icup->wccrp = &width;
-
- /* Channel disables.*/
- icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
-
-}
-
-/**
- * @brief Deactivates the ICU peripheral.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_stop(ICUDriver *icup) {
-
- //uint32_t emios0_active_channels = get_emios0_active_channels();
- //uint32_t emios1_active_channels = get_emios1_active_channels();
-
- chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_stop(), #1",
- "too many channels");
- chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_stop(), #2",
- "too many channels");
-
- if (icup->state == ICU_READY) {
-
- /* Disables the peripheral.*/
-#if SPC5_ICU_USE_EMIOS0_CH0
- if (&ICUD1 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH0 */
-#if SPC5_ICU_USE_EMIOS0_CH1
- if (&ICUD2 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH1 */
-#if SPC5_ICU_USE_EMIOS0_CH2
- if (&ICUD3 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH2 */
-#if SPC5_ICU_USE_EMIOS0_CH3
- if (&ICUD4 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH3 */
-#if SPC5_ICU_USE_EMIOS0_CH4
- if (&ICUD5 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH4 */
-#if SPC5_ICU_USE_EMIOS0_CH5
- if (&ICUD6 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH5 */
-#if SPC5_ICU_USE_EMIOS0_CH6
- if (&ICUD7 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH6 */
-#if SPC5_ICU_USE_EMIOS0_CH7
- if (&ICUD8 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH7 */
-#if SPC5_ICU_USE_EMIOS0_CH24
- if (&ICUD9 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS0_CH24 */
-#if SPC5_ICU_USE_EMIOS1_CH24
- if (&ICUD10 == icup) {
- /* Reset UC Control Register.*/
- icup->emiosp->CH[icup->ch_number].CCR.R = 0;
-
- decrease_emios1_active_channels();
- }
-#endif /* SPC5_ICU_USE_EMIOS1_CH24 */
-
- /* eMIOS0 clock deactivation.*/
-#if SPC5_ICU_USE_EMIOS0
- deactive_emios0_clock(icup, NULL);
-#endif
-
- /* eMIOS1 clock deactivation.*/
-#if SPC5_ICU_USE_EMIOS1
- deactive_emios1_clock(icup, NULL);
-#endif
- }
-}
-
-/**
- * @brief Enables the input capture.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_enable(ICUDriver *icup) {
-
- /* Channel enables.*/
- /*
- if (!(icup->emiosp->UCDIS.R && (1 << icup->ch_number))) {
-
- icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
- }
- */
-
- /* Channel enables.*/
- icup->emiosp->UCDIS.R &= ~(1 << icup->ch_number);
-
- /* Clear pending IRQs (if any).*/
- icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Active interrupts.*/
- if (icup->config->period_cb != NULL || icup->config->width_cb != NULL || \
- icup->config->overflow_cb != NULL) {
- icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U;
- }
-
-
-
- /* Enable Global Time Base.*/
- /*
- if (icup->emiosp->MCR.B.GTBE == 0) {
- icup->emiosp->MCR.B.GTBE = 1U;
- }
- */
-
-}
-
-/**
- * @brief Disables the input capture.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- *
- * @notapi
- */
-void icu_lld_disable(ICUDriver *icup) {
-
- /* Clear pending IRQs (if any).*/
- icup->emiosp->CH[icup->ch_number].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 0;
-
- /* Channel disables.*/
- icup->emiosp->UCDIS.R |= (1 << icup->ch_number);
-
-}
-
-#endif /* HAL_USE_ICU */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h deleted file mode 100644 index 31921333c..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.h +++ /dev/null @@ -1,382 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/icu_lld.h
- * @brief SPC5xx low level ICU driver header.
- *
- * @addtogroup ICU
- * @{
- */
-
-#ifndef _ICU_LLD_H_
-#define _ICU_LLD_H_
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-#if SPC5_HAS_EMIOS0 || defined(__DOXYGEN__)
-/**
- * @brief ICUD1 driver enable switch.
- * @details If set to @p TRUE the support for ICUD1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH0) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH0 FALSE
-#endif
-
-/**
- * @brief ICUD2 driver enable switch.
- * @details If set to @p TRUE the support for ICUD2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH1) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH1 FALSE
-#endif
-
-/**
- * @brief ICUD3 driver enable switch.
- * @details If set to @p TRUE the support for ICUD3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH2) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH2 FALSE
-#endif
-
-/**
- * @brief ICUD4 driver enable switch.
- * @details If set to @p TRUE the support for ICUD4 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH3) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH3 FALSE
-#endif
-
-/**
- * @brief ICUD5 driver enable switch.
- * @details If set to @p TRUE the support for ICUD5 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH4) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH4 FALSE
-#endif
-
-/**
- * @brief ICUD6 driver enable switch.
- * @details If set to @p TRUE the support for ICUD6 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH5) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH5 FALSE
-#endif
-
-/**
- * @brief ICUD7 driver enable switch.
- * @details If set to @p TRUE the support for ICUD7 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH6) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH6 FALSE
-#endif
-
-/**
- * @brief ICUD8 driver enable switch.
- * @details If set to @p TRUE the support for ICUD8 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH7) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH7 FALSE
-#endif
-
-/**
- * @brief ICUD9 driver enable switch.
- * @details If set to @p TRUE the support for ICUD9 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS0_CH24) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS0_CH24 FALSE
-#endif
-
-/**
- * @brief ICUD1 and ICUD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F0F1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F0F1_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD3 and ICUD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F2F3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F2F3_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD5 and ICUD6 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F4F5_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F4F5_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD7 and ICUD8 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F6F7_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F6F7_PRIORITY 7
-#endif
-
-/**
- * @brief ICUD9 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F24F25_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F24F25_PRIORITY 7
-#endif
-#endif
-
-#if SPC5_HAS_EMIOS1 || defined(__DOXYGEN__)
-/**
- * @brief ICUD10 driver enable switch.
- * @details If set to @p TRUE the support for ICUD10 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_ICU_USE_EMIOS1_CH24) || defined(__DOXYGEN__)
-#define SPC5_ICU_USE_EMIOS1_CH24 FALSE
-#endif
-
-/**
- * @brief ICUD10 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F24F25_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F24F25_PRIORITY 7
-#endif
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EMIOS0
-#error "EMIOS0 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_EMIOS1
-#error "EMIOS1 not present in the selected device"
-#endif
-
-#define SPC5_ICU_USE_EMIOS0 (SPC5_ICU_USE_EMIOS0_CH0 || \
- SPC5_ICU_USE_EMIOS0_CH1 || \
- SPC5_ICU_USE_EMIOS0_CH2 || \
- SPC5_ICU_USE_EMIOS0_CH3 || \
- SPC5_ICU_USE_EMIOS0_CH4 || \
- SPC5_ICU_USE_EMIOS0_CH5 || \
- SPC5_ICU_USE_EMIOS0_CH6 || \
- SPC5_ICU_USE_EMIOS0_CH7 || \
- SPC5_ICU_USE_EMIOS0_CH24)
-
-#define SPC5_ICU_USE_EMIOS1 SPC5_ICU_USE_EMIOS1_CH24
-
-#if !SPC5_ICU_USE_EMIOS0 && !SPC5_ICU_USE_EMIOS1
-#error "ICU driver activated but no Channels assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief ICU driver mode.
- */
-typedef enum {
- ICU_INPUT_ACTIVE_HIGH = 0, /**< Trigger on rising edge. */
- ICU_INPUT_ACTIVE_LOW = 1, /**< Trigger on falling edge. */
-} icumode_t;
-
-/**
- * @brief ICU frequency type.
- */
-typedef uint32_t icufreq_t;
-
-/**
- * @brief ICU counter type.
- */
-typedef uint16_t icucnt_t;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- /**
- * @brief Driver mode.
- */
- icumode_t mode;
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- icufreq_t frequency;
- /**
- * @brief Callback for pulse width measurement.
- */
- icucallback_t width_cb;
- /**
- * @brief Callback for cycle period measurement.
- */
- icucallback_t period_cb;
- /**
- * @brief Callback for timer overflow.
- */
- icucallback_t overflow_cb;
- /* End of the mandatory fields.*/
-} ICUConfig;
-
-/**
- * @brief Structure representing an ICU driver.
- */
-struct ICUDriver {
- /**
- * @brief Driver state.
- */
- icustate_t state;
- /**
- * @brief eMIOSx channel number.
- */
- uint32_t ch_number;
- /**
- * @brief Current configuration data.
- */
- const ICUConfig *config;
- /**
- * @brief CH Counter clock.
- */
- uint32_t clock;
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the eMIOSx registers block.
- */
- volatile struct EMIOS_tag *emiosp;
- /**
- * @brief CCR register used for width capture.
- */
- volatile vint16_t *wccrp;
- /**
- * @brief CCR register used for period capture.
- */
- volatile vint16_t *pccrp;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @brief Returns the width of the latest pulse.
- * @details The pulse width is defined as number of ticks between the start
- * edge and the stop edge.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- * @return The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_width(icup) (*((icup)->wccrp) + 1)
-
-/**
- * @brief Returns the width of the latest cycle.
- * @details The cycle width is defined as number of ticks between a start
- * edge and the next start edge.
- *
- * @param[in] icup pointer to the @p ICUDriver object
- * @return The number of ticks.
- *
- * @notapi
- */
-#define icu_lld_get_period(icup) (*((icup)->pccrp) + 1)
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_ICU_USE_EMIOS0_CH0 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD1;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH1 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD2;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH2 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD3;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH3 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD4;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH4 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD5;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH5 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD6;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH6 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD7;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH7 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD8;
-#endif
-
-#if SPC5_ICU_USE_EMIOS0_CH24 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD9;
-#endif
-
-#if SPC5_ICU_USE_EMIOS1_CH24 && !defined(__DOXYGEN__)
-extern ICUDriver ICUD10;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void icu_lld_init(void);
- void icu_lld_start(ICUDriver *icup);
- void icu_lld_stop(ICUDriver *icup);
- void icu_lld_enable(ICUDriver *icup);
- void icu_lld_disable(ICUDriver *icup);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _ICU_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c deleted file mode 100644 index f353b180a..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.c +++ /dev/null @@ -1,1759 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/pwm_lld.c
- * @brief SPC5xx low level PWM driver code.
- *
- * @addtogroup PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief PWMD1 driver identifier.
- * @note The driver PWMD1 allocates the unified channels eMIOS0_CH8 -
- * eMIOS0_CH15 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS0_GROUP0 || defined(__DOXYGEN__)
-PWMDriver PWMD1;
-#endif
-
-/**
- * @brief PWMD2 driver identifier.
- * @note The driver PWMD2 allocates the unified channels eMIOS0_CH16 -
- * eMIOS0_CH23 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS0_GROUP1 || defined(__DOXYGEN__)
-PWMDriver PWMD2;
-#endif
-
-/**
- * @brief PWMD3 driver identifier.
- * @note The driver PWMD3 allocates the unified channels eMIOS1_CH0 -
- * eMIOS1_CH7 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS1_GROUP0 || defined(__DOXYGEN__)
-PWMDriver PWMD3;
-#endif
-
-/**
- * @brief PWMD4 driver identifier.
- * @note The driver PWMD4 allocates the unified channels eMIOS1_CH8 -
- * eMIOS1_CH15 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS1_GROUP1 || defined(__DOXYGEN__)
-PWMDriver PWMD4;
-#endif
-
-/**
- * @brief PWMD5 driver identifier.
- * @note The driver PWMD5 allocates the unified channels eMIOS1_CH16 -
- * eMIOS1_CH23 when enabled.
- */
-#if SPC5_PWM_USE_EMIOS1_GROUP2 || defined(__DOXYGEN__)
-PWMDriver PWMD5;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief PWM IRQ handler.
- *
- * @param[in] pwmp pointer to the @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt1(PWMDriver *pwmp, uint32_t index) {
-
- uint32_t sr = pwmp->emiosp->CH[index].CSR.R;
- if (sr & EMIOSS_OVFL) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVFLC;
- }
- if (sr & EMIOSS_OVR) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVRC;
- }
- if (sr & EMIOSS_FLAG) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_FLAGC;
- if (pwmp->config->callback != NULL) {
- pwmp->config->callback(pwmp);
- }
- }
-
-}
-
-static void pwm_lld_serve_interrupt2(PWMDriver *pwmp, uint32_t index) {
-
- uint32_t sr = pwmp->emiosp->CH[index].CSR.R;
- if (sr & EMIOSS_OVFL) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVFLC;
- }
- if (sr & EMIOSS_OVR) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_OVRC;
- }
- if (sr & EMIOSS_FLAG) {
- pwmp->emiosp->CH[index].CSR.R |= EMIOSS_FLAGC;
- if (pwmp->config->channels[index%8U - 1].callback != NULL) {
- pwmp->config->channels[index%8U - 1].callback(pwmp);
- }
- }
-
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
-#if !defined(SPC5_EMIOS0_GFR_F8F9_HANDLER)
-#error "SPC5_EMIOS0_GFR_F8F9_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 8 and 9 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F8F9_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD1.emiosp->GFR.R;
-
- if (gfr & (1U << 8U)) {
- pwm_lld_serve_interrupt1(&PWMD1, 8U);
- }
- if (gfr & (1U << 9U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 9U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F10F11_HANDLER)
-#error "SPC5_EMIOS0_GFR_F10F11_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 10 and 11 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F10F11_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD1.emiosp->GFR.R;
-
- if (gfr & (1U << 10U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 10U);
- }
- if (gfr & (1U << 11U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 11U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F12F13_HANDLER)
-#error "SPC5_EMIOS0_GFR_F12F13_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 12 and 13 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F12F13_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD1.emiosp->GFR.R;
-
- if (gfr & (1U << 12U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 12U);
- }
- if (gfr & (1U << 13U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 13U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F14F15_HANDLER)
-#error "SPC5_EMIOS0_GFR_F14F15_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 14 and 15 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F14F15_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD1.emiosp->GFR.R;
-
- if (gfr && (1U << 14U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 14U);
- }
- if (gfr && (1U << 15U)) {
- pwm_lld_serve_interrupt2(&PWMD1, 15U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
-#if !defined(SPC5_EMIOS0_GFR_F16F17_HANDLER)
-#error "SPC5_EMIOS0_GFR_F16F17_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 16 and 17 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F16F17_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD2.emiosp->GFR.R;
-
- if (gfr && (1U << 16U)) {
- pwm_lld_serve_interrupt1(&PWMD2, 16U);
- }
- if (gfr && (1U << 17U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 17U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F18F19_HANDLER)
-#error "SPC5_EMIOS0_GFR_F18F19_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 18 and 19 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F18F19_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD2.emiosp->GFR.R;
-
- if (gfr && (1U << 18U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 18U);
- }
- if (gfr && (1U << 19U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 19U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F20F21_HANDLER)
-#error "SPC5_EMIOS0_GFR_F20F21_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 20 and 21 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F20F21_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD2.emiosp->GFR.R;
-
- if (gfr && (1U << 20U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 20U);
- }
- if (gfr && (1U << 21U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 21U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS0_GFR_F22F23_HANDLER)
-#error "SPC5_EMIOS0_GFR_F22F23_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS0 Channels 22 and 23 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS0_GFR_F22F23_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD2.emiosp->GFR.R;
-
- if (gfr && (1U << 22U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 22U);
- }
- if (gfr && (1U << 23U)) {
- pwm_lld_serve_interrupt2(&PWMD2, 23U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
-#if !defined(SPC5_EMIOS1_GFR_F0F1_HANDLER)
-#error "SPC5_EMIOS1_GFR_F0F1_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 0 and 1 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F0F1_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD3.emiosp->GFR.R;
-
- if (gfr && (1U << 0)) {
- pwm_lld_serve_interrupt1(&PWMD3, 0);
- }
- if (gfr && (1U << 1U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 1U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F2F3_HANDLER)
-#error "SPC5_EMIOS1_GFR_F2F3_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 2 and 3 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F2F3_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD3.emiosp->GFR.R;
-
- if (gfr && (1U << 2U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 2U);
- }
- if (gfr && (1U << 3U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 3U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F4F5_HANDLER)
-#error "SPC5_EMIOS1_GFR_F4F5_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 4 and 5 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F4F5_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD3.emiosp->GFR.R;
-
- if (gfr && (1U << 4U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 4U);
- }
- if (gfr && (1U << 5U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 5U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F6F7_HANDLER)
-#error "SPC5_EMIOS1_GFR_F6F7_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 6 and 7 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F6F7_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD3.emiosp->GFR.R;
-
- if (gfr && (1U << 6U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 6U);
- }
- if (gfr && (1U << 7U)) {
- pwm_lld_serve_interrupt2(&PWMD3, 7U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
-#if !defined(SPC5_EMIOS1_GFR_F8F9_HANDLER)
-#error "SPC5_EMIOS1_GFR_F8F9_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 8 and 9 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F8F9_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD4.emiosp->GFR.R;
-
- if (gfr && (1U << 8U)) {
- pwm_lld_serve_interrupt1(&PWMD4, 8U);
- }
- if (gfr && (1U << 9U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 9U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F10F11_HANDLER)
-#error "SPC5_EMIOS1_GFR_F10F11_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 10 and 11 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F10F11_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD4.emiosp->GFR.R;
-
- if (gfr && (1U << 10U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 10U);
- }
- if (gfr && (1U << 11U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 11U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F12F13_HANDLER)
-#error "SPC5_EMIOS1_GFR_F12F13_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 12 and 13 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F12F13_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD4.emiosp->GFR.R;
-
- if (gfr && (1U << 12U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 12U);
- }
- if (gfr && (1U << 13U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 13U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F14F15_HANDLER)
-#error "SPC5_EMIOS1_GFR_F14F15_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 14 and 15 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F14F15_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD4.emiosp->GFR.R;
-
- if (gfr && (1U << 14U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 14U);
- }
- if (gfr && (1U << 15U)) {
- pwm_lld_serve_interrupt2(&PWMD4, 15U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
-#if !defined(SPC5_EMIOS1_GFR_F16F17_HANDLER)
-#error "SPC5_EMIOS1_GFR_F16F17_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 16 and 17 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F16F17_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD5.emiosp->GFR.R;
-
- if (gfr && (1U << 16U)) {
- pwm_lld_serve_interrupt1(&PWMD5, 16U);
- }
- if (gfr && (1U << 17U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 17U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F18F19_HANDLER)
-#error "SPC5_EMIOS1_GFR_F18F19_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 18 and 19 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F18F19_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD5.emiosp->GFR.R;
-
- if (gfr && (1U << 18U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 18U);
- }
- if (gfr && (1U << 19U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 19U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F20F21_HANDLER)
-#error "SPC5_EMIOS1_GFR_F20F21_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 20 and 21 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F20F21_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD5.emiosp->GFR.R;
-
- if (gfr && (1U << 20U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 20U);
- }
- if (gfr && (1U << 21U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 21U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-
-#if !defined(SPC5_EMIOS1_GFR_F22F23_HANDLER)
-#error "SPC5_EMIOS1_GFR_F22F23_HANDLER not defined"
-#endif
-/**
- * @brief eMIOS1 Channels 22 and 23 interrupt handler.
- * @note It is assumed that the various sources are only activated if the
- * associated callback pointer is not equal to @p NULL in order to not
- * perform an extra check in a potentially critical interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(SPC5_EMIOS1_GFR_F22F23_HANDLER) {
-
- CH_IRQ_PROLOGUE();
-
- uint32_t gfr = PWMD5.emiosp->GFR.R;
-
- if (gfr && (1U << 22U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 22U);
- }
- if (gfr && (1U << 23U)) {
- pwm_lld_serve_interrupt2(&PWMD5, 23U);
- }
-
- CH_IRQ_EPILOGUE();
-}
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level PWM driver initialization.
- *
- * @notapi
- */
-void pwm_lld_init(void) {
- /* eMIOSx channels initially all not in use.*/
- reset_emios0_active_channels();
- reset_emios1_active_channels();
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- /* Driver initialization.*/
- pwmObjectInit(&PWMD1);
- PWMD1.emiosp = &EMIOS_0;
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- /* Driver initialization.*/
- pwmObjectInit(&PWMD2);
- PWMD2.emiosp = &EMIOS_0;
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- /* Driver initialization.*/
- pwmObjectInit(&PWMD3);
- PWMD3.emiosp = &EMIOS_1;
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- /* Driver initialization.*/
- pwmObjectInit(&PWMD4);
- PWMD4.emiosp = &EMIOS_1;
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- /* Driver initialization.*/
- pwmObjectInit(&PWMD5);
- PWMD5.emiosp = &EMIOS_1;
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
-#if SPC5_PWM_USE_EMIOS0
-
- INTC.PSR[SPC5_EMIOS0_GFR_F8F9_NUMBER].R = SPC5_EMIOS0_GFR_F8F9_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F10F11_NUMBER].R = SPC5_EMIOS0_GFR_F10F11_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F12F13_NUMBER].R = SPC5_EMIOS0_GFR_F12F13_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F14F15_NUMBER].R = SPC5_EMIOS0_GFR_F14F15_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F16F17_NUMBER].R = SPC5_EMIOS0_GFR_F16F17_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F18F19_NUMBER].R = SPC5_EMIOS0_GFR_F18F19_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F20F21_NUMBER].R = SPC5_EMIOS0_GFR_F20F21_PRIORITY;
- INTC.PSR[SPC5_EMIOS0_GFR_F22F23_NUMBER].R = SPC5_EMIOS0_GFR_F22F23_PRIORITY;
-
-#endif
-
-#if SPC5_PWM_USE_EMIOS1
-
- INTC.PSR[SPC5_EMIOS1_GFR_F0F1_NUMBER].R = SPC5_EMIOS1_GFR_F0F1_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F2F3_NUMBER].R = SPC5_EMIOS1_GFR_F2F3_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F4F5_NUMBER].R = SPC5_EMIOS1_GFR_F4F5_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F6F7_NUMBER].R = SPC5_EMIOS1_GFR_F6F7_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F8F9_NUMBER].R = SPC5_EMIOS1_GFR_F8F9_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F10F11_NUMBER].R = SPC5_EMIOS1_GFR_F10F11_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F12F13_NUMBER].R = SPC5_EMIOS1_GFR_F12F13_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F14F15_NUMBER].R = SPC5_EMIOS1_GFR_F14F15_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F16F17_NUMBER].R = SPC5_EMIOS1_GFR_F16F17_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F18F19_NUMBER].R = SPC5_EMIOS1_GFR_F18F19_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F20F21_NUMBER].R = SPC5_EMIOS1_GFR_F20F21_PRIORITY;
- INTC.PSR[SPC5_EMIOS1_GFR_F22F23_NUMBER].R = SPC5_EMIOS1_GFR_F22F23_PRIORITY;
-
-#endif
-
-}
-
-/**
- * @brief Configures and activates the PWM peripheral.
- *
- * @param[in] pwmp pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_start(PWMDriver *pwmp) {
-
- uint32_t psc = 0, i = 0;
-
- chDbgAssert(get_emios0_active_channels() < 28,
- "pwm_lld_start(), #1", "too many channels");
- chDbgAssert(get_emios1_active_channels() < 28,
- "pwm_lld_start(), #2", "too many channels");
-
- if (pwmp->state == PWM_STOP) {
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
- increase_emios0_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
- increase_emios0_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
- increase_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
- increase_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
- increase_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
- /* Set eMIOS0 Clock.*/
-#if SPC5_PWM_USE_EMIOS0
- active_emios0_clock(NULL, pwmp);
-#endif
-
- /* Set eMIOS1 Clock.*/
-#if SPC5_PWM_USE_EMIOS1
- active_emios1_clock(NULL, pwmp);
-#endif
-
- }
- /* Configures the peripheral.*/
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[8U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[16U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~1U;
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[0].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[8U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[16U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- }
-#endif
-
- /* Set clock prescaler and control register.*/
- if (pwmp->emiosp == &EMIOS_0) {
- psc = (SPC5_EMIOS0_CLK / pwmp->config->frequency);
- chDbgAssert((psc <= 0xFFFF) &&
- (((psc) * pwmp->config->frequency) == SPC5_EMIOS0_CLK) &&
- ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
- "pwm_lld_start(), #1", "invalid frequency");
- } else if (pwmp->emiosp == &EMIOS_1) {
- psc = (SPC5_EMIOS1_CLK / pwmp->config->frequency);
- chDbgAssert((psc <= 0xFFFF) &&
- (((psc) * pwmp->config->frequency) == SPC5_EMIOS1_CLK) &&
- ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),
- "pwm_lld_start(), #2", "invalid frequency");
- }
-
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
-
- pwmp->emiosp->CH[8U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[8U].CCNTR.R = 1U;
- pwmp->emiosp->CH[8U].CADR.R = pwmp->config->period;
- pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
- pwmp->emiosp->CH[8U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
- pwmp->emiosp->CH[8U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_UCPREN;
-
- if (pwmp->config->mode == PWM_ALIGN_EDGE) {
- for (i = 0; i < PWM_CHANNELS; i++) {
- switch (pwmp->config->channels[i].mode) {
- case PWM_OUTPUT_DISABLED:
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 9U].CADR.R = 0;
- pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 9U].CADR.R = 1U;
- pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 9U].CCR.R &= ~EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
- break;
- }
- }
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << 8U);
-
- }
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
-
- pwmp->emiosp->CH[16U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[16U].CCNTR.R = 1U;
- pwmp->emiosp->CH[16U].CADR.R = pwmp->config->period;
- pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
- pwmp->emiosp->CH[16U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
- pwmp->emiosp->CH[16U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_UCPREN;
-
- if (pwmp->config->mode == PWM_ALIGN_EDGE) {
- for (i = 0; i < PWM_CHANNELS; i++) {
- switch (pwmp->config->channels[i].mode) {
- case PWM_OUTPUT_DISABLED:
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 17U].CADR.R = 0;
- pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 17U].CADR.R = 1U;
- pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 17U].CCR.R &= ~EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
- break;
- }
- }
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << 16U);
-
- }
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
-
- pwmp->emiosp->CH[0].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[0].CCNTR.R = 1U;
- pwmp->emiosp->CH[0].CADR.R = pwmp->config->period;
- pwmp->emiosp->CH[0].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
- pwmp->emiosp->CH[0].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
- pwmp->emiosp->CH[0].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[0].CCR.R |= EMIOSC_UCPREN;
-
- if (pwmp->config->mode == PWM_ALIGN_EDGE) {
- for (i = 0; i < PWM_CHANNELS; i++) {
- switch (pwmp->config->channels[i].mode) {
- case PWM_OUTPUT_DISABLED:
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (1U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 1U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 1U].CADR.R = 0;
- pwmp->emiosp->CH[i + 1U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 1U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 1U));
-
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (1U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 1U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 1U].CADR.R = 1U;
- pwmp->emiosp->CH[i + 1U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 1U].CCR.R &= ~EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 1U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 1U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 1U));
-
- break;
- }
- }
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= 1U;
-
- }
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
-
- pwmp->emiosp->CH[8U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[8U].CCNTR.R = 1U;
- pwmp->emiosp->CH[8U].CADR.R = pwmp->config->period;
- pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
- pwmp->emiosp->CH[8U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
- pwmp->emiosp->CH[8U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[8U].CCR.R |= EMIOSC_UCPREN;
-
- if (pwmp->config->mode == PWM_ALIGN_EDGE) {
- for (i = 0; i < PWM_CHANNELS; i++) {
- switch (pwmp->config->channels[i].mode) {
- case PWM_OUTPUT_DISABLED:
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 9U].CADR.R = 0;
- pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 9U].CADR.R = 1U;
- pwmp->emiosp->CH[i + 9U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 9U].CCR.R &= ~EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 9U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 9U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 9U));
-
- break;
- }
- }
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << 8U);
-
- }
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
-
- pwmp->emiosp->CH[16U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[16U].CCNTR.R = 1U;
- pwmp->emiosp->CH[16U].CADR.R = pwmp->config->period;
- pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER);
- pwmp->emiosp->CH[16U].CCR.R |= EMIOS_CCR_MODE_MCB_UP;
- pwmp->emiosp->CH[16U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[16U].CCR.R |= EMIOSC_UCPREN;
-
- if (pwmp->config->mode == PWM_ALIGN_EDGE) {
- for (i = 0; i < PWM_CHANNELS; i++) {
- switch (pwmp->config->channels[i].mode) {
- case PWM_OUTPUT_DISABLED:
- break;
- case PWM_OUTPUT_ACTIVE_HIGH:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 17U].CADR.R = 0;
- pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
- break;
- case PWM_OUTPUT_ACTIVE_LOW:
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + i));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[i + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPEN = 0;
- pwmp->emiosp->CH[i + 17U].CADR.R = 1U;
- pwmp->emiosp->CH[i + 17U].CBDR.R = 0;
-
- /* Set output polarity.*/
- pwmp->emiosp->CH[i + 17U].CCR.R &= ~EMIOSC_EDPOL;
-
- /* Set unified channel mode.*/
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_BSL(EMIOS_BSL_COUNTER_BUS_2);
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOS_CCR_MODE_OPWMB;
-
- pwmp->emiosp->CH[i + 17U].CCR.B.UCPRE = psc - 1U;
- pwmp->emiosp->CH[i + 17U].CCR.R |= EMIOSC_UCPREN;
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << (i + 17U));
-
- break;
- }
- }
-
- /* Channel disables.*/
- pwmp->emiosp->UCDIS.R |= (1U << 16U);
-
- }
- }
-#endif
-
-}
-
-/**
- * @brief Deactivates the PWM peripheral.
- *
- * @param[in] pwmp pointer to the @p PWMDriver object
- *
- * @notapi
- */
-void pwm_lld_stop(PWMDriver *pwmp) {
-
- uint32_t i = 0;
-
- chDbgAssert(get_emios0_active_channels() < 28, "pwm_lld_stop(), #1",
- "too many channels");
- chDbgAssert(get_emios1_active_channels() < 28, "pwm_lld_stop(), #2",
- "too many channels");
-
- if (pwmp->state == PWM_READY) {
-
- /* Disables the peripheral.*/
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
- /* Reset UC Control Register of group channels.*/
- for (i = 0; i < 8; i++) {
- pwmp->emiosp->CH[i + 8U].CCR.R = 0;
- }
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
- /* Reset UC Control Register of group channels.*/
- for (i = 0; i < 8; i++) {
- pwmp->emiosp->CH[i + 16U].CCR.R = 0;
- }
- decrease_emios0_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS0_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
- /* Reset UC Control Register of group channels.*/
- for (i = 0; i < 8; i++) {
- pwmp->emiosp->CH[i].CCR.R = 0;
- }
- decrease_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP0 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
- /* Reset UC Control Register of group channels.*/
- for (i = 0; i < 8; i++) {
- pwmp->emiosp->CH[i + 8U].CCR.R = 0;
- }
- decrease_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP1 */
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
- /* Reset UC Control Register of group channels.*/
- for (i = 0; i < 8; i++) {
- pwmp->emiosp->CH[i + 16U].CCR.R = 0;
- }
- decrease_emios1_active_channels();
- }
-#endif /* SPC5_PWM_USE_EMIOS1_GROUP2 */
-
- /* eMIOS0 clock deactivation.*/
-#if SPC5_PWM_USE_EMIOS0
- deactive_emios0_clock(NULL, pwmp);
-#endif
-
- /* eMIOS1 clock deactivation.*/
-#if SPC5_PWM_USE_EMIOS1
- deactive_emios1_clock(NULL, pwmp);
-#endif
- }
-}
-
-/**
- * @brief Changes the period the PWM peripheral.
- * @details This function changes the period of a PWM unit that has already
- * been activated using @p pwmStart().
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The PWM unit period is changed to the new value.
- * @note The function has effect at the next cycle start.
- * @note If a period is specified that is shorter than the pulse width
- * programmed in one of the channels then the behavior is not
- * guaranteed.
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] period new cycle time in ticks
- *
- * @notapi
- */
-void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
- pwmp->period = period;
- pwmp->emiosp->CH[8U].CADR.R = period;
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
- pwmp->period = period;
- pwmp->emiosp->CH[16U].CADR.R = period;
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
- pwmp->period = period;
- pwmp->emiosp->CH[0].CADR.R = period;
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
- pwmp->period = period;
- pwmp->emiosp->CH[8U].CADR.R = period;
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
- pwmp->period = period;
- pwmp->emiosp->CH[16U].CADR.R = period;
- }
-#endif
-
-}
-
-/**
- * @brief Enables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is active using the specified configuration.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- * @param[in] width PWM pulse width as clock pulses number
- *
- * @notapi
- */
-void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width) {
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + channel));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- /* Set PWM width.*/
- pwmp->emiosp->CH[channel + 9U].CBDR.R = width;
-
- /* Active interrupts.*/
- if (pwmp->config->channels[channel].callback != NULL) {
- pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 1U;
- }
-
- /* Enables timer base channel if disable.*/
- if (pwmp->emiosp->UCDIS.R & (1U << 8U)) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
- /* Active interrupts.*/
- if (pwmp->config->callback != NULL ) {
- pwmp->emiosp->CH[8U].CCR.B.FEN = 1U;
- }
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + channel));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- /* Set PWM width.*/
- pwmp->emiosp->CH[channel + 17U].CBDR.R = width;
-
- /* Active interrupts.*/
- if (pwmp->config->channels[channel].callback != NULL) {
- pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 1U;
- }
-
- /* Enables timer base channel if disable.*/
- if (pwmp->emiosp->UCDIS.R & (1U << 16U)) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
- /* Active interrupts.*/
- if (pwmp->config->callback != NULL ) {
- pwmp->emiosp->CH[16U].CCR.B.FEN = 1U;
- }
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (1U + channel));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 1U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- /* Set PWM width.*/
- pwmp->emiosp->CH[channel + 1U].CBDR.R = width;
-
-
- /* Active interrupts.*/
- if (pwmp->config->channels[channel].callback != NULL) {
- pwmp->emiosp->CH[channel + 1U].CCR.B.FEN = 1U;
- }
-
- /* Enables timer base channel if disable.*/
- if (pwmp->emiosp->UCDIS.R & 1U) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~1U;
-
- /* Active interrupts.*/
- if (pwmp->config->callback != NULL ) {
- pwmp->emiosp->CH[0].CCR.B.FEN = 1U;
- }
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (9U + channel));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- /* Set PWM width.*/
- pwmp->emiosp->CH[channel + 9U].CBDR.R = width;
-
- /* Active interrupts.*/
- if (pwmp->config->channels[channel].callback != NULL) {
- pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 1U;
- }
-
- /* Enables timer base channel if disable.*/
- if (pwmp->emiosp->UCDIS.R & (1U << 8U)) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 8U);
-
- /* Active interrupts.*/
- if (pwmp->config->callback != NULL ) {
- pwmp->emiosp->CH[8U].CCR.B.FEN = 1U;
- }
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
-
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << (17U + channel));
-
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC | EMIOSS_OVFLC |
- EMIOSS_FLAGC;
-
- /* Set PWM width.*/
- pwmp->emiosp->CH[channel + 17U].CBDR.R = width;
-
- /* Active interrupts.*/
- if (pwmp->config->channels[channel].callback != NULL) {
- pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 1U;
- }
-
- /* Enables timer base channel if disable.*/
- if (pwmp->emiosp->UCDIS.R & (1U << 16U)) {
- /* Channel enables.*/
- pwmp->emiosp->UCDIS.R &= ~(1U << 16U);
-
- /* Active interrupts.*/
- if (pwmp->config->callback != NULL ) {
- pwmp->emiosp->CH[16U].CCR.B.FEN = 1U;
- }
- }
-
- }
-#endif
-
-}
-
-/**
- * @brief Disables a PWM channel.
- * @pre The PWM unit must have been activated using @p pwmStart().
- * @post The channel is disabled and its output line returned to the
- * idle state.
- * @note Depending on the hardware implementation this function has
- * effect starting on the next cycle (recommended implementation)
- * or immediately (fallback implementation).
- *
- * @param[in] pwmp pointer to a @p PWMDriver object
- * @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
- *
- * @notapi
- */
-void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0
- if (&PWMD1 == pwmp) {
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << (channel + 9U));
-
- /* Disable timer base channel if all PWM channels are disabled.*/
- if ((pwmp->emiosp->UCDIS.R & (0xFE << 8U)) == (0xFE << 8U)) {
- /* Deactive interrupts.*/
- pwmp->emiosp->CH[8U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << 8U);
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1
- if (&PWMD2 == pwmp) {
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << (channel + 17));
-
- /* Disable timer base channel if all PWM channels are disabled.*/
- if ((pwmp->emiosp->UCDIS.R & (0xFE << 16U)) == (0xFE << 16U)) {
- /* Deactive interrupts.*/
- pwmp->emiosp->CH[16U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << 16U);
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0
- if (&PWMD3 == pwmp) {
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 1U].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- pwmp->emiosp->CH[channel + 1U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << (channel + 1U));
-
- /* Disable timer base channel if all PWM channels are disabled.*/
- if ((pwmp->emiosp->UCDIS.R & 0xFE) == 0xFE) {
- /* Deactive interrupts.*/
- pwmp->emiosp->CH[0].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= 1U;
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1
- if (&PWMD4 == pwmp) {
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 9U].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- pwmp->emiosp->CH[channel + 9U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << (channel + 9U));
-
- /* Disable timer base channel if all PWM channels are disabled.*/
- if ((pwmp->emiosp->UCDIS.R & (0xFE << 8U)) == (0xFE << 8U)) {
- /* Deactive interrupts.*/
- pwmp->emiosp->CH[8U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << 8U);
- }
-
- }
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2
- if (&PWMD5 == pwmp) {
- /* Clear pending IRQs (if any).*/
- pwmp->emiosp->CH[channel + 17U].CSR.R = EMIOSS_OVRC |
- EMIOSS_OVFLC | EMIOSS_FLAGC;
-
- /* Disable interrupts.*/
- pwmp->emiosp->CH[channel + 17U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << (channel + 17U));
-
- /* Disable timer base channel if all PWM channels are disabled.*/
- if ((pwmp->emiosp->UCDIS.R & (0xFE << 16U)) == (0xFE << 16U)) {
- /* Deactive interrupts.*/
- pwmp->emiosp->CH[16U].CCR.B.FEN = 0;
-
- /* Disable channel.*/
- pwmp->emiosp->UCDIS.R |= (1U << 16U);
- }
-
- }
-#endif
-
-}
-
-#endif /* HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h b/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h deleted file mode 100644 index e2dc403a8..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/pwm_lld.h +++ /dev/null @@ -1,420 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/pwm_lld.h
- * @brief SPC5xx low level PWM driver header.
- *
- * @addtogroup PWM
- * @{
- */
-
-#ifndef _PWM_LLD_H_
-#define _PWM_LLD_H_
-
-#if HAL_USE_PWM || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Number of PWM channels per PWM driver.
- */
-#define PWM_CHANNELS 7
-
-/**
- * @brief Edge-Aligned PWM functional mode.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_EDGE 0x00
-
-/**
- * @brief Center-Aligned PWM functional mode.
- * @note This is an SPC5-specific setting.
- */
-#define PWM_ALIGN_CENTER 0x01
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-#if SPC5_HAS_EMIOS0 || defined(__DOXYGEN__)
-/**
- * @brief PWMD1 driver enable switch.
- * @details If set to @p TRUE the support for PWMD1 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS0_GROUP0) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS0__GROUP0 FALSE
-#endif
-
-/**
- * @brief PWMD2 driver enable switch.
- * @details If set to @p TRUE the support for PWMD2 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS0_GROUP1) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS0_GROUP1 FALSE
-#endif
-
-/**
- * @brief PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F8F9_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F10F11_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F12F13_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD1 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F14F15_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F16F17_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F18F19_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F20F21_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD2 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS0_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_GFR_F22F23_PRIORITY 7
-#endif
-#endif
-
-#if SPC5_HAS_EMIOS1 || defined(__DOXYGEN__)
-/**
- * @brief PWMD3 driver enable switch.
- * @details If set to @p TRUE the support for PWMD3 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS1_GROUP0) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS1_GROUP0 FALSE
-#endif
-
-/**
- * @brief PWMD4 driver enable switch.
- * @details If set to @p TRUE the support for PWMD4 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS1_GROUP1) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS1_GROUP1 FALSE
-#endif
-
-/**
- * @brief PWMD5 driver enable switch.
- * @details If set to @p TRUE the support for PWMD5 is included.
- * @note The default is @p FALSE.
- */
-#if !defined(SPC5_PWM_USE_EMIOS1_GROUP2) || defined(__DOXYGEN__)
-#define SPC5_PWM_USE_EMIOS1_GROUP2 FALSE
-#endif
-
-/**
- * @brief PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F0F1_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F0F1_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F2F3_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F2F3_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F4F5_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F4F5_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD3 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F6F7_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F6F7_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F8F9_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F10F11_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F12F13_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD4 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F14F15_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F16F17_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F18F19_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F20F21_PRIORITY 7
-#endif
-
-/**
- * @brief PWMD5 interrupt priority level setting.
- */
-#if !defined(SPC5_EMIOS1_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_GFR_F22F23_PRIORITY 7
-#endif
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if !SPC5_HAS_EMIOS0
-#error "EMIOS0 not present in the selected device"
-#endif
-
-#if !SPC5_HAS_EMIOS1
-#error "EMIOS1 not present in the selected device"
-#endif
-
-#define SPC5_PWM_USE_EMIOS0 (SPC5_PWM_USE_EMIOS0_GROUP0 || \
- SPC5_PWM_USE_EMIOS0_GROUP1)
-
-#define SPC5_PWM_USE_EMIOS1 (SPC5_PWM_USE_EMIOS1_GROUP0 || \
- SPC5_PWM_USE_EMIOS1_GROUP1 || \
- SPC5_PWM_USE_EMIOS1_GROUP2)
-
-#if !SPC5_PWM_USE_EMIOS0 && !SPC5_PWM_USE_EMIOS1
-#error "PWM driver activated but no Channels assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief PWM mode type.
- */
-typedef uint32_t pwmmode_t;
-
-/**
- * @brief PWM channel type.
- */
-typedef uint8_t pwmchannel_t;
-
-/**
- * @brief PWM counter type.
- */
-typedef uint32_t pwmcnt_t;
-
-/**
- * @brief PWM driver channel configuration structure.
- * @note Some architectures may not be able to support the channel mode
- * or the callback, in this case the fields are ignored.
- */
-typedef struct {
- /**
- * @brief Channel active logic level.
- */
- pwmmode_t mode;
- /**
- * @brief Channel callback pointer.
- * @note This callback is invoked on the channel compare event. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /* End of the mandatory fields.*/
-} PWMChannelConfig;
-
-/**
- * @brief Driver configuration structure.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-typedef struct {
- /**
- * @brief Timer clock in Hz.
- * @note The low level can use assertions in order to catch invalid
- * frequency specifications.
- */
- uint32_t frequency;
- /**
- * @brief PWM period in ticks.
- * @note The low level can use assertions in order to catch invalid
- * period specifications.
- */
- pwmcnt_t period;
- /**
- * @brief Periodic callback pointer.
- * @note This callback is invoked on PWM counter reset. If set to
- * @p NULL then the callback is disabled.
- */
- pwmcallback_t callback;
- /**
- * @brief Channels configurations.
- */
- PWMChannelConfig channels[PWM_CHANNELS];
- /* End of the mandatory fields.*/
- /**
- * @brief PWM functional mode.
- */
- pwmmode_t mode;
-} PWMConfig;
-
-/**
- * @brief Structure representing an PWM driver.
- * @note Implementations may extend this structure to contain more,
- * architecture dependent, fields.
- */
-struct PWMDriver {
- /**
- * @brief Driver state.
- */
- pwmstate_t state;
- /**
- * @brief Current configuration data.
- */
- const PWMConfig *config;
- /**
- * @brief Current PWM period in ticks.
- */
- pwmcnt_t period;
-#if defined(PWM_DRIVER_EXT_FIELDS)
- PWM_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the eMIOSx registers block.
- */
- volatile struct EMIOS_tag *emiosp;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if SPC5_PWM_USE_EMIOS0_GROUP0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD1;
-#endif
-
-#if SPC5_PWM_USE_EMIOS0_GROUP1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD2;
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP0 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD3;
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP1 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD4;
-#endif
-
-#if SPC5_PWM_USE_EMIOS1_GROUP2 && !defined(__DOXYGEN__)
-extern PWMDriver PWMD5;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void pwm_lld_init(void);
- void pwm_lld_start(PWMDriver *pwmp);
- void pwm_lld_stop(PWMDriver *pwmp);
- void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
- void pwm_lld_enable_channel(PWMDriver *pwmp,
- pwmchannel_t channel,
- pwmcnt_t width);
- void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_PWM */
-
-#endif /* _PWM_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c deleted file mode 100644 index 20ce38773..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c +++ /dev/null @@ -1,195 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/spc5_emios.c
- * @brief SPC5xx low level ICU and PWM drivers common code.
- *
- * @addtogroup ICU - PWM
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
-
-#include "spc5_emios.h"
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief Number of active eMIOSx Channels.
- */
-static uint32_t emios0_active_channels;
-static uint32_t emios1_active_channels;
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-void reset_emios0_active_channels() {
- emios0_active_channels = 0;
-}
-
-void reset_emios1_active_channels() {
- emios1_active_channels = 0;
-}
-
-uint32_t get_emios0_active_channels() {
- return emios0_active_channels;
-}
-
-uint32_t get_emios1_active_channels() {
- return emios1_active_channels;
-}
-
-void increase_emios0_active_channels() {
- emios0_active_channels++;
-}
-
-void decrease_emios0_active_channels() {
- emios0_active_channels--;
-}
-
-void increase_emios1_active_channels() {
- emios1_active_channels++;
-}
-
-void decrease_emios1_active_channels() {
- emios1_active_channels--;
-}
-
-void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
- /* If this is the first Channel activated then the eMIOS0 is enabled.*/
- if (emios0_active_channels == 1) {
- halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
- SPC5_EMIOS0_START_PCTL);
-
- /* Disable all unified channels.*/
- if (icup != NULL) {
- icup->emiosp->MCR.B.GPREN = 0;
- icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
- icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- icup->emiosp->MCR.B.GTBE = 1U;
-
- icup->emiosp->UCDIS.R = 0xFFFFFFFF;
-
- } else if (pwmp != NULL) {
- pwmp->emiosp->MCR.B.GPREN = 0;
- pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);
- pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- pwmp->emiosp->MCR.B.GTBE = 1U;
-
- pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
-
- }
-
- }
-}
-
-void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
- /* If this is the first Channel activated then the eMIOS1 is enabled.*/
- if (emios1_active_channels == 1) {
- halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
- SPC5_EMIOS1_START_PCTL);
-
- /* Disable all unified channels.*/
- if (icup != NULL) {
- icup->emiosp->MCR.B.GPREN = 0;
- icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
- icup->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- icup->emiosp->MCR.B.GTBE = 1U;
-
- icup->emiosp->UCDIS.R = 0xFFFFFFFF;
-
- } else if (pwmp != NULL) {
- pwmp->emiosp->MCR.B.GPREN = 0;
- pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);
- pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;
-
- pwmp->emiosp->MCR.B.GTBE = 1U;
-
- pwmp->emiosp->UCDIS.R = 0xFFFFFFFF;
-
- }
-
- }
-}
-
-void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
- /* If it is the last active channels then the eMIOS0 is disabled.*/
- if (emios0_active_channels == 0) {
- if (icup != NULL) {
- if (icup->emiosp->UCDIS.R == 0) {
- //icup->emiosp->MCR.B.MDIS = 0;
- halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
- SPC5_EMIOS0_STOP_PCTL);
- }
- } else if (pwmp != NULL) {
- if (pwmp->emiosp->UCDIS.R == 0) {
- //pwmp->emiosp->MCR.B.MDIS = 0;
- halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,
- SPC5_EMIOS0_STOP_PCTL);
- }
- }
- }
-}
-
-void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
- /* If it is the last active channels then the eMIOS1 is disabled.*/
- if (emios1_active_channels == 0) {
- if (icup != NULL) {
- if (icup->emiosp->UCDIS.R == 0) {
- //icup->emiosp->MCR.B.MDIS = 0;
- halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
- SPC5_EMIOS1_STOP_PCTL);
- }
- } else if (pwmp != NULL) {
- if (pwmp->emiosp->UCDIS.R == 0) {
- //pwmp->emiosp->MCR.B.MDIS = 0;
- halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,
- SPC5_EMIOS1_STOP_PCTL);
- }
- }
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-
-#endif /* HAL_USE_ICU || HAL_USE_PWM */
-
-/** @} */
diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h deleted file mode 100644 index 946db2400..000000000 --- a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.h +++ /dev/null @@ -1,169 +0,0 @@ -/*
- SPC5 HAL - Copyright (C) 2013 STMicroelectronics
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file eMIOS_v1/spc5_emios.h
- * @brief SPC5xx low level ICU - PWM driver common header.
- *
- * @addtogroup ICU - PWM
- * @{
- */
-
-#ifndef _SPC5_EMIOS_H_
-#define _SPC5_EMIOS_H_
-
-#if HAL_USE_ICU || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-#define EMIOSMCR_MDIS (1U << 30U)
-#define EMIOSMCR_FRZ (1U << 29U)
-#define EMIOSMCR_GTBE (1U << 28U)
-#define EMIOSMCR_GPREN (1U << 26U)
-#define EMIOSMCR_GPRE(n) ((n) << 8U)
-
-#define EMIOSC_FREN (1U << 31U)
-#define EMIOSC_UCPRE(n) ((n) << 26U)
-#define EMIOSC_UCPREN (1U << 25U)
-#define EMIOSC_DMA (1U << 24U)
-#define EMIOSC_IF(n) ((n) << 19U)
-#define EMIOSC_FCK (1U << 18U)
-#define EMIOSC_FEN (1U << 17U)
-#define EMIOSC_FORCMA (1U << 13U)
-#define EMIOSC_FORCMB (1U << 12U)
-#define EMIOSC_BSL(n) ((n) << 9U)
-#define EMIOSC_EDSEL (1U << 8U)
-#define EMIOSC_EDPOL (1U << 7U)
-#define EMIOSC_MODE(n) ((n) << 0)
-
-#define EMIOS_BSL_COUNTER_BUS_A 0
-#define EMIOS_BSL_COUNTER_BUS_2 1U
-#define EMIOS_BSL_INTERNAL_COUNTER 3U
-
-#define EMIOS_CCR_MODE_GPIO_IN 0
-#define EMIOS_CCR_MODE_GPIO_OUT 1U
-#define EMIOS_CCR_MODE_SAIC 2U
-#define EMIOS_CCR_MODE_SAOC 3U
-#define EMIOS_CCR_MODE_IPWM 4U
-#define EMIOS_CCR_MODE_IPM 5U
-#define EMIOS_CCR_MODE_DAOC_B_MATCH 6U
-#define EMIOS_CCR_MODE_DAOC_BOTH_MATCH 7U
-#define EMIOS_CCR_MODE_MC_CMS 16U
-#define EMIOS_CCR_MODE_MC_CME 17U
-#define EMIOS_CCR_MODE_MC_UP_DOWN 18U
-#define EMIOS_CCR_MODE_OPWMT 38U
-#define EMIOS_CCR_MODE_MCB_UP 80U
-#define EMIOS_CCR_MODE_MCB_UP_DOWN 84U
-#define EMIOS_CCR_MODE_OPWFMB 88U
-#define EMIOS_CCR_MODE_OPWMCB_TE 92U
-#define EMIOS_CCR_MODE_OPWMCB_LE 93U
-#define EMIOS_CCR_MODE_OPWMB 96U
-
-#define EMIOSS_OVR (1U << 31U)
-#define EMIOSS_OVRC (1U << 31U)
-#define EMIOSS_OVFL (1U << 15U)
-#define EMIOSS_OVFLC (1U << 15U)
-#define EMIOSS_FLAG (1U << 0)
-#define EMIOSS_FLAGC (1U << 0)
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-#if SPC5_HAS_EMIOS0
-/**
- * @brief eMIOS0 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS0_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief eMIOS0 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS0_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-#endif
-
-#if SPC5_HAS_EMIOS1
-/**
- * @brief eMIOS1 peripheral configuration when started.
- * @note The default configuration is 1 (always run) in run mode and
- * 2 (only halt) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS1_START_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
- SPC5_ME_PCTL_LP(2))
-#endif
-
-/**
- * @brief eMIOS1 peripheral configuration when stopped.
- * @note The default configuration is 0 (never run) in run mode and
- * 0 (never run) in low power mode. The defaults of the run modes
- * are defined in @p hal_lld.h.
- */
-#if !defined(SPC5_EMIOS1_STOP_PCTL) || defined(__DOXYGEN__)
-#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
- SPC5_ME_PCTL_LP(0))
-#endif
-#endif
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-void reset_emios0_active_channels(void);
-void reset_emios1_active_channels(void);
-uint32_t get_emios0_active_channels(void);
-uint32_t get_emios1_active_channels(void);
-void increase_emios0_active_channels(void);
-void decrease_emios0_active_channels(void);
-void increase_emios1_active_channels(void);
-void decrease_emios1_active_channels(void);
-void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp);
-void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp);
-void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp);
-void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp);
-
-#endif /* HAL_USE_ICU */
-
-#endif /* _SPC5_EMIOS_H_ */
-
-/** @} */
|