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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-12 16:26:56 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-12 16:26:56 +0000 |
| commit | c246d898d2d2c16972182dab3e7201c359c8b7da (patch) | |
| tree | 5b7bffe17908f133f213b36ae5ab9d50ac899aae | |
| parent | d7b170b525754e5fc502c32d796dfa594775fd0e (diff) | |
| download | ChibiOS-c246d898d2d2c16972182dab3e7201c359c8b7da.tar.gz ChibiOS-c246d898d2d2c16972182dab3e7201c359c8b7da.tar.bz2 ChibiOS-c246d898d2d2c16972182dab3e7201c359c8b7da.zip | |
New STM32F3xx CMSIS headers.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8587 35acf78f-673a-0410-8e92-d51de3d6d3f4
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f301x8.h | 359 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f302x8.h | 398 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f302xc.h | 436 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f302xe.h | 7856 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f303x8.h | 398 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f303xc.h | 391 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f303xe.h | 8346 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f318xx.h | 350 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f328xx.h | 384 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f334x8.h | 422 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f358xx.h | 362 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f373xc.h | 286 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f378xx.h | 252 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f398xx.h | 8139 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/stm32f3xx.h | 54 | ||||
| -rw-r--r-- | os/ext/CMSIS/ST/system_stm32f3xx.h | 6 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F3xx/hal_lld.h | 3 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F3xx/stm32_isr.h | 5 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F3xx/stm32_registry.h | 777 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 1 | ||||
| -rw-r--r-- | readme.txt | 1 |
21 files changed, 27407 insertions, 1819 deletions
diff --git a/os/ext/CMSIS/ST/stm32f301x8.h b/os/ext/CMSIS/ST/stm32f301x8.h index 24ba4edac..40f595ae5 100644 --- a/os/ext/CMSIS/ST/stm32f301x8.h +++ b/os/ext/CMSIS/ST/stm32f301x8.h @@ -2,9 +2,9 @@ ******************************************************************************
* @file stm32f301x8.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
- * @brief CMSIS STM32F301x6/STM32F301x8 Devices Peripheral Access Layer Header File.
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F301x8 Devices Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
@@ -14,7 +14,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,11 +63,11 @@ /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 0 /*!< STM32F301x6/STM32F301x8 devices do not provide an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F301x6/STM32F301x8 devices use 4 Bits for the Priority Levels */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< STM32F301x8 devices do not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F301x8 devices use 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< STM32F301x6/STM32F301x8 devices provide an FPU */
+#define __FPU_PRESENT 1 /*!< STM32F301x8 devices provide an FPU */
/**
* @}
@@ -78,7 +78,7 @@ */
/**
- * @brief STM32F301x6/STM32F301x8 device Interrupt Number Definition, according to the selected device
+ * @brief STM32F301x8 devices Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
@@ -129,12 +129,12 @@ typedef enum EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel1 underrun error Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */
I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -235,20 +235,20 @@ typedef struct typedef struct
{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
__IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
__IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
/**
@@ -277,8 +277,8 @@ typedef struct typedef struct
{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
@@ -287,20 +287,20 @@ typedef struct typedef struct
{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
- __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
- __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
- __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
- __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
- __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
}EXTI_TypeDef;
/**
@@ -348,11 +348,10 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
- __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
}GPIO_TypeDef;
/**
@@ -370,10 +369,10 @@ typedef struct typedef struct
{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
- __IO uint32_t RESERVED0; /*!< Reserved, 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
} SYSCFG_TypeDef;
/**
@@ -480,6 +479,10 @@ typedef struct __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
} RTC_TypeDef;
@@ -489,13 +492,13 @@ typedef struct typedef struct
{
- __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
- __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
@@ -531,7 +534,6 @@ typedef struct __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
} TIM_TypeDef;
-
/**
* @brief Touch Sensing Controller (TSC)
*/
@@ -591,7 +593,6 @@ typedef struct #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
@@ -663,7 +664,7 @@ typedef struct #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
#define ADC1_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
/**
* @}
*/
@@ -688,13 +689,13 @@ typedef struct #define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define COMP ((COMP_TypeDef *) COMP_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
@@ -722,6 +723,7 @@ typedef struct #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+
/**
* @}
*/
@@ -743,6 +745,7 @@ typedef struct /* Analog to Digital Converter SAR (ADC) */
/* */
/******************************************************************************/
+
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
@@ -1521,6 +1524,7 @@ typedef struct /* Analog Comparators (COMP) */
/* */
/******************************************************************************/
+
/********************** Bit definition for COMP2_CSR register ***************/
#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
#define COMP2_CSR_COMP2INPDAC ((uint32_t)0x00000002) /*!< COMP2 non inverting input to DAC output */
@@ -1673,7 +1677,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -1718,7 +1722,6 @@ typedef struct #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
-
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
@@ -1884,7 +1887,7 @@ typedef struct /* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
-/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
+/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
@@ -1914,8 +1917,11 @@ typedef struct #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
+/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
@@ -1945,8 +1951,11 @@ typedef struct #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
+/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
@@ -1970,14 +1979,11 @@ typedef struct #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
@@ -2001,14 +2007,11 @@ typedef struct #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
@@ -2032,14 +2035,11 @@ typedef struct #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
-
-/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
@@ -2063,12 +2063,37 @@ typedef struct #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
/******************************************************************************/
/* */
@@ -2133,6 +2158,11 @@ typedef struct #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -2162,6 +2192,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -2476,7 +2507,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -2490,6 +2521,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -2509,9 +2543,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -2833,8 +2875,8 @@ typedef struct #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
-#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
/***************** Bit definition for RCC_APB2ENR register ******************/
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
@@ -2954,10 +2996,12 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
@@ -2976,16 +3020,12 @@ typedef struct #define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
-
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
-
#define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
#define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
-
#define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
#define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
-
#define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
#define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
@@ -2993,7 +3033,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -3002,7 +3042,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -3371,8 +3411,20 @@ typedef struct /******************** Bits definition for RTC_BKP15R register ***************/
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
+#define RTC_BKP_NUMBER 20
/******************************************************************************/
/* */
@@ -3471,7 +3523,7 @@ typedef struct /* System Configuration(SYSCFG) */
/* */
/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -3480,7 +3532,7 @@ typedef struct #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00003800) /*!< DMA remap mask */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
@@ -3675,9 +3727,9 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
-/***************** Bit definition for SYSCFG_CFGR2 register *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
-#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
/******************************************************************************/
/* */
@@ -3942,7 +3994,7 @@ typedef struct #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
@@ -4498,11 +4550,23 @@ typedef struct ((INSTANCE) == DMA1_Channel7))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
/****************************** I2C Instances *********************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
@@ -4513,12 +4577,12 @@ typedef struct #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
-
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -4566,12 +4630,12 @@ typedef struct /****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
-
+ ((INSTANCE) == TIM1)
+
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : supporting clock selection ****************/
@@ -4614,7 +4678,7 @@ typedef struct /****************** TIM Instances : supporting Hall interface *****************/
#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : supporting input XOR function *************/
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
@@ -4650,8 +4714,8 @@ typedef struct #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM15) || \
- ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting the break function *************/
@@ -4725,11 +4789,11 @@ typedef struct /****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : supporting DMA generation on Update events*/
#define IS_TIM_DMA_INSTANCE(INSTANCE)\
@@ -4787,7 +4851,7 @@ typedef struct /******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
-
+
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
@@ -4796,7 +4860,7 @@ typedef struct ((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
-/****************** UART Instances : Auto Baud Rate detection *****************/
+/****************** UART Instances : Driver Enable ****************************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
@@ -4807,6 +4871,8 @@ typedef struct /*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
@@ -4824,27 +4890,34 @@ typedef struct /******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+#define COMP1_2_IRQn COMP2_IRQn
+#define COMP1_2_3_IRQn COMP2_IRQn
+#define COMP_IRQn COMP2_IRQn
+#define COMP4_5_6_IRQn COMP4_6_IRQn
+#define HRTIM1_FLT_IRQn I2C3_ER_IRQn
+#define HRTIM1_TIME_IRQn I2C3_EV_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
-#define ADC1_2_IRQn ADC1_IRQn
-#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM16_IRQn TIM1_UP_TIM16_IRQn
-#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define COMP_IRQn COMP2_IRQn
-#define COMP1_2_IRQn COMP2_IRQn
-#define COMP1_2_3_IRQn COMP2_IRQn
-#define COMP4_5_6_IRQn COMP4_6_IRQn
-#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_2_IRQHandler ADC1_IRQHandler
-#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define COMP_IRQHandler COMP2_IRQHandler
-#define COMP1_2_IRQHandler COMP2_IRQHandler
-#define COMP1_2_3_IRQHandler COMP2_IRQHandler
-#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
-#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+#define COMP1_2_IRQHandler COMP2_IRQHandler
+#define COMP1_2_3_IRQHandler COMP2_IRQHandler
+#define COMP_IRQHandler COMP2_IRQHandler
+#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
+#define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
+#define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+
#ifdef __cplusplus
}
diff --git a/os/ext/CMSIS/ST/stm32f302x8.h b/os/ext/CMSIS/ST/stm32f302x8.h index d48373590..005a36916 100644 --- a/os/ext/CMSIS/ST/stm32f302x8.h +++ b/os/ext/CMSIS/ST/stm32f302x8.h @@ -2,9 +2,9 @@ ******************************************************************************
* @file stm32f302x8.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
- * @brief CMSIS STM32F302x6/STM32F302x8 Devices Peripheral Access Layer Header File.
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F302x8 Devices Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
@@ -14,7 +14,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,11 +63,11 @@ /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 0 /*!< STM32F302x6/STM32F302x8 devices do not provide an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F302x6/STM32F302x8 devices use 4 Bits for the Priority Levels */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< STM32F302x8 devices do not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F302x8 devices use 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< STM32F302x6/STM32F302x8 devices provide an FPU */
+#define __FPU_PRESENT 1 /*!< STM32F302x8 devices provide an FPU */
/**
* @}
@@ -78,7 +78,7 @@ */
/**
- * @brief STM32F302x6/STM32F302x8 device Interrupt Number Definition, according to the selected device
+ * @brief STM32F302x8 devices Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
@@ -134,15 +134,15 @@ typedef enum RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel1 underrun error Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */
I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
- USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
- USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -303,20 +303,20 @@ typedef struct typedef struct
{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
__IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
__IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
/**
@@ -345,8 +345,8 @@ typedef struct typedef struct
{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
@@ -355,20 +355,20 @@ typedef struct typedef struct
{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
- __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
- __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
- __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
- __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
- __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
}EXTI_TypeDef;
/**
@@ -416,11 +416,10 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
- __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
}GPIO_TypeDef;
/**
@@ -438,10 +437,10 @@ typedef struct typedef struct
{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
- __IO uint32_t RESERVED0; /*!< Reserved, 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
} SYSCFG_TypeDef;
/**
@@ -548,6 +547,10 @@ typedef struct __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
} RTC_TypeDef;
@@ -557,13 +560,13 @@ typedef struct typedef struct
{
- __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
- __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
@@ -599,7 +602,6 @@ typedef struct __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
} TIM_TypeDef;
-
/**
* @brief Touch Sensing Controller (TSC)
*/
@@ -673,9 +675,9 @@ typedef struct __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
- __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
- __IO uint16_t RESERVEDD; /*!< Reserved */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
} USB_TypeDef;
/**
@@ -695,7 +697,6 @@ typedef struct #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
@@ -770,7 +771,7 @@ typedef struct #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
#define ADC1_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
/**
* @}
*/
@@ -796,13 +797,13 @@ typedef struct #define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define COMP ((COMP_TypeDef *) COMP_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
@@ -831,6 +832,7 @@ typedef struct #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
#define USB ((USB_TypeDef *) USB_BASE)
+
/**
* @}
*/
@@ -852,6 +854,7 @@ typedef struct /* Analog to Digital Converter SAR (ADC) */
/* */
/******************************************************************************/
+
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
@@ -1630,6 +1633,7 @@ typedef struct /* Analog Comparators (COMP) */
/* */
/******************************************************************************/
+
/********************** Bit definition for COMP2_CSR register ***************/
#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
#define COMP2_CSR_COMP2INPDAC ((uint32_t)0x00000002) /*!< COMP2 non inverting input to DAC output */
@@ -3038,7 +3042,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -3083,7 +3087,6 @@ typedef struct #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
-
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
@@ -3139,6 +3142,7 @@ typedef struct #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x40000000)
+#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
/******************** Bit definition for DBGMCU_APB2_FZ register ************/
#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
@@ -3249,7 +3253,7 @@ typedef struct /* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
-/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
+/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
@@ -3279,8 +3283,11 @@ typedef struct #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
+/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
@@ -3310,8 +3317,11 @@ typedef struct #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
+/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
@@ -3335,14 +3345,11 @@ typedef struct #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
@@ -3366,14 +3373,11 @@ typedef struct #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
@@ -3397,14 +3401,11 @@ typedef struct #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
-
-/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
@@ -3428,12 +3429,37 @@ typedef struct #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
/******************************************************************************/
/* */
@@ -3498,6 +3524,11 @@ typedef struct #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -3527,6 +3558,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -3841,7 +3873,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -3855,6 +3887,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -3874,9 +3909,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -4206,8 +4249,8 @@ typedef struct #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
-#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
/***************** Bit definition for RCC_APB2ENR register ******************/
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
@@ -4329,10 +4372,12 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
@@ -4351,16 +4396,12 @@ typedef struct #define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
-
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
-
#define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
#define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
-
#define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
#define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
-
#define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
#define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
@@ -4368,7 +4409,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -4377,7 +4418,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -4746,8 +4787,20 @@ typedef struct /******************** Bits definition for RTC_BKP15R register ***************/
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
+#define RTC_BKP_NUMBER 20
/******************************************************************************/
/* */
@@ -4846,7 +4899,7 @@ typedef struct /* System Configuration(SYSCFG) */
/* */
/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -4856,7 +4909,7 @@ typedef struct #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00003800) /*!< DMA remap mask */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
@@ -5051,9 +5104,9 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
-/***************** Bit definition for SYSCFG_CFGR2 register *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
-#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
/******************************************************************************/
/* */
@@ -5318,7 +5371,7 @@ typedef struct #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
@@ -5804,7 +5857,7 @@ typedef struct /**************************** ISTR interrupt events *************************/
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
@@ -5815,8 +5868,11 @@ typedef struct #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+/* Legacy defines */
+#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
+
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
@@ -5825,9 +5881,12 @@ typedef struct #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+/* Legacy defines */
+#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
+
/************************* CNTR control register bits definitions ***********/
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
@@ -5838,10 +5897,14 @@ typedef struct #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
-#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+/* Legacy defines */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
+#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
+
/*************************** LPM register bits definitions ******************/
#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
@@ -5995,11 +6058,23 @@ typedef struct ((INSTANCE) == DMA1_Channel7))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
/****************************** I2C Instances *********************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
@@ -6010,12 +6085,12 @@ typedef struct #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
-
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -6063,12 +6138,12 @@ typedef struct /****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
-
+ ((INSTANCE) == TIM1)
+
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : supporting clock selection ****************/
@@ -6111,7 +6186,7 @@ typedef struct /****************** TIM Instances : supporting Hall interface *****************/
#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : supporting input XOR function *************/
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
@@ -6147,8 +6222,8 @@ typedef struct #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM15) || \
- ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting the break function *************/
@@ -6222,11 +6297,11 @@ typedef struct /****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : supporting DMA generation on Update events*/
#define IS_TIM_DMA_INSTANCE(INSTANCE)\
@@ -6284,7 +6359,7 @@ typedef struct /******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
-
+
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
@@ -6293,7 +6368,7 @@ typedef struct ((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
-/****************** UART Instances : Auto Baud Rate detection *****************/
+/****************** UART Instances : Driver Enable ****************************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
@@ -6304,6 +6379,8 @@ typedef struct /*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
/****************************** USB Instances *********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
@@ -6324,31 +6401,42 @@ typedef struct /******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+#define COMP1_2_IRQn COMP2_IRQn
+#define COMP1_2_3_IRQn COMP2_IRQn
+#define COMP_IRQn COMP2_IRQn
+#define COMP4_5_6_IRQn COMP4_6_IRQn
+#define HRTIM1_FLT_IRQn I2C3_ER_IRQn
+#define HRTIM1_TIME_IRQn I2C3_EV_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define USBWakeUp_IRQn USBWakeUp_RMP_IRQn
+#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
+#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
-#define ADC1_2_IRQn ADC1_IRQn
-#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
-#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
-#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM16_IRQn TIM1_UP_TIM16_IRQn
-#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define COMP_IRQn COMP2_IRQn
-#define COMP1_2_IRQn COMP2_IRQn
-#define COMP1_2_3_IRQn COMP2_IRQn
-#define COMP4_5_6_IRQn COMP4_6_IRQn
-#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_2_IRQHandler ADC1_IRQHandler
-#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
-#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
-#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define COMP_IRQHandler COMP2_IRQHandler
-#define COMP1_2_IRQHandler COMP2_IRQHandler
-#define COMP1_2_3_IRQHandler COMP2_IRQHandler
-#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
-#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+#define COMP1_2_IRQHandler COMP2_IRQHandler
+#define COMP1_2_3_IRQHandler COMP2_IRQHandler
+#define COMP_IRQHandler COMP2_IRQHandler
+#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
+#define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
+#define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler
+#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
+#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
+
#ifdef __cplusplus
}
diff --git a/os/ext/CMSIS/ST/stm32f302xc.h b/os/ext/CMSIS/ST/stm32f302xc.h index d6a9d0082..f002cca46 100644 --- a/os/ext/CMSIS/ST/stm32f302xc.h +++ b/os/ext/CMSIS/ST/stm32f302xc.h @@ -2,9 +2,9 @@ ******************************************************************************
* @file stm32f302xc.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
- * @brief CMSIS STM32F302xB/STM32F302xC Devices Peripheral Access Layer Header File.
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F302xC Devices Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
@@ -14,7 +14,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,11 +63,11 @@ /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32F302xB/STM32F302xC devices provide an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F302xB/STM32F302xC devices use 4 Bits for the Priority Levels */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F302xC devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F302xC devices use 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< STM32F302xB/STM32F302xC devices provide an FPU */
+#define __FPU_PRESENT 1 /*!< STM32F302xC devices provide an FPU */
/**
* @}
@@ -78,7 +78,7 @@ */
/**
- * @brief STM32F302xB/STM32F302xC device Interrupt Number Definition, according to the selected device
+ * @brief STM32F302xC devices Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
@@ -139,7 +139,7 @@ typedef enum SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error Interrupts */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
@@ -147,10 +147,10 @@ typedef enum DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
COMP1_2_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt via EXTI Line21 and 22 */
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
- USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
- USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -316,14 +316,14 @@ typedef struct __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
@@ -353,8 +353,8 @@ typedef struct typedef struct
{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
@@ -363,20 +363,20 @@ typedef struct typedef struct
{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
- __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
- __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
- __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
- __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
- __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
}EXTI_TypeDef;
/**
@@ -424,11 +424,10 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
- __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
}GPIO_TypeDef;
/**
@@ -446,10 +445,10 @@ typedef struct typedef struct
{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
- __IO uint32_t RESERVED0; /*!< Reserved, 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
} SYSCFG_TypeDef;
/**
@@ -565,13 +564,13 @@ typedef struct typedef struct
{
- __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
- __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
@@ -680,7 +679,7 @@ typedef struct __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
- __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
} USB_TypeDef;
/**
@@ -700,7 +699,6 @@ typedef struct #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
@@ -789,7 +787,7 @@ typedef struct #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
/**
* @}
*/
@@ -816,17 +814,17 @@ typedef struct #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define CAN ((CAN_TypeDef *) CAN_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
-#define COMP ((COMP_TypeDef *) COMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
-#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
@@ -864,6 +862,7 @@ typedef struct #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
#define USB ((USB_TypeDef *) USB_BASE)
+
/**
* @}
*/
@@ -885,6 +884,7 @@ typedef struct /* Analog to Digital Converter SAR (ADC) */
/* */
/******************************************************************************/
+
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
@@ -1663,6 +1663,7 @@ typedef struct /* Analog Comparators (COMP) */
/* */
/******************************************************************************/
+
/********************** Bit definition for COMP1_CSR register ***************/
#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
@@ -1796,7 +1797,6 @@ typedef struct #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
-#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
@@ -3160,7 +3160,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -3205,31 +3205,8 @@ typedef struct #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
-#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
-#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
-#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
-#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
-
-#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
-#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-
-#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
-
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
@@ -3240,36 +3217,20 @@ typedef struct /****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
-/***************** Bit definition for DAC_DHR12R2 register ******************/
-#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12L2 register ******************/
-#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8R2 register ******************/
-#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
-
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
-/******************* Bit definition for DAC_DOR2 register *******************/
-#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
-
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
/******************************************************************************/
/* */
@@ -3411,7 +3372,7 @@ typedef struct /* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
-/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
+/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
@@ -3441,8 +3402,11 @@ typedef struct #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
+/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
@@ -3472,8 +3436,11 @@ typedef struct #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
+/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
@@ -3497,14 +3464,11 @@ typedef struct #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
@@ -3528,14 +3492,11 @@ typedef struct #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
@@ -3559,14 +3520,11 @@ typedef struct #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
-
-/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
@@ -3590,12 +3548,37 @@ typedef struct #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
/******************************************************************************/
/* */
@@ -3660,6 +3643,11 @@ typedef struct #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -3689,6 +3677,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -4003,7 +3992,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -4017,6 +4006,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -4036,9 +4028,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -4309,7 +4309,7 @@ typedef struct #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
-#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
/********************* Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
@@ -4370,7 +4370,7 @@ typedef struct #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
/***************** Bit definition for RCC_APB2ENR register ******************/
@@ -4427,6 +4427,7 @@ typedef struct /******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
@@ -4498,10 +4499,12 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
@@ -4511,10 +4514,8 @@ typedef struct #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
#define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
#define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
-
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000300) /*!< TIMSW bits */
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
-
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
@@ -4522,7 +4523,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -4531,7 +4532,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -4540,7 +4541,7 @@ typedef struct #define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART4 clock source */
#define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
#define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
#define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
@@ -4549,7 +4550,7 @@ typedef struct #define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART5 clock source */
#define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
#define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
#define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
@@ -4919,7 +4920,7 @@ typedef struct #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
+#define RTC_BKP_NUMBER 16
/******************************************************************************/
/* */
@@ -5018,7 +5019,7 @@ typedef struct /* System Configuration(SYSCFG) */
/* */
/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -5029,7 +5030,7 @@ typedef struct #define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
@@ -5223,10 +5224,10 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
-/***************** Bit definition for SYSCFG_CFGR2 register *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
-#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
@@ -5493,7 +5494,7 @@ typedef struct #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
@@ -5574,13 +5575,6 @@ typedef struct #define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
#define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-/******************* Bit definition for TIM8_OR register *********************/
-#define TIM8_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
-#define TIM8_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
-#define TIM8_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
-#define TIM8_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
-#define TIM8_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
-
/****************** Bit definition for TIM_CCMR3 register *******************/
#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
@@ -5984,7 +5978,7 @@ typedef struct /**************************** ISTR interrupt events *************************/
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
@@ -5994,8 +5988,11 @@ typedef struct #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+/* Legacy defines */
+#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
+
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
@@ -6003,9 +6000,12 @@ typedef struct #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+/* Legacy defines */
+#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
+
/************************* CNTR control register bits definitions ***********/
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
@@ -6014,10 +6014,14 @@ typedef struct #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
-#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+/* Legacy defines */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
+#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
+
/******************** FNR Frame Number Register bit definitions ************/
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
@@ -6129,11 +6133,10 @@ typedef struct /****************************** ADC Instances *********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2))
-
+
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_2_COMMON)
-
/****************************** CAN Instances *********************************/
#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
@@ -6158,9 +6161,8 @@ typedef struct #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
- (((INSTANCE) == DAC1) && \
- (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2)))
+ (((INSTANCE) == DAC1) && \
+ ((CHANNEL) == DAC_CHANNEL_1))
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -6177,12 +6179,23 @@ typedef struct ((INSTANCE) == DMA2_Channel5))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOE) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOD))
/****************************** I2C Instances *********************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
@@ -6192,13 +6205,13 @@ typedef struct #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
-
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2))
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -6256,12 +6269,12 @@ typedef struct /****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
-
+ ((INSTANCE) == TIM1)
+
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : supporting clock selection ****************/
@@ -6318,7 +6331,7 @@ typedef struct /****************** TIM Instances : supporting Hall interface *****************/
#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : supporting input XOR function *************/
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
@@ -6349,8 +6362,8 @@ typedef struct #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM15))
@@ -6362,10 +6375,10 @@ typedef struct #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM15) || \
- ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting the break function *************/
@@ -6455,7 +6468,7 @@ typedef struct /****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
@@ -6524,7 +6537,7 @@ typedef struct ((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
-
+
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
@@ -6566,6 +6579,12 @@ typedef struct ((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4))
+
/****************************** USB Instances *********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
@@ -6586,31 +6605,38 @@ typedef struct /******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define COMP1_2_3_IRQn COMP1_2_IRQn
+#define COMP2_IRQn COMP1_2_IRQn
+#define COMP_IRQn COMP1_2_IRQn
+#define COMP4_5_6_IRQn COMP4_6_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define USBWakeUp_IRQn USBWakeUp_RMP_IRQn
+#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
+#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
-#define ADC1_IRQn ADC1_2_IRQn
-#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
-#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
-#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM16_IRQn TIM1_UP_TIM16_IRQn
-#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define COMP_IRQn COMP1_2_IRQn
-#define COMP2_IRQn COMP1_2_IRQn
-#define COMP1_2_3_IRQn COMP1_2_IRQn
-#define COMP4_5_6_IRQn COMP4_6_IRQn
-#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
-#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
-#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define COMP_IRQHandler COMP1_2_IRQHandler
-#define COMP2_IRQHandler COMP1_2_IRQHandler
-#define COMP1_2_3_IRQHandler COMP1_2_IRQHandler
-#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
-#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define COMP1_2_3_IRQHandler COMP1_2_IRQHandler
+#define COMP2_IRQHandler COMP1_2_IRQHandler
+#define COMP_IRQHandler COMP1_2_IRQHandler
+#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler
+#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
+#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
+
#ifdef __cplusplus
}
diff --git a/os/ext/CMSIS/ST/stm32f302xe.h b/os/ext/CMSIS/ST/stm32f302xe.h new file mode 100644 index 000000000..b33ca5c86 --- /dev/null +++ b/os/ext/CMSIS/ST/stm32f302xe.h @@ -0,0 +1,7856 @@ +/**
+ ******************************************************************************
+ * @file stm32f302xe.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F302xE Devices Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f302xe
+ * @{
+ */
+
+#ifndef __STM32F302xE_H
+#define __STM32F302xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F302xE devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F302xE devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F302xE devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F302xE devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
+ USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ COMP1_2_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt via EXTI Line21 and 22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
+ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
+
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
+ uint16_t RESERVED0; /*!< Reserved, 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
+ __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
+ __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
+} OPAMP_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED0; /*!< Reserved, 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
+} TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED1; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED2; /*!< Reserved, 0x2A */
+} USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
+} USB_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FMC_BASE ((uint32_t)0x60000000) /*!< FMC base address */
+#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+#define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
+#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
+#define DAC_BASE DAC1_BASE
+#define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
+#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
+#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
+#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
+#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
+#define COMP_BASE COMP1_BASE
+#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
+#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
+#define OPAMP_BASE OPAMP1_BASE
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
+#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
+#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
+#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
+#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
+#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
+#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
+#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+#define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800)
+#define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00)
+
+/*!< AHB3 peripherals */
+#define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
+#define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
+#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
+
+/*!< FMC Bankx base address */
+#define FMC_BANK1 (FMC_BASE) /*!< FMC Bank1 base address */
+#define FMC_BANK1_1 (FMC_BANK1) /*!< FMC Bank1_1 base address */
+#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000) /*!< FMC Bank1_2 base address */
+#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000) /*!< FMC Bank1_3 base address */
+#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000) /*!< FMC Bank1_4 base address */
+
+#define FMC_BANK2 (FMC_BASE + 0x10000000) /*!< FMC Bank2 base address */
+#define FMC_BANK3 (FMC_BASE + 0x20000000) /*!< FMC Bank3 base address */
+#define FMC_BANK4 (FMC_BASE + 0x30000000) /*!< FMC Bank4 base address */
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN ((CAN_TypeDef *) CAN_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
+#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
+#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter SAR (ADC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_ISR register ********************/
+#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
+#define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
+
+/******************** Bit definition for ADC_IER register ********************/
+#define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
+#define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
+#define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
+#define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
+#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
+
+/******************** Bit definition for ADC_CFGR register ********************/
+#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
+#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
+
+#define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
+#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
+
+#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
+
+#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
+#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
+#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
+#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
+
+#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
+#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
+
+#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
+#define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
+#define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
+#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
+#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
+#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
+
+#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
+#define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
+#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
+#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
+#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
+#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
+
+/******************** Bit definition for ADC_SMPR1 register ********************/
+#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
+#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
+#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
+#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
+
+#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
+#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
+#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
+#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
+
+#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
+#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
+#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
+#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
+
+#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
+#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
+#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
+#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
+
+#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
+#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
+#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
+#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
+
+#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
+#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
+#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
+#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
+
+#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
+#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
+#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
+#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
+
+#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
+#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
+#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
+#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
+
+#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
+#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
+#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
+#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
+
+#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
+#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
+#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
+#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
+
+/******************** Bit definition for ADC_SMPR2 register ********************/
+#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
+#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
+#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
+#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
+
+#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
+#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
+#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
+#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
+
+#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
+#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
+#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
+#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
+
+#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
+#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
+#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
+#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
+
+#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
+#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
+#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
+#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
+
+#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
+#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
+#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
+#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
+
+#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
+#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
+#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
+#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
+
+#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
+#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
+#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
+#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
+
+#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
+#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
+#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
+#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
+
+/******************** Bit definition for ADC_TR1 register ********************/
+#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
+#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
+#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
+#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
+#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
+#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
+#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
+#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
+#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
+#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
+#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
+#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
+#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
+
+#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
+#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
+#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
+#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
+#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
+#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
+#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
+#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
+#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
+#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
+#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
+#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
+#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
+
+/******************** Bit definition for ADC_TR2 register ********************/
+#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
+#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
+#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
+#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
+#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
+#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
+#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
+#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
+#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
+
+#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
+#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
+#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
+#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
+#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
+#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
+#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
+#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
+#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
+
+/******************** Bit definition for ADC_TR3 register ********************/
+#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
+#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
+#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
+#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
+#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
+#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
+#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
+#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
+#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
+
+#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
+#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
+#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
+#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
+#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
+#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
+#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
+#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
+#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
+
+/******************** Bit definition for ADC_SQR1 register ********************/
+#define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
+
+#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
+#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
+#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
+#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
+#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
+
+#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
+#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
+#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
+#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
+#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
+
+#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
+#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
+#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
+#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
+#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
+
+#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
+#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
+#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
+#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
+#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
+
+/******************** Bit definition for ADC_SQR2 register ********************/
+#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
+#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
+#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
+#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
+#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
+
+#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
+#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
+#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
+#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
+#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
+
+#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
+
+#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
+
+#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
+
+/******************** Bit definition for ADC_SQR3 register ********************/
+#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
+#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
+#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
+#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
+#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
+
+#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
+#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
+#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
+#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
+#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
+
+#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
+#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
+#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
+#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
+#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
+
+#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
+#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
+#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
+#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
+#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
+
+#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
+#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
+#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
+#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
+#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
+
+/******************** Bit definition for ADC_SQR4 register ********************/
+#define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
+#define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
+#define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
+#define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
+#define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
+
+#define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
+#define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
+#define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
+#define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
+#define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
+#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
+#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
+#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
+#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
+#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
+#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
+#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
+#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
+#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
+#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
+#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
+#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
+#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
+#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
+#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
+#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
+
+/******************** Bit definition for ADC_JSQR register ********************/
+#define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
+
+#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
+#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
+#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
+#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
+
+#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
+#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
+
+#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
+
+/******************** Bit definition for ADC_OFR1 register ********************/
+#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
+#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
+#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
+#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
+#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
+#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
+#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
+#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
+#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
+#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
+#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
+#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
+
+#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
+#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
+#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
+#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
+#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
+
+#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
+
+/******************** Bit definition for ADC_OFR2 register ********************/
+#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
+#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
+#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
+#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
+#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
+#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
+#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
+#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
+#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
+#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
+#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
+#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
+
+#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
+#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
+#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
+#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
+#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
+
+#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
+
+/******************** Bit definition for ADC_OFR3 register ********************/
+#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
+#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
+#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
+#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
+#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
+#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
+#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
+#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
+#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
+#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
+#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
+#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
+
+#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
+#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
+#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
+#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
+#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
+
+#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
+
+/******************** Bit definition for ADC_OFR4 register ********************/
+#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
+#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
+#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
+#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
+#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
+#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
+#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
+#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
+#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
+#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
+#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
+#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
+
+#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
+#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
+#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
+#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
+#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
+
+#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
+
+/******************** Bit definition for ADC_JDR1 register ********************/
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR2 register ********************/
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR3 register ********************/
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR4 register ********************/
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_AWD2CR register ********************/
+#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
+#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
+#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
+#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
+#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
+#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
+#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
+#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
+#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
+#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
+#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
+#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
+#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
+#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
+#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
+#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
+#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
+#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
+
+/******************** Bit definition for ADC_AWD3CR register ********************/
+#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
+#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
+#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
+#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
+#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
+#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
+#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
+#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
+#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
+#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
+#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
+#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
+#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
+#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
+#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
+#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
+#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
+#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
+
+/******************** Bit definition for ADC_DIFSEL register ********************/
+#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
+#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
+#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
+#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
+#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
+#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
+#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
+#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
+#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
+#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
+#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
+#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
+#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
+#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
+#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
+#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
+#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
+#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
+#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
+#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
+#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
+#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
+#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
+#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
+#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
+#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
+#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
+#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
+#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
+#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
+#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC12_CSR register ********************/
+#define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
+#define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
+#define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
+#define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
+#define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
+#define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
+#define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
+#define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
+#define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
+#define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
+
+/******************** Bit definition for ADC_CCR register ********************/
+#define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
+#define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
+#define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
+#define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
+#define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
+#define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
+#define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
+#define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
+#define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
+#define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
+#define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
+#define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
+#define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
+#define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
+#define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
+#define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
+#define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
+#define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
+#define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
+#define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
+#define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
+
+/******************** Bit definition for ADC_CDR register ********************/
+#define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
+#define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
+#define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
+#define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
+#define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
+#define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
+#define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
+#define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
+#define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
+#define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
+#define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
+#define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
+#define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
+#define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
+#define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
+#define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
+
+#define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
+#define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
+#define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
+#define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
+#define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
+#define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
+#define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
+#define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
+#define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
+#define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
+#define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
+#define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
+#define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
+#define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
+#define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
+#define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+
+/********************** Bit definition for COMP1_CSR register ***************/
+#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
+#define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */
+#define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
+#define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
+#define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
+#define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
+#define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */
+#define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */
+#define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
+#define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
+#define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
+#define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */
+#define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
+
+/********************** Bit definition for COMP2_CSR register ***************/
+#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
+#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
+#define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
+#define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
+#define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
+#define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */
+#define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
+#define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
+#define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
+#define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
+#define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
+#define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
+#define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
+#define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
+#define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
+#define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
+#define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/********************** Bit definition for COMP4_CSR register ***************/
+#define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
+#define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */
+#define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
+#define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
+#define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
+#define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */
+#define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
+#define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
+#define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
+#define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
+#define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
+#define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
+#define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
+#define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
+#define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
+#define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
+#define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
+#define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
+
+/********************** Bit definition for COMP6_CSR register ***************/
+#define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
+#define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */
+#define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
+#define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
+#define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
+#define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */
+#define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
+#define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
+#define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
+#define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
+#define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
+#define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
+#define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
+#define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
+#define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
+#define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
+#define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
+#define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
+
+/********************** Bit definition for COMP_CSR register ****************/
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
+#define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
+#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /*!< COMPx window mode enable */
+#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
+#define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
+#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
+#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
+#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
+#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
+
+/******************************************************************************/
+/* */
+/* Operational Amplifier (OPAMP) */
+/* */
+/******************************************************************************/
+/********************* Bit definition for OPAMP1_CSR register ***************/
+#define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */
+#define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP2_CSR register ***************/
+#define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
+#define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMPx_CSR register ***************/
+#define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network (CAN ) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
+#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x40000000)
+#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+#define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
+#define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
+#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCRx register *******************/
+#define FMC_BCRx_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCRx_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCRx_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCRx_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCRx_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCRx_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCRx_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCRx_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCRx_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCRx_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCRx_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCRx_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCRx_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCRx_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCRx_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCRx_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTRx register ******************/
+#define FMC_BTRx_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTRx_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTRx_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTRx_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTRx_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTRx_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTRx_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTRx_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTRx_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTRx_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTRx_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTRx_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTRx_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTRx_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTRx register ******************/
+#define FMC_BWTRx_ADDSETx ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSETx_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTRx_ADDSETx_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTRx_ADDSETx_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTRx_ADDSETx_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTRx_ADDHLDx ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLDx_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTRx_ADDHLDx_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTRx_ADDHLDx_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTRx_ADDHLDx_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTRx_DATASTx ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATASTx_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTRx_DATASTx_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTRx_DATASTx_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTRx_DATASTx_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTRx_DATASTx_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTRx_DATASTx_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTRx_DATASTx_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTRx_DATASTx_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTRx_ACCMODx ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMODx_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTRx_ACCMODx_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
+#define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCRx register *******************/
+#define FMC_PCRx_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCRx_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCRx_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCRx_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCRx_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCRx_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCRx_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCRx_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCRx_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCRx_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCRx_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCRx_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCRx_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCRx_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCRx_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCRx_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCRx_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCRx_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCRx_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCRx_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCRx_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+#define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+#define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+#define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SRx register *******************/
+#define FMC_SRx_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SRx_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SRx_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SRx_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SRx_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SRx_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SRx_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR2 register *******************/
+#define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR3 register *******************/
+#define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR4 register *******************/
+#define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEMx register ******************/
+#define FMC_PMEMx_MEMSETx ((uint32_t)0x000000FF) /*!<MEMSETx[7:0] bits (Common memory x setup time) */
+#define FMC_PMEMx_MEMSETx_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEMx_MEMSETx_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEMx_MEMSETx_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEMx_MEMSETx_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEMx_MEMSETx_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEMx_MEMSETx_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEMx_MEMSETx_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEMx_MEMSETx_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEMx_MEMWAITx ((uint32_t)0x0000FF00) /*!<MEMWAITx[7:0] bits (Common memory x wait time) */
+#define FMC_PMEMx_MEMWAITx_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEMx_MEMHOLDx ((uint32_t)0x00FF0000) /*!<MEMHOLDx[7:0] bits (Common memory x hold time) */
+#define FMC_PMEMx_MEMHOLDx_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEMx_MEMHOLDx_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEMx_MEMHOLDx_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEMx_MEMHOLDx_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEMx_MEMHOLDx_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEMx_MEMHOLDx_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEMx_MEMHOLDx_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEMx_MEMHOLDx_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEMx_MEMHIZx ((uint32_t)0xFF000000) /*!<MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
+#define FMC_PMEMx_MEMHIZx_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEMx_MEMHIZx_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEMx_MEMHIZx_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEMx_MEMHIZx_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEMx_MEMHIZx_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEMx_MEMHIZx_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEMx_MEMHIZx_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEMx_MEMHIZx_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+#define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+#define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+#define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATTx register ******************/
+#define FMC_PATTx_ATTSETx ((uint32_t)0x000000FF) /*!<ATTSETx[7:0] bits (Attribute memory x setup time) */
+#define FMC_PATTx_ATTSETx_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATTx_ATTSETx_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATTx_ATTSETx_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATTx_ATTSETx_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATTx_ATTSETx_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATTx_ATTSETx_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATTx_ATTSETx_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATTx_ATTSETx_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATTx_ATTWAITx ((uint32_t)0x0000FF00) /*!<ATTWAITx[7:0] bits (Attribute memory x wait time) */
+#define FMC_PATTx_ATTWAITx_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATTx_ATTWAITx_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATTx_ATTWAITx_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATTx_ATTWAITx_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATTx_ATTWAITx_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATTx_ATTWAITx_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATTx_ATTWAITx_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATTx_ATTWAITx_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATTx_ATTHOLDx ((uint32_t)0x00FF0000) /*!<ATTHOLDx[7:0] bits (Attribute memory x hold time) */
+#define FMC_PATTx_ATTHOLDx_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATTx_ATTHOLDx_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATTx_ATTHOLDx_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATTx_ATTHOLDx_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATTx_ATTHOLDx_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATTx_ATTHOLDx_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATTx_ATTHOLDx_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATTx_ATTHOLDx_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATTx_ATTHIZx ((uint32_t)0xFF000000) /*!<ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
+#define FMC_PATTx_ATTHIZx_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATTx_ATTHIZx_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATTx_ATTHIZx_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATTx_ATTHIZx_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATTx_ATTHIZx_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATTx_ATTHIZx_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATTx_ATTHIZx_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATTx_ATTHIZx_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+#define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+#define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+#define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+#define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+#define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register ********************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< USB configuration */
+#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
+
+#define RCC_CFGR_USBPRE_DIV1_5 ((uint32_t)0x00000000) /*!< USB prescaler is PLL clock divided by 1.5 */
+#define RCC_CFGR_USBPRE_DIV1 ((uint32_t)0x00400000) /*!< USB prescaler is PLL clock divided by 1 */
+
+/*!< I2S configuration */
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
+
+#define RCC_CFGR_I2SSRC_SYSCLK ((uint32_t)0x00000000) /*!< System clock selected as I2S clock source */
+#define RCC_CFGR_I2SSRC_EXT ((uint32_t)0x00800000) /*!< External clock selected as I2S clock source */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
+
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
+
+/********************* Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/****************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00008000) /*!< SPI4 reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
+
+/****************** Bit definition for RCC_APB1RSTR register ******************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
+#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
+#define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_FMCEN ((uint32_t)0x00000020) /*!< FMC clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00010000) /*!< GPIOH clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+#define RCC_AHBENR_GPIOGEN ((uint32_t)0x00800000) /*!< GPIOG clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
+#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00008000) /*!< SPI4 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+
+/****************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
+#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+#define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+#define RCC_AHBRSTR_FMCRST ((uint32_t)0x00000020) /*!< FMC reset */
+#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00010000) /*!< GPIOH reset */
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
+#define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00800000) /*!< GPIOG reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
+#define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */
+#define RCC_AHBRSTR_ADC34RST ((uint32_t)0x20000000) /*!< ADC3 & ADC4 reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
+
+/*!< ADCPRE12 configuration */
+#define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
+#define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+#define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
+
+#define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
+#define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
+#define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
+#define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
+#define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
+#define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
+#define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
+#define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
+#define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
+#define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
+#define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
+#define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
+#define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
+
+/******************* Bit definition for RCC_CFGR3 register ******************/
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
+
+#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+#define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
+#define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
+#define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
+#define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
+#define RCC_CFGR3_I2C3SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C3 clock source */
+#define RCC_CFGR3_I2C3SW_SYSCLK ((uint32_t)0x00000040) /*!< System clock selected as I2C3 clock source */
+
+#define RCC_CFGR3_TIMSW ((uint32_t)0x0000AF00) /*!< TIMSW bits */
+#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
+#define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
+#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
+#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
+#define RCC_CFGR3_TIM2SW ((uint32_t)0x01000000) /*!< TIM2SW bits */
+#define RCC_CFGR3_TIM34SW ((uint32_t)0x02000000) /*!< TIM34SW bits */
+#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
+#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
+#define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
+#define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
+#define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
+#define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
+#define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
+#define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
+
+#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
+#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
+
+#define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
+#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
+#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
+
+#define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */
+#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
+#define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
+
+#define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */
+#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
+#define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
+
+#define RCC_CFGR3_TIM2SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM2 clock source */
+#define RCC_CFGR3_TIM2SW_PLL ((uint32_t)0x01000000) /*!< PLL clock used as TIM2 clock source */
+
+#define RCC_CFGR3_TIM34SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM3/TIM4 clock source */
+#define RCC_CFGR3_TIM34SW_PLL ((uint32_t)0x02000000) /*!< PLL clock used as TIM3/TIM4 clock source */
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 16
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration(SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_CFGR1_MEM_MODE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */
+#define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
+#define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
+#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00003900) /*!< DMA remap mask */
+#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
+#define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
+#define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
+#define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x01000000) /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
+#define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
+#define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
+#define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
+#define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
+#define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
+#define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
+
+/*!<*
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!< PH[0] pin */
+
+/*!<*
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!< PH[1] pin */
+
+/*!<*
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */
+
+/*!<*
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
+
+/*!<*
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!< PH[4] pin */
+
+/*!<*
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */
+
+/*!<*
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */
+
+/*!<*
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
+
+/*!<*
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */
+
+/*!<*
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */
+
+/*!<*
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */
+
+/*!<*
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
+
+/*!<*
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */
+
+/*!<*
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */
+
+/*!<*
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */
+
+/*!<*
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
+#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
+#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+#define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+#define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_CCR5 register *******************/
+#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
+
+/******************* Bit definition for TIM_CCR6 register *******************/
+#define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM16_OR register *********************/
+#define TIM16_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
+#define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+/******************* Bit definition for TIM1_OR register *********************/
+#define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
+#define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR3 register *******************/
+#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
+#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
+#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
+
+#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+
+#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+
+#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
+#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
+#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+#define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
+#define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* USB Device General registers */
+/* */
+/******************************************************************************/
+#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
+#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
+#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
+#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
+#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
+#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+
+/* Legacy defines */
+#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+
+/* Legacy defines */
+#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
+
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+
+/* Legacy defines */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
+#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
+
+/*************************** LPM register bits definitions ******************/
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
+
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
+
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
+
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_2_COMMON)
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
+
+/****************************** COMP Instances ********************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2) || \
+ ((INSTANCE) == COMP4) || \
+ ((INSTANCE) == COMP6))
+
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
+ ((INSTANCE) == COMP4) || \
+ ((INSTANCE) == COMP6))
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
+ (((INSTANCE) == DAC1) && \
+ ((CHANNEL) == DAC_CHANNEL_1))
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************************** I2S Instances *********************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+ ((INSTANCE) == OPAMP2))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+/******************* TIM Instances : All supported instances ******************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/******************* TIM Instances : at least 1 capture/compare channel *******/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : at least 2 capture/compare channels *******/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : at least 3 capture/compare channels *******/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+/****************** TIM Instances : at least 4 capture/compare channels *******/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+/************************** TIM Instances : Advanced-control timers ***********/
+
+/****************** TIM Instances : supporting clock selection ****************/
+#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+/****************** TIM Instances : supporting Hall interface *****************/
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting input XOR function *************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting master mode ********************/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting slave mode *********************/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : supporting DMA burst **********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting input/output channel(s) ********/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1))
+
+/****************** TIM Instances : supporting DMA generation on Update events*/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting DMA generation on Capture/Compare events */
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting remapping capability ***********/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM16))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
+ (((INSTANCE) == TIM1))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Driver Enable ****************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4))
+
+/****************************** USB Instances *********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F3xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F3 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define COMP1_2_3_IRQn COMP1_2_IRQn
+#define COMP2_IRQn COMP1_2_IRQn
+#define COMP_IRQn COMP1_2_IRQn
+#define COMP4_5_6_IRQn COMP4_6_IRQn
+#define HRTIM1_FLT_IRQn I2C3_ER_IRQn
+#define HRTIM1_TIME_IRQn I2C3_EV_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define USBWakeUp_IRQn USBWakeUp_RMP_IRQn
+#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
+#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define COMP1_2_3_IRQHandler COMP1_2_IRQHandler
+#define COMP2_IRQHandler COMP1_2_IRQHandler
+#define COMP_IRQHandler COMP1_2_IRQHandler
+#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
+#define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
+#define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler
+#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
+#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F302xE_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/stm32f303x8.h b/os/ext/CMSIS/ST/stm32f303x8.h index 9b5cc88e2..98ef1ec7c 100644 --- a/os/ext/CMSIS/ST/stm32f303x8.h +++ b/os/ext/CMSIS/ST/stm32f303x8.h @@ -2,9 +2,9 @@ ******************************************************************************
* @file stm32f303x8.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
- * @brief CMSIS STM32F303x6/STM32F303x8 Devices Peripheral Access Layer Header File.
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F303x8 Devices Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
@@ -14,7 +14,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,11 +63,11 @@ /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 0 /*!< STM32F303x6/STM32F303x8 devices do not provide an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F303x6/STM32F303x8 devices use 4 Bits for the Priority Levels */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< STM32F303x8 devices do not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F303x8 devices use 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< STM32F303x6/STM32F303x8 devices provide an FPU */
+#define __FPU_PRESENT 1 /*!< STM32F303x8 devices provide an FPU */
/**
* @}
@@ -78,7 +78,7 @@ */
/**
- * @brief STM32F303x6/STM32F303x8 device Interrupt Number Definition, according to the selected device
+ * @brief STM32F303x8 devices Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
@@ -112,8 +112,8 @@ typedef enum DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
- CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
- CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
@@ -130,12 +130,12 @@ typedef enum USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
- TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
- COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */
- COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -338,8 +338,8 @@ typedef struct typedef struct
{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
@@ -348,20 +348,20 @@ typedef struct typedef struct
{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
- __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
- __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
- __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
- __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
- __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
}EXTI_TypeDef;
/**
@@ -409,8 +409,7 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
@@ -431,10 +430,10 @@ typedef struct typedef struct
{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
__IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
__IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
__IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
__IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
@@ -544,17 +543,6 @@ typedef struct __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
} RTC_TypeDef;
@@ -660,14 +648,12 @@ typedef struct * @{
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 64KB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 12KB) base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the bit-band region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 12KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
@@ -700,11 +686,8 @@ typedef struct #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
#define COMP_BASE COMP2_BASE
-#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
-#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
-#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
-#define OPAMP_BASE OPAMP1_BASE
+#define OPAMP_BASE OPAMP2_BASE
#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
@@ -740,7 +723,7 @@ typedef struct #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
/**
* @}
*/
@@ -760,16 +743,16 @@ typedef struct #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define CAN ((CAN_TypeDef *) CAN_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
-#define COMP ((COMP_TypeDef *) COMP_BASE)
-#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
@@ -799,6 +782,7 @@ typedef struct #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
+
/**
* @}
*/
@@ -820,6 +804,7 @@ typedef struct /* Analog to Digital Converter SAR (ADC) */
/* */
/******************************************************************************/
+
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
@@ -1598,6 +1583,7 @@ typedef struct /* Analog Comparators (COMP) */
/* */
/******************************************************************************/
+
/********************** Bit definition for COMP2_CSR register ***************/
#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
@@ -3008,7 +2994,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -3034,6 +3020,7 @@ typedef struct /******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_OUTEN1 ((uint32_t)0x00000002) /*!< DAC channel1 output switch enable */
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
@@ -3054,7 +3041,7 @@ typedef struct #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_OUTEN2 ((uint32_t)0x00020000) /*!< DAC channel2 output switch enable */
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
@@ -3258,7 +3245,7 @@ typedef struct /* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
-/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
+/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
@@ -3288,8 +3275,11 @@ typedef struct #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
+/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
@@ -3319,8 +3309,11 @@ typedef struct #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
+/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
@@ -3344,14 +3337,11 @@ typedef struct #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
@@ -3375,14 +3365,11 @@ typedef struct #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
@@ -3406,14 +3393,11 @@ typedef struct #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
-
-/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
@@ -3437,12 +3421,37 @@ typedef struct #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
/******************************************************************************/
/* */
@@ -3507,6 +3516,11 @@ typedef struct #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -3536,6 +3550,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -3850,7 +3865,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -3864,6 +3879,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -3883,9 +3901,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -4152,7 +4178,7 @@ typedef struct #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
-#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
/********************* Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
@@ -4206,7 +4232,7 @@ typedef struct #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
/***************** Bit definition for RCC_APB2ENR register ******************/
@@ -4328,20 +4354,20 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000010) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
-
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000100) /*!< TIMSW bits */
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
-
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
@@ -4349,7 +4375,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -4358,7 +4384,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -4694,41 +4720,8 @@ typedef struct /******************** Bits definition for RTC_BKP4R register ****************/
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
-/******************** Bits definition for RTC_BKP5R register ****************/
-#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP6R register ****************/
-#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP7R register ****************/
-#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP8R register ****************/
-#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP9R register ****************/
-#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP10R register ***************/
-#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP11R register ***************/
-#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP12R register ***************/
-#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP13R register ***************/
-#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP14R register ***************/
-#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP15R register ***************/
-#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
-
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
+#define RTC_BKP_NUMBER 5
/******************************************************************************/
/* */
@@ -4806,7 +4799,7 @@ typedef struct /* System Configuration(SYSCFG) */
/* */
/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -4815,8 +4808,8 @@ typedef struct #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x0000F800) /*!< DMA remap mask */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
-#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
#define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
@@ -5016,10 +5009,10 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
-/***************** Bit definition for SYSCFG_CFGR2 register *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
-#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
@@ -5304,7 +5297,7 @@ typedef struct #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
@@ -5827,11 +5820,10 @@ typedef struct /****************************** ADC Instances *********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2))
-
+
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON))
-
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_2_COMMON)
/****************************** CAN Instances *********************************/
#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
@@ -5871,29 +5863,42 @@ typedef struct ((INSTANCE) == DMA1_Channel7))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
/****************************** I2C Instances *********************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
/****************************** SPI Instances *********************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1))
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
/******************* TIM Instances : All supported instances ******************/
#define IS_TIM_INSTANCE(INSTANCE)\
@@ -5941,7 +5946,7 @@ typedef struct /****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1))
-
+
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : supporting clock selection ****************/
@@ -6033,9 +6038,9 @@ typedef struct #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM15) || \
- ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting the break function *************/
@@ -6182,7 +6187,7 @@ typedef struct /******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
-
+
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
@@ -6205,6 +6210,8 @@ typedef struct /*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
@@ -6222,31 +6229,36 @@ typedef struct /******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
+#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
+#define COMP1_2_IRQn COMP2_IRQn
+#define COMP1_2_3_IRQn COMP2_IRQn
+#define COMP_IRQn COMP2_IRQn
+#define COMP4_5_6_IRQn COMP4_6_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
+#define TIM7_IRQn TIM7_DAC2_IRQn
-#define ADC1_IRQn ADC1_2_IRQn
-#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
-#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
-#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM16_IRQn TIM1_UP_TIM16_IRQn
-#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define COMP_IRQn COMP2_IRQn
-#define COMP1_2_3_IRQn COMP2_IRQn
-#define COMP1_2_IRQn COMP2_IRQn
-#define COMP4_5_6_IRQn COMP4_6_IRQn
-#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
-#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
-#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define COMP_IRQHandler COMP2_IRQHandler
-#define COMP1_2_3_IRQHandler COMP2_IRQHandler
-#define COMP1_2_IRQHandler COMP2_IRQHandler
-#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
-#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
+#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
+#define COMP1_2_IRQHandler COMP2_IRQHandler
+#define COMP1_2_3_IRQHandler COMP2_IRQHandler
+#define COMP_IRQHandler COMP2_IRQHandler
+#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
+#define TIM7_IRQHandler TIM7_DAC2_IRQHandler
+
#ifdef __cplusplus
}
diff --git a/os/ext/CMSIS/ST/stm32f303xc.h b/os/ext/CMSIS/ST/stm32f303xc.h index e741b1f12..e38d90df5 100644 --- a/os/ext/CMSIS/ST/stm32f303xc.h +++ b/os/ext/CMSIS/ST/stm32f303xc.h @@ -2,9 +2,9 @@ ******************************************************************************
* @file stm32f303xc.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
- * @brief CMSIS STM32F303xB/STM32F303xC Devices Peripheral Access Layer Header File.
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F303xC Devices Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
@@ -14,7 +14,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,11 +63,11 @@ /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32F303xB/STM32F303xC devices provide an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F303xB/STM32F303xC devices use 4 Bits for the Priority Levels */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F303xC devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F303xC devices use 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< STM32F303xB/STM32F303xC devices provide an FPU */
+#define __FPU_PRESENT 1 /*!< STM32F303xC devices provide an FPU */
/**
* @}
@@ -78,7 +78,7 @@ */
/**
- * @brief STM32F303xB/STM32F303xC devices Interrupt Number Definition, according to the selected device
+ * @brief STM32F303xC devices Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
@@ -144,7 +144,7 @@ typedef enum SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
@@ -155,10 +155,10 @@ typedef enum COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
- USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
- USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -361,8 +361,8 @@ typedef struct typedef struct
{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
@@ -371,20 +371,20 @@ typedef struct typedef struct
{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
- __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
- __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
- __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
- __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
- __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
}EXTI_TypeDef;
/**
@@ -432,8 +432,7 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
@@ -454,10 +453,10 @@ typedef struct typedef struct
{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
__IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
} SYSCFG_TypeDef;
/**
@@ -573,13 +572,13 @@ typedef struct typedef struct
{
- __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
- __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
@@ -688,7 +687,7 @@ typedef struct __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
- __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
} USB_TypeDef;
/**
@@ -705,14 +704,12 @@ typedef struct * @{
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 256KB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 40KB) base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the bit-band region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 40KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
@@ -809,7 +806,7 @@ typedef struct #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
#define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
/**
* @}
*/
@@ -837,9 +834,9 @@ typedef struct #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define CAN ((CAN_TypeDef *) CAN_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
@@ -847,12 +844,12 @@ typedef struct #define COMP5 ((COMP_TypeDef *) COMP5_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
-#define COMP ((COMP_TypeDef *) COMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
-#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
@@ -894,6 +891,7 @@ typedef struct #define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
#define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
#define USB ((USB_TypeDef *) USB_BASE)
+
/**
* @}
*/
@@ -915,6 +913,7 @@ typedef struct /* Analog to Digital Converter SAR (ADC) */
/* */
/******************************************************************************/
+
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
@@ -1781,6 +1780,7 @@ typedef struct /* Analog Comparators (COMP) */
/* */
/******************************************************************************/
+
/********************** Bit definition for COMP1_CSR register ***************/
#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
@@ -1996,7 +1996,6 @@ typedef struct #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
-#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
@@ -3420,7 +3419,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -3673,7 +3672,7 @@ typedef struct /* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
-/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
+/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
@@ -3703,8 +3702,11 @@ typedef struct #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
+/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
@@ -3734,8 +3736,11 @@ typedef struct #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
+/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
@@ -3759,14 +3764,11 @@ typedef struct #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
@@ -3790,14 +3792,11 @@ typedef struct #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
@@ -3821,14 +3820,11 @@ typedef struct #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
-
-/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
@@ -3852,12 +3848,37 @@ typedef struct #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
/******************************************************************************/
/* */
@@ -3922,6 +3943,11 @@ typedef struct #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -3951,6 +3977,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -4265,7 +4292,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -4279,6 +4306,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -4298,9 +4328,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -4571,7 +4609,7 @@ typedef struct #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
-#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
/********************* Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
@@ -4634,7 +4672,7 @@ typedef struct #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
@@ -4694,6 +4732,7 @@ typedef struct /******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_VREGRSTF ((uint32_t)0x00800000) /*!< Voltage regulator reset flag */
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
@@ -4788,10 +4827,12 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
@@ -4801,14 +4842,11 @@ typedef struct #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
#define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
#define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
-
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000300) /*!< TIMSW bits */
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
-
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
-
#define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
#define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
@@ -4816,7 +4854,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -4825,7 +4863,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -4834,7 +4872,7 @@ typedef struct #define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART4 clock source */
#define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
#define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
#define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
@@ -4843,7 +4881,7 @@ typedef struct #define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART5 clock source */
#define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
#define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
#define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
@@ -5213,7 +5251,7 @@ typedef struct #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
+#define RTC_BKP_NUMBER 16
/******************************************************************************/
/* */
@@ -5312,7 +5350,7 @@ typedef struct /* System Configuration(SYSCFG) */
/* */
/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -5323,8 +5361,8 @@ typedef struct #define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
-#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
@@ -5528,10 +5566,10 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
-/***************** Bit definition for SYSCFG_CFGR2 register *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/8/15/16/17 */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
-#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
@@ -5798,7 +5836,7 @@ typedef struct #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
@@ -6289,7 +6327,7 @@ typedef struct /**************************** ISTR interrupt events *************************/
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
@@ -6299,8 +6337,11 @@ typedef struct #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+/* Legacy defines */
+#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
+
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
@@ -6308,9 +6349,12 @@ typedef struct #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+/* Legacy defines */
+#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
+
/************************* CNTR control register bits definitions ***********/
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
@@ -6319,10 +6363,14 @@ typedef struct #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
-#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+/* Legacy defines */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
+#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
+
/******************** FNR Frame Number Register bit definitions ************/
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
@@ -6470,9 +6518,9 @@ typedef struct #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
- (((INSTANCE) == DAC1) && \
+ ((((INSTANCE) == DAC1) && \
(((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2)))
+ ((CHANNEL) == DAC_CHANNEL_2))))
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -6489,12 +6537,23 @@ typedef struct ((INSTANCE) == DMA2_Channel5))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOE) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOD))
/****************************** I2C Instances *********************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
@@ -6504,15 +6563,15 @@ typedef struct #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
-
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3) || \
((INSTANCE) == OPAMP4))
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -6583,7 +6642,7 @@ typedef struct #define IS_TIM_CC6_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
-
+
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : supporting clock selection ****************/
@@ -6698,11 +6757,11 @@ typedef struct #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
- ((INSTANCE) == TIM15) || \
- ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting the break function *************/
@@ -6765,10 +6824,10 @@ typedef struct (((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))) \
- || \
+ || \
(((INSTANCE) == TIM8) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))) \
|| \
(((INSTANCE) == TIM15) && \
@@ -6886,7 +6945,7 @@ typedef struct ((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
-
+
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
@@ -6928,6 +6987,9 @@ typedef struct ((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
+
/****************************** USB Instances *********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
@@ -6948,31 +7010,48 @@ typedef struct /******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define SDADC1_IRQn ADC4_IRQn
+#define COMP1_2_IRQn COMP1_2_3_IRQn
+#define COMP2_IRQn COMP1_2_3_IRQn
+#define COMP_IRQn COMP1_2_3_IRQn
+#define COMP4_6_IRQn COMP4_5_6_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
+#define TIM7_DAC2_IRQn TIM7_IRQn
+#define TIM12_IRQn TIM8_BRK_IRQn
+#define TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM13_IRQn TIM8_UP_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define USBWakeUp_IRQn USBWakeUp_RMP_IRQn
+#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
+#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
-#define ADC1_IRQn ADC1_2_IRQn
-#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
-#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
-#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM16_IRQn TIM1_UP_TIM16_IRQn
-#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define COMP_IRQn COMP1_2_3_IRQn
-#define COMP2_IRQn COMP1_2_3_IRQn
-#define COMP1_2_IRQn COMP1_2_3_IRQn
-#define COMP4_6_IRQn COMP4_5_6_IRQn
-#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
-#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
-#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define COMP_IRQHandler COMP1_2_3_IRQHandler
-#define COMP2_IRQHandler COMP1_2_3_IRQHandler
-#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
-#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
-#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define SDADC1_IRQHandler ADC4_IRQHandler
+#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP_IRQHandler COMP1_2_3_IRQHandler
+#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
+#define TIM12_IRQHandler TIM8_BRK_IRQHandler
+#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM13_IRQHandler TIM8_UP_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler
+#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
+#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
+
#ifdef __cplusplus
}
diff --git a/os/ext/CMSIS/ST/stm32f303xe.h b/os/ext/CMSIS/ST/stm32f303xe.h new file mode 100644 index 000000000..7ea2c379b --- /dev/null +++ b/os/ext/CMSIS/ST/stm32f303xe.h @@ -0,0 +1,8346 @@ +/**
+ ******************************************************************************
+ * @file stm32f303xe.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f303xe
+ * @{
+ */
+
+#ifndef __STM32F303xE_H
+#define __STM32F303xE_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F303xE devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F303xE devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F303xE devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F303xE devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
+ USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
+ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
+ COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
+ COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
+ USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
+ USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
+ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
+ TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */
+ TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */
+ TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */
+ TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
+
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
+ uint16_t RESERVED0; /*!< Reserved, 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
+ __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
+ __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
+} OPAMP_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
+ __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
+ __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
+ __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
+ __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
+ __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
+ __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
+ __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
+ __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
+ __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
+ __IO uint32_t CFGR4; /*!< SYSCFG configuration register 4, Address offset: 0x48 */
+ __IO uint32_t RESERVED12; /*!< Reserved, 0x4C */
+ __IO uint32_t RESERVED13; /*!< Reserved, 0x50 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED0; /*!< Reserved, 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
+} TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED1; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED2; /*!< Reserved, 0x2A */
+} USART_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
+} USB_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FMC_BASE ((uint32_t)0x60000000) /*!< FMC base address */
+#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+#define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
+#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
+#define DAC_BASE DAC1_BASE
+#define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
+#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
+#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
+#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
+#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
+#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
+#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
+#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
+#define COMP_BASE COMP1_BASE
+#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
+#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
+#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
+#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
+#define OPAMP_BASE OPAMP1_BASE
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
+#define TIM20_BASE (APB2PERIPH_BASE + 0x00005000)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
+#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
+#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
+#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
+#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
+#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
+#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
+#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+#define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800)
+#define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00)
+
+/*!< AHB3 peripherals */
+#define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
+#define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
+#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
+#define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400)
+#define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
+#define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
+
+/*!< FMC Bankx base address */
+#define FMC_BANK1 (FMC_BASE) /*!< FMC Bank1 base address */
+#define FMC_BANK1_1 (FMC_BANK1) /*!< FMC Bank1_1 base address */
+#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000) /*!< FMC Bank1_2 base address */
+#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000) /*!< FMC Bank1_3 base address */
+#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000) /*!< FMC Bank1_4 base address */
+
+#define FMC_BANK2 (FMC_BASE + 0x10000000) /*!< FMC Bank2 base address */
+#define FMC_BANK3 (FMC_BASE + 0x20000000) /*!< FMC Bank3 base address */
+#define FMC_BANK4 (FMC_BASE + 0x30000000) /*!< FMC Bank4 base address */
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN ((CAN_TypeDef *) CAN_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
+#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
+#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
+#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
+#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
+#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
+#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
+#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
+#define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
+#define USB ((USB_TypeDef *) USB_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter SAR (ADC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_ISR register ********************/
+#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
+#define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
+
+/******************** Bit definition for ADC_IER register ********************/
+#define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
+#define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
+#define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
+#define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
+#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
+
+/******************** Bit definition for ADC_CFGR register ********************/
+#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
+#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
+
+#define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
+#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
+
+#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
+
+#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
+#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
+#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
+#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
+
+#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
+#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
+
+#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
+#define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
+#define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
+#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
+#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
+#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
+
+#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
+#define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
+#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
+#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
+#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
+#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
+
+/******************** Bit definition for ADC_SMPR1 register ********************/
+#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
+#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
+#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
+#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
+
+#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
+#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
+#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
+#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
+
+#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
+#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
+#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
+#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
+
+#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
+#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
+#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
+#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
+
+#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
+#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
+#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
+#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
+
+#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
+#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
+#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
+#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
+
+#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
+#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
+#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
+#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
+
+#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
+#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
+#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
+#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
+
+#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
+#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
+#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
+#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
+
+#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
+#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
+#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
+#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
+
+/******************** Bit definition for ADC_SMPR2 register ********************/
+#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
+#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
+#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
+#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
+
+#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
+#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
+#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
+#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
+
+#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
+#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
+#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
+#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
+
+#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
+#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
+#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
+#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
+
+#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
+#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
+#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
+#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
+
+#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
+#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
+#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
+#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
+
+#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
+#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
+#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
+#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
+
+#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
+#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
+#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
+#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
+
+#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
+#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
+#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
+#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
+
+/******************** Bit definition for ADC_TR1 register ********************/
+#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
+#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
+#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
+#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
+#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
+#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
+#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
+#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
+#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
+#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
+#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
+#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
+#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
+
+#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
+#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
+#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
+#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
+#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
+#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
+#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
+#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
+#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
+#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
+#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
+#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
+#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
+
+/******************** Bit definition for ADC_TR2 register ********************/
+#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
+#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
+#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
+#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
+#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
+#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
+#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
+#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
+#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
+
+#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
+#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
+#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
+#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
+#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
+#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
+#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
+#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
+#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
+
+/******************** Bit definition for ADC_TR3 register ********************/
+#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
+#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
+#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
+#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
+#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
+#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
+#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
+#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
+#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
+
+#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
+#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
+#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
+#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
+#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
+#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
+#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
+#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
+#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
+
+/******************** Bit definition for ADC_SQR1 register ********************/
+#define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
+
+#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
+#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
+#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
+#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
+#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
+
+#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
+#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
+#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
+#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
+#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
+
+#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
+#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
+#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
+#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
+#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
+
+#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
+#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
+#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
+#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
+#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
+
+/******************** Bit definition for ADC_SQR2 register ********************/
+#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
+#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
+#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
+#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
+#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
+
+#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
+#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
+#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
+#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
+#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
+
+#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
+
+#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
+
+#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
+
+/******************** Bit definition for ADC_SQR3 register ********************/
+#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
+#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
+#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
+#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
+#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
+
+#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
+#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
+#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
+#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
+#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
+
+#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
+#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
+#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
+#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
+#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
+
+#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
+#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
+#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
+#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
+#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
+
+#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
+#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
+#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
+#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
+#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
+
+/******************** Bit definition for ADC_SQR4 register ********************/
+#define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
+#define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
+#define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
+#define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
+#define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
+
+#define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
+#define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
+#define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
+#define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
+#define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
+#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
+#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
+#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
+#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
+#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
+#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
+#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
+#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
+#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
+#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
+#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
+#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
+#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
+#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
+#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
+#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
+
+/******************** Bit definition for ADC_JSQR register ********************/
+#define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
+
+#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
+#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
+#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
+#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
+
+#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
+#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
+
+#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
+
+/******************** Bit definition for ADC_OFR1 register ********************/
+#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
+#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
+#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
+#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
+#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
+#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
+#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
+#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
+#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
+#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
+#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
+#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
+
+#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
+#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
+#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
+#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
+#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
+
+#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
+
+/******************** Bit definition for ADC_OFR2 register ********************/
+#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
+#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
+#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
+#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
+#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
+#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
+#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
+#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
+#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
+#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
+#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
+#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
+
+#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
+#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
+#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
+#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
+#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
+
+#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
+
+/******************** Bit definition for ADC_OFR3 register ********************/
+#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
+#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
+#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
+#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
+#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
+#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
+#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
+#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
+#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
+#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
+#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
+#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
+
+#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
+#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
+#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
+#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
+#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
+
+#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
+
+/******************** Bit definition for ADC_OFR4 register ********************/
+#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
+#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
+#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
+#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
+#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
+#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
+#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
+#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
+#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
+#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
+#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
+#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
+
+#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
+#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
+#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
+#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
+#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
+
+#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
+
+/******************** Bit definition for ADC_JDR1 register ********************/
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR2 register ********************/
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR3 register ********************/
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR4 register ********************/
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_AWD2CR register ********************/
+#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
+#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
+#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
+#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
+#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
+#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
+#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
+#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
+#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
+#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
+#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
+#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
+#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
+#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
+#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
+#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
+#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
+#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
+
+/******************** Bit definition for ADC_AWD3CR register ********************/
+#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
+#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
+#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
+#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
+#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
+#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
+#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
+#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
+#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
+#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
+#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
+#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
+#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
+#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
+#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
+#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
+#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
+#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
+
+/******************** Bit definition for ADC_DIFSEL register ********************/
+#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
+#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
+#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
+#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
+#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
+#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
+#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
+#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
+#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
+#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
+#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
+#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
+#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
+#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
+#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
+#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
+#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
+#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
+#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
+#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
+#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
+#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
+#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
+#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
+#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
+#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
+#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
+#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
+#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
+#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
+#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC12_CSR register ********************/
+#define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
+#define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
+#define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
+#define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
+#define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
+#define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
+#define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
+#define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
+#define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
+#define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
+
+/******************** Bit definition for ADC34_CSR register ********************/
+#define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
+#define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
+#define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
+#define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
+#define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
+#define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
+#define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
+#define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
+#define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
+#define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
+
+/******************** Bit definition for ADC_CCR register ********************/
+#define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
+#define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
+#define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
+#define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
+#define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
+#define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
+#define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
+#define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
+#define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
+#define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
+#define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
+#define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
+#define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
+#define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
+#define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
+#define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
+#define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
+#define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
+#define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
+#define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
+#define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
+
+/******************** Bit definition for ADC_CCR register ********************/
+#define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
+#define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
+#define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
+#define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
+#define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
+#define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
+
+#define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
+#define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
+#define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
+#define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
+#define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
+
+#define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
+#define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
+#define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
+#define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
+
+#define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
+#define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
+#define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
+
+#define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
+#define ADC34_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
+#define ADC34_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
+
+/******************** Bit definition for ADC_CDR register ********************/
+#define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
+#define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
+#define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
+#define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
+#define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
+#define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
+#define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
+#define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
+#define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
+#define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
+#define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
+#define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
+#define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
+#define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
+#define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
+#define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
+
+#define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
+#define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
+#define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
+#define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
+#define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
+#define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
+#define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
+#define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
+#define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
+#define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
+#define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
+#define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
+#define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
+#define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
+#define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
+#define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
+
+/******************** Bit definition for ADC_CDR register ********************/
+#define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
+#define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
+#define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
+#define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
+#define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
+#define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
+#define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
+#define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
+#define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
+#define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
+#define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
+#define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
+#define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
+#define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
+#define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
+#define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
+
+#define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
+#define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
+#define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
+#define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
+#define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
+#define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
+#define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
+#define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
+#define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
+#define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
+#define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
+#define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
+#define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
+#define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
+#define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
+#define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+
+/********************** Bit definition for COMP1_CSR register ***************/
+#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
+#define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */
+#define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
+#define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
+#define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
+#define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
+#define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */
+#define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */
+#define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
+#define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
+#define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
+#define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */
+#define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
+
+/********************** Bit definition for COMP2_CSR register ***************/
+#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
+#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
+#define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
+#define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
+#define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
+#define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */
+#define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
+#define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
+#define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
+#define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
+#define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
+#define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
+#define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
+#define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
+#define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
+#define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
+#define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/********************** Bit definition for COMP3_CSR register ***************/
+#define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */
+#define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
+#define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
+#define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
+#define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
+#define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */
+#define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
+#define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
+#define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
+#define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
+#define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */
+#define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */
+#define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
+#define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
+#define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
+#define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */
+#define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */
+
+/********************** Bit definition for COMP4_CSR register ***************/
+#define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
+#define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */
+#define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
+#define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
+#define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
+#define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */
+#define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
+#define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
+#define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
+#define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
+#define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
+#define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
+#define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
+#define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
+#define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
+#define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
+#define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
+#define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
+
+/********************** Bit definition for COMP5_CSR register ***************/
+#define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */
+#define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
+#define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
+#define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
+#define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
+#define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */
+#define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
+#define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
+#define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
+#define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
+#define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */
+#define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */
+#define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
+#define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
+#define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
+#define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */
+#define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */
+
+/********************** Bit definition for COMP6_CSR register ***************/
+#define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
+#define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */
+#define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
+#define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
+#define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
+#define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */
+#define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
+#define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
+#define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
+#define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
+#define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
+#define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
+#define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
+#define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
+#define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
+#define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
+#define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
+#define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
+
+/********************** Bit definition for COMP7_CSR register ***************/
+#define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */
+#define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
+#define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
+#define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
+#define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
+#define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */
+#define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
+#define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
+#define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
+#define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
+#define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */
+#define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */
+#define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
+#define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
+#define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
+#define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */
+#define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */
+
+/********************** Bit definition for COMP_CSR register ****************/
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
+#define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
+#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /*!< COMPx window mode enable */
+#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
+#define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
+#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
+#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
+#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
+#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
+
+/******************************************************************************/
+/* */
+/* Operational Amplifier (OPAMP) */
+/* */
+/******************************************************************************/
+/********************* Bit definition for OPAMP1_CSR register ***************/
+#define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */
+#define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP2_CSR register ***************/
+#define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
+#define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP3_CSR register ***************/
+#define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */
+#define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP4_CSR register ***************/
+#define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */
+#define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMPx_CSR register ***************/
+#define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network (CAN ) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
+#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x40000000)
+#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB2_FZ_DBG_TIM20_STOP ((uint32_t)0x00000020)
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+#define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
+#define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
+#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCRx register *******************/
+#define FMC_BCRx_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCRx_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCRx_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCRx_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCRx_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCRx_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCRx_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCRx_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCRx_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCRx_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCRx_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCRx_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCRx_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCRx_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCRx_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCRx_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTRx register ******************/
+#define FMC_BTRx_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTRx_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTRx_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTRx_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTRx_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTRx_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTRx_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTRx_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTRx_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTRx_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTRx_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTRx_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTRx_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTRx_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTRx register ******************/
+#define FMC_BWTRx_ADDSETx ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSETx_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTRx_ADDSETx_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTRx_ADDSETx_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTRx_ADDSETx_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTRx_ADDHLDx ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLDx_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTRx_ADDHLDx_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTRx_ADDHLDx_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTRx_ADDHLDx_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTRx_DATASTx ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATASTx_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTRx_DATASTx_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTRx_DATASTx_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTRx_DATASTx_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTRx_DATASTx_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTRx_DATASTx_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTRx_DATASTx_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTRx_DATASTx_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTRx_ACCMODx ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMODx_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTRx_ACCMODx_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
+#define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCRx register *******************/
+#define FMC_PCRx_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCRx_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCRx_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCRx_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCRx_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCRx_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCRx_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCRx_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCRx_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCRx_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCRx_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCRx_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCRx_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCRx_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCRx_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCRx_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCRx_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCRx_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCRx_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCRx_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCRx_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+#define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+#define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+#define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SRx register *******************/
+#define FMC_SRx_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SRx_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SRx_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SRx_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SRx_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SRx_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SRx_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR2 register *******************/
+#define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR3 register *******************/
+#define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR4 register *******************/
+#define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEMx register ******************/
+#define FMC_PMEMx_MEMSETx ((uint32_t)0x000000FF) /*!<MEMSETx[7:0] bits (Common memory x setup time) */
+#define FMC_PMEMx_MEMSETx_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEMx_MEMSETx_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEMx_MEMSETx_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEMx_MEMSETx_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEMx_MEMSETx_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEMx_MEMSETx_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEMx_MEMSETx_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEMx_MEMSETx_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEMx_MEMWAITx ((uint32_t)0x0000FF00) /*!<MEMWAITx[7:0] bits (Common memory x wait time) */
+#define FMC_PMEMx_MEMWAITx_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEMx_MEMHOLDx ((uint32_t)0x00FF0000) /*!<MEMHOLDx[7:0] bits (Common memory x hold time) */
+#define FMC_PMEMx_MEMHOLDx_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEMx_MEMHOLDx_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEMx_MEMHOLDx_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEMx_MEMHOLDx_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEMx_MEMHOLDx_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEMx_MEMHOLDx_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEMx_MEMHOLDx_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEMx_MEMHOLDx_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEMx_MEMHIZx ((uint32_t)0xFF000000) /*!<MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
+#define FMC_PMEMx_MEMHIZx_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEMx_MEMHIZx_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEMx_MEMHIZx_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEMx_MEMHIZx_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEMx_MEMHIZx_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEMx_MEMHIZx_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEMx_MEMHIZx_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEMx_MEMHIZx_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+#define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+#define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+#define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATTx register ******************/
+#define FMC_PATTx_ATTSETx ((uint32_t)0x000000FF) /*!<ATTSETx[7:0] bits (Attribute memory x setup time) */
+#define FMC_PATTx_ATTSETx_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATTx_ATTSETx_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATTx_ATTSETx_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATTx_ATTSETx_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATTx_ATTSETx_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATTx_ATTSETx_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATTx_ATTSETx_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATTx_ATTSETx_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATTx_ATTWAITx ((uint32_t)0x0000FF00) /*!<ATTWAITx[7:0] bits (Attribute memory x wait time) */
+#define FMC_PATTx_ATTWAITx_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATTx_ATTWAITx_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATTx_ATTWAITx_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATTx_ATTWAITx_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATTx_ATTWAITx_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATTx_ATTWAITx_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATTx_ATTWAITx_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATTx_ATTWAITx_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATTx_ATTHOLDx ((uint32_t)0x00FF0000) /*!<ATTHOLDx[7:0] bits (Attribute memory x hold time) */
+#define FMC_PATTx_ATTHOLDx_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATTx_ATTHOLDx_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATTx_ATTHOLDx_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATTx_ATTHOLDx_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATTx_ATTHOLDx_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATTx_ATTHOLDx_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATTx_ATTHOLDx_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATTx_ATTHOLDx_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATTx_ATTHIZx ((uint32_t)0xFF000000) /*!<ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
+#define FMC_PATTx_ATTHIZx_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATTx_ATTHIZx_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATTx_ATTHIZx_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATTx_ATTHIZx_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATTx_ATTHIZx_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATTx_ATTHIZx_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATTx_ATTHIZx_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATTx_ATTHIZx_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+#define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+#define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+#define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+#define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+#define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register ********************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< USB configuration */
+#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
+
+#define RCC_CFGR_USBPRE_DIV1_5 ((uint32_t)0x00000000) /*!< USB prescaler is PLL clock divided by 1.5 */
+#define RCC_CFGR_USBPRE_DIV1 ((uint32_t)0x00400000) /*!< USB prescaler is PLL clock divided by 1 */
+
+/*!< I2S configuration */
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
+
+#define RCC_CFGR_I2SSRC_SYSCLK ((uint32_t)0x00000000) /*!< System clock selected as I2S clock source */
+#define RCC_CFGR_I2SSRC_EXT ((uint32_t)0x00800000) /*!< External clock selected as I2S clock source */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
+
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
+
+/********************* Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/****************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00008000) /*!< SPI4 reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
+#define RCC_APB2RSTR_TIM20RST ((uint32_t)0x00100000) /*!< TIM20 reset */
+
+/****************** Bit definition for RCC_APB1RSTR register ******************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
+#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
+#define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_FMCEN ((uint32_t)0x00000020) /*!< FMC clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00010000) /*!< GPIOH clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+#define RCC_AHBENR_GPIOGEN ((uint32_t)0x00800000) /*!< GPIOG clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
+#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00008000) /*!< SPI4 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_TIM20EN ((uint32_t)0x00100000) /*!< TIM20 clock enable */
+
+/****************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
+#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+#define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_VREGRSTF ((uint32_t)0x00800000) /*!< Voltage regulator reset flag */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+#define RCC_AHBRSTR_FMCRST ((uint32_t)0x00000020) /*!< FMC reset */
+#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00010000) /*!< GPIOH reset */
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
+#define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00800000) /*!< GPIOG reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
+#define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */
+#define RCC_AHBRSTR_ADC34RST ((uint32_t)0x20000000) /*!< ADC3 & ADC4 reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
+
+/*!< ADCPRE12 configuration */
+#define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
+#define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+#define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
+
+#define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
+#define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
+#define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
+#define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
+#define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
+#define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
+#define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
+#define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
+#define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
+#define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
+#define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
+#define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
+#define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
+
+/*!< ADCPRE34 configuration */
+#define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */
+#define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+#define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */
+
+#define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
+#define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */
+#define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */
+#define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */
+#define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */
+#define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */
+#define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */
+#define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */
+#define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */
+#define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */
+#define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */
+#define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */
+#define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */
+
+/******************* Bit definition for RCC_CFGR3 register ******************/
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
+
+#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+#define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
+#define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
+#define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
+#define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
+#define RCC_CFGR3_I2C3SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C3 clock source */
+#define RCC_CFGR3_I2C3SW_SYSCLK ((uint32_t)0x00000040) /*!< System clock selected as I2C3 clock source */
+
+#define RCC_CFGR3_TIMSW ((uint32_t)0x0000AF00) /*!< TIMSW bits */
+#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
+#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
+#define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
+#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
+#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
+#define RCC_CFGR3_TIM20SW ((uint32_t)0x00008000) /*!< TIM20SW bits */
+#define RCC_CFGR3_TIM2SW ((uint32_t)0x01000000) /*!< TIM2SW bits */
+#define RCC_CFGR3_TIM34SW ((uint32_t)0x02000000) /*!< TIM34SW bits */
+#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
+#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
+#define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
+#define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
+#define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
+#define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
+#define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
+#define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
+#define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
+#define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
+#define RCC_CFGR3_TIM20SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM20 clock source */
+#define RCC_CFGR3_TIM20SW_PLL ((uint32_t)0x00008000) /*!< PLL clock used as TIM20 clock source */
+
+#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
+#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
+
+#define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
+#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
+#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
+
+#define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */
+#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
+#define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
+
+#define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */
+#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
+#define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
+
+#define RCC_CFGR3_TIM2SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM2 clock source */
+#define RCC_CFGR3_TIM2SW_PLL ((uint32_t)0x01000000) /*!< PLL clock used as TIM2 clock source */
+
+#define RCC_CFGR3_TIM34SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM3/TIM4 clock source */
+#define RCC_CFGR3_TIM34SW_PLL ((uint32_t)0x02000000) /*!< PLL clock used as TIM3/TIM4 clock source */
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 16
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration(SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_CFGR1_MEM_MODE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */
+#define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
+#define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
+#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00007900) /*!< DMA remap mask */
+#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
+#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
+#define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
+#define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
+#define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x01000000) /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
+#define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
+#define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
+#define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
+#define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
+#define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
+#define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
+
+/***************** Bit definition for SYSCFG_RCR register *******************/
+#define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
+#define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
+#define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
+#define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
+#define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
+#define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
+#define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
+#define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
+#define SYSCFG_RCR_PAGE8 ((uint32_t)0x00000100) /*!< ICODE SRAM Write protection page 8 */
+#define SYSCFG_RCR_PAGE9 ((uint32_t)0x00000200) /*!< ICODE SRAM Write protection page 9 */
+#define SYSCFG_RCR_PAGE10 ((uint32_t)0x00000400) /*!< ICODE SRAM Write protection page 10 */
+#define SYSCFG_RCR_PAGE11 ((uint32_t)0x00000800) /*!< ICODE SRAM Write protection page 11 */
+#define SYSCFG_RCR_PAGE12 ((uint32_t)0x00001000) /*!< ICODE SRAM Write protection page 12 */
+#define SYSCFG_RCR_PAGE13 ((uint32_t)0x00002000) /*!< ICODE SRAM Write protection page 13 */
+#define SYSCFG_RCR_PAGE14 ((uint32_t)0x00004000) /*!< ICODE SRAM Write protection page 14 */
+#define SYSCFG_RCR_PAGE15 ((uint32_t)0x00008000) /*!< ICODE SRAM Write protection page 15 */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
+
+/*!<*
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!< PH[0] pin */
+
+/*!<*
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!< PH[1] pin */
+
+/*!<*
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */
+
+/*!<*
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
+
+/*!<*
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!< PH[4] pin */
+
+/*!<*
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */
+
+/*!<*
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */
+
+/*!<*
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
+
+/*!<*
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */
+
+/*!<*
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */
+
+/*!<*
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */
+
+/*!<*
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
+
+/*!<*
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */
+
+/*!<*
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */
+
+/*!<*
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */
+
+/*!<*
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
+#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
+#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+/***************** Bit definition for SYSCFG_CFGR4 register *****************/
+#define SYSCFG_CFGR4_ADC12_EXT2_RMP ((uint32_t)0x00000001) /*!< ADC12 regular channel EXT2 remap */
+#define SYSCFG_CFGR4_ADC12_EXT3_RMP ((uint32_t)0x00000002) /*!< ADC12 regular channel EXT3 remap */
+#define SYSCFG_CFGR4_ADC12_EXT5_RMP ((uint32_t)0x00000004) /*!< ADC12 regular channel EXT5 remap */
+#define SYSCFG_CFGR4_ADC12_EXT13_RMP ((uint32_t)0x00000008) /*!< ADC12 regular channel EXT13 remap */
+#define SYSCFG_CFGR4_ADC12_EXT15_RMP ((uint32_t)0x00000010) /*!< ADC12 regular channel EXT15 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT3_RMP ((uint32_t)0x00000020) /*!< ADC12 injected channel JEXT3 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT6_RMP ((uint32_t)0x00000040) /*!< ADC12 injected channel JEXT6 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT13_RMP ((uint32_t)0x00000080) /*!< ADC12 injected channel JEXT13 remap */
+#define SYSCFG_CFGR4_ADC34_EXT5_RMP ((uint32_t)0x00000100) /*!< ADC34 regular channel EXT5 remap */
+#define SYSCFG_CFGR4_ADC34_EXT6_RMP ((uint32_t)0x00000200) /*!< ADC34 regular channel EXT6 remap */
+#define SYSCFG_CFGR4_ADC34_EXT15_RMP ((uint32_t)0x00000400) /*!< ADC34 regular channel EXT15 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT5_RMP ((uint32_t)0x00000800) /*!< ADC34 injected channel JEXT5 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT11_RMP ((uint32_t)0x00001000) /*!< ADC34 injected channel JEXT11 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT14_RMP ((uint32_t)0x00002000) /*!< ADC34 injected channel JEXT14 remap */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+#define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+#define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_CCR5 register *******************/
+#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
+
+/******************* Bit definition for TIM_CCR6 register *******************/
+#define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM16_OR register *********************/
+#define TIM16_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
+#define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+/******************* Bit definition for TIM1_OR register *********************/
+#define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
+#define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+/******************* Bit definition for TIM8_OR register *********************/
+#define TIM8_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
+#define TIM8_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM8_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM8_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM8_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+/******************* Bit definition for TIM20_OR register *******************/
+#define TIM20_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM20 ETR remap) */
+#define TIM20_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM20_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM20_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM20_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR3 register *******************/
+#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
+#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
+#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
+
+#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+
+#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+
+#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
+#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
+#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+#define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
+#define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* USB Device General registers */
+/* */
+/******************************************************************************/
+#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
+#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
+#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
+#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
+#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
+#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+
+/* Legacy defines */
+#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+
+/* Legacy defines */
+#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
+
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+
+/* Legacy defines */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
+#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
+
+/*************************** LPM register bits definitions ******************/
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
+
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
+
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
+
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3) || \
+ ((INSTANCE) == ADC4))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON) || \
+ ((INSTANCE) == ADC3_4_COMMON))
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
+
+/****************************** COMP Instances ********************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2) || \
+ ((INSTANCE) == COMP3) || \
+ ((INSTANCE) == COMP4) || \
+ ((INSTANCE) == COMP5) || \
+ ((INSTANCE) == COMP6) || \
+ ((INSTANCE) == COMP7))
+
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
+ ((INSTANCE) == COMP4) || \
+ ((INSTANCE) == COMP6))
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == DAC1) && \
+ (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))))
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************************** I2S Instances *********************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+ ((INSTANCE) == OPAMP2) || \
+ ((INSTANCE) == OPAMP3) || \
+ ((INSTANCE) == OPAMP4))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+/******************* TIM Instances : All supported instances ******************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/******************* TIM Instances : at least 1 capture/compare channel *******/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 2 capture/compare channels *******/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 3 capture/compare channels *******/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 4 capture/compare channels *******/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/************************** TIM Instances : Advanced-control timers ***********/
+
+/****************** TIM Instances : supporting clock selection ****************/
+#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting Hall interface *****************/
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting input XOR function *************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting master mode ********************/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting slave mode *********************/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : supporting DMA burst **********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting input/output channel(s) ********/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM20) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM20) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting DMA generation on Update events*/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting DMA generation on Capture/Compare events */
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting remapping capability ***********/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Driver Enable ****************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
+
+/****************************** USB Instances *********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F3xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F3 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define SDADC1_IRQn ADC4_IRQn
+#define COMP1_2_IRQn COMP1_2_3_IRQn
+#define COMP2_IRQn COMP1_2_3_IRQn
+#define COMP_IRQn COMP1_2_3_IRQn
+#define COMP4_6_IRQn COMP4_5_6_IRQn
+#define HRTIM1_FLT_IRQn I2C3_ER_IRQn
+#define HRTIM1_TIME_IRQn I2C3_EV_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM19_IRQn TIM20_UP_IRQn
+#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
+#define TIM7_DAC2_IRQn TIM7_IRQn
+#define TIM12_IRQn TIM8_BRK_IRQn
+#define TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM13_IRQn TIM8_UP_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
+#define USBWakeUp_IRQn USBWakeUp_RMP_IRQn
+#define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
+#define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define SDADC1_IRQHandler ADC4_IRQHandler
+#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP_IRQHandler COMP1_2_3_IRQHandler
+#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
+#define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
+#define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM19_IRQHandler TIM20_UP_IRQHandler
+#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
+#define TIM12_IRQHandler TIM8_BRK_IRQHandler
+#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM13_IRQHandler TIM8_UP_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define USBWakeUp_IRQHandler USBWakeUp_RMP_IRQHandler
+#define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
+#define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F303xE_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/stm32f318xx.h b/os/ext/CMSIS/ST/stm32f318xx.h index ab71c3ef1..d9b61ece7 100644 --- a/os/ext/CMSIS/ST/stm32f318xx.h +++ b/os/ext/CMSIS/ST/stm32f318xx.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f318xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
+ * @version V2.2.0
+ * @date 13-November-2015
* @brief CMSIS STM32F318xx Devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,7 +63,7 @@ /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< STM32F318xx devices do not provide an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32F318xx devices use 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
@@ -78,7 +78,7 @@ */
/**
- * @brief STM32F318xx device Interrupt Number Definition, according to the selected device
+ * @brief STM32F318xx devices Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
@@ -128,12 +128,12 @@ typedef enum EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel1 underrun error Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */
I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -234,20 +234,20 @@ typedef struct typedef struct
{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t RESERVED0; /*!< Reserved, 0x14 */
__IO uint32_t RESERVED1; /*!< Reserved, 0x18 */
__IO uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t RESERVED3; /*!< Reserved, 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
/**
@@ -276,8 +276,8 @@ typedef struct typedef struct
{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
@@ -286,20 +286,20 @@ typedef struct typedef struct
{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
- __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
- __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
- __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
- __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
- __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
}EXTI_TypeDef;
/**
@@ -347,11 +347,10 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
- __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
}GPIO_TypeDef;
/**
@@ -369,10 +368,10 @@ typedef struct typedef struct
{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
- __IO uint32_t RESERVED0; /*!< Reserved, 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ uint32_t RESERVED; /*!< Reserved, 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
} SYSCFG_TypeDef;
/**
@@ -479,6 +478,10 @@ typedef struct __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
__IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
__IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
} RTC_TypeDef;
@@ -488,13 +491,13 @@ typedef struct typedef struct
{
- __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
- __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
@@ -530,7 +533,6 @@ typedef struct __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
} TIM_TypeDef;
-
/**
* @brief Touch Sensing Controller (TSC)
*/
@@ -590,7 +592,6 @@ typedef struct #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
@@ -662,7 +663,7 @@ typedef struct #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
#define ADC1_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
/**
* @}
*/
@@ -687,13 +688,13 @@ typedef struct #define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define COMP ((COMP_TypeDef *) COMP_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
@@ -721,6 +722,7 @@ typedef struct #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+
/**
* @}
*/
@@ -742,6 +744,7 @@ typedef struct /* Analog to Digital Converter SAR (ADC) */
/* */
/******************************************************************************/
+
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
@@ -1520,6 +1523,7 @@ typedef struct /* Analog Comparators (COMP) */
/* */
/******************************************************************************/
+
/********************** Bit definition for COMP2_CSR register ***************/
#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
#define COMP2_CSR_COMP2INPDAC ((uint32_t)0x00000002) /*!< COMP2 non inverting input to DAC output */
@@ -1672,7 +1676,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -1717,7 +1721,6 @@ typedef struct #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
-
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
@@ -1883,7 +1886,7 @@ typedef struct /* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
-/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
+/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
@@ -1913,8 +1916,11 @@ typedef struct #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
+/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
@@ -1944,8 +1950,11 @@ typedef struct #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
+/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
@@ -1969,14 +1978,11 @@ typedef struct #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
@@ -2000,14 +2006,11 @@ typedef struct #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
@@ -2031,14 +2034,11 @@ typedef struct #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
-
-/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
@@ -2062,12 +2062,37 @@ typedef struct #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
/******************************************************************************/
/* */
@@ -2132,6 +2157,11 @@ typedef struct #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -2161,6 +2191,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -2475,7 +2506,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -2489,6 +2520,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -2508,9 +2542,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -2815,8 +2857,8 @@ typedef struct #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
-#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_ADC1EN ((uint32_t)0x10000000) /*!< ADC1 clock enable */
/***************** Bit definition for RCC_APB2ENR register ******************/
#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
@@ -2936,10 +2978,12 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
@@ -2958,16 +3002,12 @@ typedef struct #define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
-
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
-
#define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
#define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
-
#define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
#define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
-
#define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
#define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
@@ -2975,7 +3015,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -2984,7 +3024,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -3353,8 +3393,20 @@ typedef struct /******************** Bits definition for RTC_BKP15R register ***************/
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
+#define RTC_BKP_NUMBER 20
/******************************************************************************/
/* */
@@ -3453,7 +3505,7 @@ typedef struct /* System Configuration(SYSCFG) */
/* */
/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -3462,7 +3514,7 @@ typedef struct #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00003800) /*!< DMA remap mask */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
@@ -3657,9 +3709,8 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
-/***************** Bit definition for SYSCFG_CFGR2 register *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
-
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
/******************************************************************************/
/* */
@@ -3924,7 +3975,7 @@ typedef struct #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
@@ -4480,11 +4531,23 @@ typedef struct ((INSTANCE) == DMA1_Channel7))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
/****************************** I2C Instances *********************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
@@ -4495,12 +4558,12 @@ typedef struct #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
-
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -4548,12 +4611,12 @@ typedef struct /****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
-
+ ((INSTANCE) == TIM1)
+
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : supporting clock selection ****************/
@@ -4596,7 +4659,7 @@ typedef struct /****************** TIM Instances : supporting Hall interface *****************/
#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : supporting input XOR function *************/
#define IS_TIM_XOR_INSTANCE(INSTANCE)\
@@ -4632,8 +4695,8 @@ typedef struct #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM15) || \
- ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting the break function *************/
@@ -4707,11 +4770,11 @@ typedef struct /****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1))
+ ((INSTANCE) == TIM1)
/****************** TIM Instances : supporting DMA generation on Update events*/
#define IS_TIM_DMA_INSTANCE(INSTANCE)\
@@ -4769,7 +4832,7 @@ typedef struct /******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
-
+
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
@@ -4778,7 +4841,7 @@ typedef struct ((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
-/****************** UART Instances : Auto Baud Rate detection *****************/
+/****************** UART Instances : Driver Enable ****************************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
@@ -4789,6 +4852,8 @@ typedef struct /*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
@@ -4806,27 +4871,34 @@ typedef struct /******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+#define COMP1_2_IRQn COMP2_IRQn
+#define COMP1_2_3_IRQn COMP2_IRQn
+#define COMP_IRQn COMP2_IRQn
+#define COMP4_5_6_IRQn COMP4_6_IRQn
+#define HRTIM1_FLT_IRQn I2C3_ER_IRQn
+#define HRTIM1_TIME_IRQn I2C3_EV_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
-#define ADC1_2_IRQn ADC1_IRQn
-#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM16_IRQn TIM1_UP_TIM16_IRQn
-#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define COMP_IRQn COMP2_IRQn
-#define COMP1_2_IRQn COMP2_IRQn
-#define COMP1_2_3_IRQn COMP2_IRQn
-#define COMP4_5_6_IRQn COMP4_6_IRQn
-#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_2_IRQHandler ADC1_IRQHandler
-#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define COMP_IRQHandler COMP2_IRQHandler
-#define COMP1_2_IRQHandler COMP2_IRQHandler
-#define COMP1_2_3_IRQHandler COMP2_IRQHandler
-#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
-#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+#define COMP1_2_IRQHandler COMP2_IRQHandler
+#define COMP1_2_3_IRQHandler COMP2_IRQHandler
+#define COMP_IRQHandler COMP2_IRQHandler
+#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
+#define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
+#define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+
#ifdef __cplusplus
}
diff --git a/os/ext/CMSIS/ST/stm32f328xx.h b/os/ext/CMSIS/ST/stm32f328xx.h index 99697849a..0adbd81bc 100644 --- a/os/ext/CMSIS/ST/stm32f328xx.h +++ b/os/ext/CMSIS/ST/stm32f328xx.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f328xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
+ * @version V2.2.0
+ * @date 13-November-2015
* @brief CMSIS STM32F328xx Devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,7 +63,7 @@ /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< STM32F328xx devices do not provide an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32F328xx devices use 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
@@ -78,7 +78,7 @@ */
/**
- * @brief STM32F328xx device Interrupt Number Definition, according to the selected device
+ * @brief STM32F328xx devices Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
@@ -111,8 +111,8 @@ typedef enum DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
- CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
- CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
@@ -129,12 +129,12 @@ typedef enum USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
- TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
- COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */
- COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -337,8 +337,8 @@ typedef struct typedef struct
{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
@@ -347,20 +347,20 @@ typedef struct typedef struct
{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
- __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
- __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
- __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
- __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
- __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
}EXTI_TypeDef;
/**
@@ -408,8 +408,7 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
@@ -430,10 +429,10 @@ typedef struct typedef struct
{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
__IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
__IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
__IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
__IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
@@ -543,17 +542,6 @@ typedef struct __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
} RTC_TypeDef;
@@ -603,7 +591,6 @@ typedef struct __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
} TIM_TypeDef;
-
/**
* @brief Touch Sensing Controller (TSC)
*/
@@ -660,14 +647,12 @@ typedef struct * @{
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 64KB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 12KB) base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the bit-band region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 12KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
@@ -757,16 +742,16 @@ typedef struct #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define CAN ((CAN_TypeDef *) CAN_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
-#define COMP ((COMP_TypeDef *) COMP_BASE)
-#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
@@ -796,6 +781,7 @@ typedef struct #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
+
/**
* @}
*/
@@ -817,6 +803,7 @@ typedef struct /* Analog to Digital Converter SAR (ADC) */
/* */
/******************************************************************************/
+
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
@@ -1595,6 +1582,7 @@ typedef struct /* Analog Comparators (COMP) */
/* */
/******************************************************************************/
+
/********************** Bit definition for COMP2_CSR register ***************/
#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
@@ -3005,7 +2993,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -3030,7 +3018,7 @@ typedef struct /******************************************************************************/
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_OUTEN1 ((uint32_t)0x00000002) /*!< DAC channel1 output switch enable */
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
@@ -3051,7 +3039,7 @@ typedef struct #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_OUTEN2 ((uint32_t)0x00020000) /*!< DAC channel2 output switch enable */
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
@@ -3255,7 +3243,7 @@ typedef struct /* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
-/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
+/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
@@ -3285,8 +3273,11 @@ typedef struct #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
+/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
@@ -3316,8 +3307,11 @@ typedef struct #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
+/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
@@ -3341,14 +3335,11 @@ typedef struct #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
@@ -3372,14 +3363,11 @@ typedef struct #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
@@ -3403,14 +3391,11 @@ typedef struct #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
-
-/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
@@ -3434,12 +3419,37 @@ typedef struct #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
/******************************************************************************/
/* */
@@ -3504,6 +3514,11 @@ typedef struct #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -3533,6 +3548,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -3847,7 +3863,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -3861,6 +3877,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -3880,9 +3899,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -4132,7 +4159,7 @@ typedef struct #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
-#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
/********************* Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
@@ -4186,7 +4213,7 @@ typedef struct #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
/***************** Bit definition for RCC_APB2ENR register ******************/
@@ -4207,7 +4234,6 @@ typedef struct #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
-#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
#define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /*!< DAC 2 clock enable */
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
@@ -4309,20 +4335,20 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000010) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
-
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000100) /*!< TIMSW bits */
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
-
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
@@ -4330,7 +4356,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -4339,7 +4365,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -4675,41 +4701,8 @@ typedef struct /******************** Bits definition for RTC_BKP4R register ****************/
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
-/******************** Bits definition for RTC_BKP5R register ****************/
-#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP6R register ****************/
-#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP7R register ****************/
-#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP8R register ****************/
-#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP9R register ****************/
-#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP10R register ***************/
-#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP11R register ***************/
-#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP12R register ***************/
-#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP13R register ***************/
-#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP14R register ***************/
-#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP15R register ***************/
-#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
-
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
+#define RTC_BKP_NUMBER 5
/******************************************************************************/
/* */
@@ -4787,7 +4780,7 @@ typedef struct /* System Configuration(SYSCFG) */
/* */
/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -4796,8 +4789,8 @@ typedef struct #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x0000F800) /*!< DMA remap mask */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
-#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
#define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
@@ -4997,9 +4990,9 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
-/***************** Bit definition for SYSCFG_CFGR2 register *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
@@ -5287,7 +5280,7 @@ typedef struct #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
@@ -5810,11 +5803,10 @@ typedef struct /****************************** ADC Instances *********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2))
-
+
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON))
-
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_2_COMMON)
/****************************** CAN Instances *********************************/
#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
@@ -5854,29 +5846,42 @@ typedef struct ((INSTANCE) == DMA1_Channel7))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
/****************************** I2C Instances *********************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
/****************************** SPI Instances *********************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1))
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
/******************* TIM Instances : All supported instances ******************/
#define IS_TIM_INSTANCE(INSTANCE)\
@@ -5924,7 +5929,7 @@ typedef struct /****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1))
-
+
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : supporting clock selection ****************/
@@ -6016,9 +6021,9 @@ typedef struct #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM15) || \
- ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting the break function *************/
@@ -6165,7 +6170,7 @@ typedef struct /******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
-
+
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
@@ -6188,6 +6193,8 @@ typedef struct /*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
@@ -6205,31 +6212,36 @@ typedef struct /******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
+#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
+#define COMP1_2_IRQn COMP2_IRQn
+#define COMP1_2_3_IRQn COMP2_IRQn
+#define COMP_IRQn COMP2_IRQn
+#define COMP4_5_6_IRQn COMP4_6_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
+#define TIM7_IRQn TIM7_DAC2_IRQn
-#define ADC1_IRQn ADC1_2_IRQn
-#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
-#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
-#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM16_IRQn TIM1_UP_TIM16_IRQn
-#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define COMP_IRQn COMP2_IRQn
-#define COMP1_2_3_IRQn COMP2_IRQn
-#define COMP1_2_IRQn COMP2_IRQn
-#define COMP4_5_6_IRQn COMP4_6_IRQn
-#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
-#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
-#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define COMP_IRQHandler COMP2_IRQHandler
-#define COMP1_2_3_IRQHandler COMP2_IRQHandler
-#define COMP1_2_IRQHandler COMP2_IRQHandler
-#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
-#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
+#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
+#define COMP1_2_IRQHandler COMP2_IRQHandler
+#define COMP1_2_3_IRQHandler COMP2_IRQHandler
+#define COMP_IRQHandler COMP2_IRQHandler
+#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
+#define TIM7_IRQHandler TIM7_DAC2_IRQHandler
+
#ifdef __cplusplus
}
diff --git a/os/ext/CMSIS/ST/stm32f334x8.h b/os/ext/CMSIS/ST/stm32f334x8.h index 9162a95d1..4b02dafdf 100644 --- a/os/ext/CMSIS/ST/stm32f334x8.h +++ b/os/ext/CMSIS/ST/stm32f334x8.h @@ -2,9 +2,9 @@ ******************************************************************************
* @file stm32f334x8.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
- * @brief CMSIS STM32F334x4/STM32F334x6/STM32F334x8 Devices Peripheral Access Layer Header File.
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
@@ -14,7 +14,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,11 +63,11 @@ /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 0 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices do not provide an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices use 4 Bits for the Priority Levels */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< STM32F334x8 devices do not provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F334x8 devices use 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices provide an FPU */
+#define __FPU_PRESENT 1 /*!< STM32F334x8 devices provide an FPU */
/**
* @}
@@ -78,7 +78,7 @@ */
/**
- * @brief STM32F334x4/STM32F334x6/STM32F334x8 device Interrupt Number Definition, according to the selected device
+ * @brief STM32F334x8 devices Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
@@ -112,8 +112,8 @@ typedef enum DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
- CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
- CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
@@ -130,11 +130,11 @@ typedef enum USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
- TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */
- COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */
- COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */
+ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */
+ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */
HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */
HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */
HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */
@@ -142,7 +142,7 @@ typedef enum HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */
HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */
HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -345,8 +345,8 @@ typedef struct typedef struct
{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
@@ -355,20 +355,20 @@ typedef struct typedef struct
{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
- __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
- __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
- __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
- __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
- __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
}EXTI_TypeDef;
/**
@@ -416,8 +416,7 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
@@ -432,7 +431,7 @@ typedef struct __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
} OPAMP_TypeDef;
-/**
+/**
* @brief High resolution Timer (HRTIM)
*/
/* HRTIM master registers definition */
@@ -534,10 +533,10 @@ typedef struct { typedef struct
{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
__IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
__IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
__IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
__IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
@@ -647,17 +646,6 @@ typedef struct __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
} RTC_TypeDef;
@@ -763,14 +751,12 @@ typedef struct * @{
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 64KB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 12KB) base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the bit-band region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 12KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
@@ -847,7 +833,7 @@ typedef struct #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
/**
* @}
*/
@@ -874,16 +860,16 @@ typedef struct #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define CAN ((CAN_TypeDef *) CAN_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
-#define COMP ((COMP_TypeDef *) COMP_BASE)
-#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
@@ -913,6 +899,7 @@ typedef struct #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
+
/**
* @}
*/
@@ -934,6 +921,7 @@ typedef struct /* Analog to Digital Converter SAR (ADC) */
/* */
/******************************************************************************/
+
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
@@ -1736,6 +1724,7 @@ typedef struct /* Analog Comparators (COMP) */
/* */
/******************************************************************************/
+
/********************** Bit definition for COMP2_CSR register ***************/
#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
@@ -3146,7 +3135,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -3172,6 +3161,7 @@ typedef struct /******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_OUTEN1 ((uint32_t)0x00000002) /*!< DAC channel1 output switch enable */
#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
@@ -3192,7 +3182,7 @@ typedef struct #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_OUTEN2 ((uint32_t)0x00020000) /*!< DAC channel2 output switch enable */
#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
@@ -3397,7 +3387,7 @@ typedef struct /* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
-/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
+/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
@@ -3427,8 +3417,11 @@ typedef struct #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
+/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
@@ -3458,8 +3451,11 @@ typedef struct #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
+/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
@@ -3483,14 +3479,11 @@ typedef struct #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
@@ -3514,14 +3507,11 @@ typedef struct #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
@@ -3545,14 +3535,11 @@ typedef struct #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
-
-/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
@@ -3576,12 +3563,37 @@ typedef struct #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
/******************************************************************************/
/* */
@@ -3646,6 +3658,11 @@ typedef struct #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -3675,6 +3692,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -4068,13 +4086,18 @@ typedef struct #define HRTIM_MCMP1R_MCMP1R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
/******************* Bit definition for HRTIM_MCMP2R register *****************/
-#define HRTIM_MCMP1R_MCMP2R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
+#define HRTIM_MCMP2R_MCMP2R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
/******************* Bit definition for HRTIM_MCMP3R register *****************/
-#define HRTIM_MCMP1R_MCMP3R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
+#define HRTIM_MCMP3R_MCMP3R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
/******************* Bit definition for HRTIM_MCMP4R register *****************/
-#define HRTIM_MCMP1R_MCMP4R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
+#define HRTIM_MCMP4R_MCMP4R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
+
+/* Legacy defines */
+#define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP2R_MCMP2R
+#define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP3R_MCMP3R
+#define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP4R_MCMP4R
/******************** Slave control register **********************************/
#define HRTIM_TIMCR_CK_PSC ((uint32_t)0x00000007) /*!< Slave prescaler mask*/
@@ -5175,7 +5198,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -5189,6 +5212,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -5208,9 +5234,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -5477,7 +5511,7 @@ typedef struct #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
-#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
/********************* Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
@@ -5506,7 +5540,7 @@ typedef struct #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
-#define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /*!< TIM17 reset */
+#define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /*!< HRTIM1 reset */
/****************** Bit definition for RCC_APB1RSTR register ******************/
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
@@ -5532,7 +5566,7 @@ typedef struct #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
/***************** Bit definition for RCC_APB2ENR register ******************/
@@ -5543,7 +5577,7 @@ typedef struct #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
-#define RCC_APB2ENR_HRTIM1EN ((uint32_t)0x20000000) /*!< TIM17 reset */
+#define RCC_APB2ENR_HRTIM1EN ((uint32_t)0x20000000) /*!< HRTIM1 reset */
/****************** Bit definition for RCC_APB1ENR register ******************/
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
@@ -5655,34 +5689,34 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK1 ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK1
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000010) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
-
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000100) /*!< TIMSW bits */
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
-
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
-#define RCC_CFGR3_HRTIMSW ((uint32_t)0x00001000) /*!< TIMSW bits */
-#define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /*!< TIM1SW bits */
+#define RCC_CFGR3_HRTIMSW ((uint32_t)0x00001000) /*!< HRTIM1SW bits */
+#define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /*!< HRTIM1SW bits */
-#define RCC_CFGR3_HRTIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
-#define RCC_CFGR3_HRTIM1SW_PLL ((uint32_t)0x00001000) /*!< PLL clock used as TIM1 clock source */
+#define RCC_CFGR3_HRTIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as HRTIM1 clock source */
+#define RCC_CFGR3_HRTIM1SW_PLL ((uint32_t)0x00001000) /*!< PLL clock used as HRTIM1 clock source */
#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -5691,7 +5725,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -6027,41 +6061,8 @@ typedef struct /******************** Bits definition for RTC_BKP4R register ****************/
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
-/******************** Bits definition for RTC_BKP5R register ****************/
-#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP6R register ****************/
-#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP7R register ****************/
-#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP8R register ****************/
-#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP9R register ****************/
-#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP10R register ***************/
-#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP11R register ***************/
-#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP12R register ***************/
-#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP13R register ***************/
-#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP14R register ***************/
-#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP15R register ***************/
-#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
-
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
+#define RTC_BKP_NUMBER 5
/******************************************************************************/
/* */
@@ -6139,7 +6140,7 @@ typedef struct /* System Configuration(SYSCFG) */
/* */
/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -6148,8 +6149,8 @@ typedef struct #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x0000F800) /*!< DMA remap mask */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
-#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
#define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
@@ -6349,10 +6350,10 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
-/***************** Bit definition for SYSCFG_CFGR2 register *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */
-#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
@@ -6640,7 +6641,7 @@ typedef struct #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
@@ -7163,11 +7164,10 @@ typedef struct /****************************** ADC Instances *********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2))
-
+
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON))
-
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_2_COMMON)
/****************************** CAN Instances *********************************/
#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
@@ -7207,32 +7207,45 @@ typedef struct ((INSTANCE) == DMA1_Channel7))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOF))
/****************************** HRTIM Instances *********************************/
#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
/****************************** I2C Instances *********************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2)
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
/****************************** SMBUS Instances *******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
/****************************** SPI Instances *********************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1))
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
/******************* TIM Instances : All supported instances ******************/
#define IS_TIM_INSTANCE(INSTANCE)\
@@ -7280,7 +7293,7 @@ typedef struct /****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1))
-
+
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : supporting clock selection ****************/
@@ -7372,9 +7385,9 @@ typedef struct #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM15) || \
- ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting the break function *************/
@@ -7521,7 +7534,7 @@ typedef struct /******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
-
+
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
@@ -7544,6 +7557,8 @@ typedef struct /*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
@@ -7561,31 +7576,40 @@ typedef struct /******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
+#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
+#define COMP1_2_IRQn COMP2_IRQn
+#define COMP1_2_3_IRQn COMP2_IRQn
+#define COMP_IRQn COMP2_IRQn
+#define COMP4_5_6_IRQn COMP4_6_IRQn
+#define I2C3_ER_IRQn HRTIM1_FLT_IRQn
+#define I2C3_EV_IRQn HRTIM1_TIME_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
+#define TIM7_IRQn TIM7_DAC2_IRQn
-#define ADC1_IRQn ADC1_2_IRQn
-#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
-#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
-#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM16_IRQn TIM1_UP_TIM16_IRQn
-#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define COMP_IRQn COMP2_IRQn
-#define COMP1_2_3_IRQn COMP2_IRQn
-#define COMP1_2_IRQn COMP2_IRQn
-#define COMP4_5_6_IRQn COMP4_6_IRQn
-#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
-#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
-#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define COMP_IRQHandler COMP2_IRQHandler
-#define COMP1_2_3_IRQHandler COMP2_IRQHandler
-#define COMP1_2_IRQHandler COMP2_IRQHandler
-#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
-#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
+#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
+#define COMP1_2_IRQHandler COMP2_IRQHandler
+#define COMP1_2_3_IRQHandler COMP2_IRQHandler
+#define COMP_IRQHandler COMP2_IRQHandler
+#define COMP4_5_6_IRQHandler COMP4_6_IRQHandler
+#define I2C3_ER_IRQHandler HRTIM1_FLT_IRQHandler
+#define I2C3_EV_IRQHandler HRTIM1_TIME_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
+#define TIM7_IRQHandler TIM7_DAC2_IRQHandler
+
#ifdef __cplusplus
}
diff --git a/os/ext/CMSIS/ST/stm32f358xx.h b/os/ext/CMSIS/ST/stm32f358xx.h index c6f4db0aa..b9e7d773a 100644 --- a/os/ext/CMSIS/ST/stm32f358xx.h +++ b/os/ext/CMSIS/ST/stm32f358xx.h @@ -2,9 +2,9 @@ ******************************************************************************
* @file stm32f358xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
- * @brief CMSIS STM32F358xx Device Peripheral Access Layer Header File.
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F358xx Devices Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
@@ -14,7 +14,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,11 +63,11 @@ /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32F358xx devices provide an MPU */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F358xx devices provide an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32F358xx devices use 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< STM32F358xx devices provide an FPU */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F358xx devices provide an FPU */
/**
* @}
@@ -111,8 +111,8 @@ typedef enum DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
- CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
- CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
@@ -142,7 +142,7 @@ typedef enum SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
@@ -153,7 +153,7 @@ typedef enum COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -356,8 +356,8 @@ typedef struct typedef struct
{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
@@ -366,20 +366,20 @@ typedef struct typedef struct
{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
- __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
- __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
- __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
- __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
- __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
}EXTI_TypeDef;
/**
@@ -427,8 +427,7 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
@@ -449,10 +448,10 @@ typedef struct typedef struct
{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
__IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
} SYSCFG_TypeDef;
/**
@@ -568,13 +567,13 @@ typedef struct typedef struct
{
- __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
- __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
@@ -666,14 +665,12 @@ typedef struct * @{
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 256KB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 40KB) base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the bit-band region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 40KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
@@ -768,7 +765,7 @@ typedef struct #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
#define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
/**
* @}
*/
@@ -796,9 +793,9 @@ typedef struct #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define CAN ((CAN_TypeDef *) CAN_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
@@ -806,12 +803,12 @@ typedef struct #define COMP5 ((COMP_TypeDef *) COMP5_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
-#define COMP ((COMP_TypeDef *) COMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
-#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
@@ -852,6 +849,7 @@ typedef struct #define ADC4 ((ADC_TypeDef *) ADC4_BASE)
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
#define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
+
/**
* @}
*/
@@ -873,6 +871,7 @@ typedef struct /* Analog to Digital Converter SAR (ADC) */
/* */
/******************************************************************************/
+
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
@@ -1739,6 +1738,7 @@ typedef struct /* Analog Comparators (COMP) */
/* */
/******************************************************************************/
+
/********************** Bit definition for COMP1_CSR register ***************/
#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
@@ -1954,7 +1954,6 @@ typedef struct #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
-#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
@@ -3378,7 +3377,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -3631,7 +3630,7 @@ typedef struct /* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
-/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
+/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
@@ -3661,8 +3660,11 @@ typedef struct #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
+/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
@@ -3692,8 +3694,11 @@ typedef struct #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
+/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
@@ -3717,14 +3722,11 @@ typedef struct #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
@@ -3748,14 +3750,11 @@ typedef struct #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
@@ -3779,14 +3778,11 @@ typedef struct #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
-
-/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
@@ -3810,12 +3806,37 @@ typedef struct #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
/******************************************************************************/
/* */
@@ -3880,6 +3901,11 @@ typedef struct #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -3909,6 +3935,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -4223,7 +4250,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -4237,6 +4264,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -4256,9 +4286,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -4506,7 +4544,7 @@ typedef struct #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
-#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
/********************* Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
@@ -4568,7 +4606,7 @@ typedef struct #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
@@ -4721,10 +4759,12 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
@@ -4734,14 +4774,11 @@ typedef struct #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
#define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
#define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
-
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000300) /*!< TIMSW bits */
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
-
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
-
#define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
#define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
@@ -4749,7 +4786,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -4758,7 +4795,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -4767,7 +4804,7 @@ typedef struct #define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART4 clock source */
#define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
#define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
#define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
@@ -4776,7 +4813,7 @@ typedef struct #define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART5 clock source */
#define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
#define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
#define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
@@ -5146,7 +5183,7 @@ typedef struct #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
+#define RTC_BKP_NUMBER 16
/******************************************************************************/
/* */
@@ -5245,7 +5282,7 @@ typedef struct /* System Configuration(SYSCFG) */
/* */
/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -5255,8 +5292,8 @@ typedef struct #define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
-#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
@@ -5460,9 +5497,9 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
-/***************** Bit definition for SYSCFG_CFGR2 register *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/8/15/16/17 */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
@@ -5729,7 +5766,7 @@ typedef struct #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
@@ -6294,9 +6331,9 @@ typedef struct #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
- (((INSTANCE) == DAC1) && \
+ ((((INSTANCE) == DAC1) && \
(((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2)))
+ ((CHANNEL) == DAC_CHANNEL_2))))
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -6313,12 +6350,23 @@ typedef struct ((INSTANCE) == DMA2_Channel5))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOE) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOD))
/****************************** I2C Instances *********************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
@@ -6328,15 +6376,15 @@ typedef struct #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
-
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3) || \
((INSTANCE) == OPAMP4))
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -6407,7 +6455,7 @@ typedef struct #define IS_TIM_CC6_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
-
+
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : supporting clock selection ****************/
@@ -6522,11 +6570,11 @@ typedef struct #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
- ((INSTANCE) == TIM15) || \
- ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting the break function *************/
@@ -6589,10 +6637,10 @@ typedef struct (((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))) \
- || \
+ || \
(((INSTANCE) == TIM8) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))) \
|| \
(((INSTANCE) == TIM15) && \
@@ -6710,7 +6758,7 @@ typedef struct ((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
-
+
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
@@ -6752,6 +6800,9 @@ typedef struct ((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
+
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
@@ -6769,31 +6820,44 @@ typedef struct /******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define SDADC1_IRQn ADC4_IRQn
+#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
+#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
+#define COMP1_2_IRQn COMP1_2_3_IRQn
+#define COMP2_IRQn COMP1_2_3_IRQn
+#define COMP_IRQn COMP1_2_3_IRQn
+#define COMP4_6_IRQn COMP4_5_6_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
+#define TIM7_DAC2_IRQn TIM7_IRQn
+#define TIM12_IRQn TIM8_BRK_IRQn
+#define TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM13_IRQn TIM8_UP_IRQn
-#define ADC1_IRQn ADC1_2_IRQn
-#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
-#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
-#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM16_IRQn TIM1_UP_TIM16_IRQn
-#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define COMP_IRQn COMP1_2_3_IRQn
-#define COMP2_IRQn COMP1_2_3_IRQn
-#define COMP1_2_IRQn COMP1_2_3_IRQn
-#define COMP4_6_IRQn COMP4_5_6_IRQn
-#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
-#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
-#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define COMP_IRQHandler COMP1_2_3_IRQHandler
-#define COMP2_IRQHandler COMP1_2_3_IRQHandler
-#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
-#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
-#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define SDADC1_IRQHandler ADC4_IRQHandler
+#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
+#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
+#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP_IRQHandler COMP1_2_3_IRQHandler
+#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
+#define TIM12_IRQHandler TIM8_BRK_IRQHandler
+#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM13_IRQHandler TIM8_UP_IRQHandler
+
#ifdef __cplusplus
}
diff --git a/os/ext/CMSIS/ST/stm32f373xc.h b/os/ext/CMSIS/ST/stm32f373xc.h index a7a2a0464..12ca29090 100644 --- a/os/ext/CMSIS/ST/stm32f373xc.h +++ b/os/ext/CMSIS/ST/stm32f373xc.h @@ -2,9 +2,9 @@ ******************************************************************************
* @file stm32f373xc.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
- * @brief CMSIS STM32F373xB/STM32F373xC Devices Peripheral Access Layer Header File.
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F373xC Devices Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
@@ -14,7 +14,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -64,10 +64,10 @@ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32F373xB/STM32F373xC devices provide an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32F373xB/STM32F373xC devices use 4 Bits for the Priority Levels */
+#define __MPU_PRESENT 1 /*!< STM32F373xC devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F373xC devices use 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< STM32F373xB/STM32F373xC devices provide an FPU */
+#define __FPU_PRESENT 1 /*!< STM32F373xC devices provide an FPU */
/**
* @}
@@ -78,7 +78,7 @@ */
/**
- * @brief STM32F373xB/STM32F373xC devices Interrupt Number Definition, according to the selected device
+ * @brief STM32F373xC devices Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
@@ -141,7 +141,7 @@ typedef enum TIM14_IRQn = 45, /*!< TIM14 global interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
@@ -156,7 +156,7 @@ typedef enum USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
USBWakeUp_IRQn = 76, /*!< USB Wakeup Interrupt */
TIM19_IRQn = 78, /*!< TIM19 global Interrupt */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -198,8 +198,6 @@ typedef struct __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
} ADC_TypeDef;
-
-
/**
* @brief Controller Area Network TxMailBox
*/
@@ -415,8 +413,7 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
@@ -430,7 +427,7 @@ typedef struct {
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
uint32_t RESERVED; /*!< Reserved, 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG control register, Adress offset: 0x14-0x08 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
} SYSCFG_TypeDef;
@@ -593,13 +590,13 @@ typedef struct typedef struct
{
- __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
- __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
@@ -705,7 +702,7 @@ typedef struct __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
- __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
} USB_TypeDef;
/**
@@ -725,7 +722,6 @@ typedef struct #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
@@ -760,9 +756,9 @@ typedef struct #define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
+#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
#define DAC_BASE DAC1_BASE
#define CEC_BASE (APB1PERIPH_BASE + 0x00007800)
-#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
#define TIM18_BASE (APB1PERIPH_BASE + 0x00009C00)
/*!< APB2 peripherals */
@@ -847,14 +843,13 @@ typedef struct #define TIM18 ((TIM_TypeDef *) TIM18_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define TIM19 ((TIM_TypeDef *) TIM19_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define SDADC1 ((SDADC_TypeDef *) SDADC1_BASE)
#define SDADC2 ((SDADC_TypeDef *) SDADC2_BASE)
#define SDADC3 ((SDADC_TypeDef *) SDADC3_BASE)
@@ -883,7 +878,9 @@ typedef struct #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define USB ((USB_TypeDef *) USB_BASE)
+
/**
* @}
*/
@@ -1037,22 +1034,22 @@ typedef struct #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
/****************** Bit definition for ADC_JOFR1 register *******************/
-#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
/****************** Bit definition for ADC_JOFR2 register *******************/
-#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
/****************** Bit definition for ADC_JOFR3 register *******************/
-#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
/****************** Bit definition for ADC_JOFR4 register *******************/
-#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
/******************* Bit definition for ADC_HTR register ********************/
-#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
+#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
/******************* Bit definition for ADC_LTR register ********************/
-#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
+#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
/******************* Bit definition for ADC_SQR1 register *******************/
#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
@@ -1253,25 +1250,25 @@ typedef struct #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
/* COMPx bits definition */
-#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
-#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
-#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
-#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
-#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
-#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
-#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
-#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
-#define COMP_CSR_COMPxWNDWEN ((uint16_t)0x0080) /*!< COMPx window mode enable */
-#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
-#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
-#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
-#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
-#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
-#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
-#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
-#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x2000) /*!< COMPx hysteresis bit 1 */
-#define COMP_CSR_COMPxOUT ((uint32_t)0x4000) /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
+#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
+#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
+#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
+#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000080) /*!< COMPx window mode enable */
+#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
+#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
+#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
+#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
/******************************************************************************/
/* */
@@ -2538,7 +2535,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -2876,17 +2873,7 @@ typedef struct #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -2907,17 +2894,7 @@ typedef struct #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -2938,17 +2915,7 @@ typedef struct #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -2969,18 +2936,7 @@ typedef struct #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
-
/******************************************************************************/
/* */
/* FLASH */
@@ -3035,13 +2991,18 @@ typedef struct #define FLASH_OBR_LEVEL2_PROT ((uint32_t)0x00000004) /*!< Level 2 Read protection status */
#define FLASH_OBR_USER ((uint32_t)0x0000F700) /*!< User Option Bytes */
-#define FLASH_OBR_WDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
#define FLASH_OBR_SDADC12_VDD_MONITOR ((uint32_t)0x00008000) /*!< SDADC12_VDD_MONITOR */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -3071,6 +3032,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -3385,7 +3347,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -3399,6 +3361,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -3418,9 +3383,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -3916,7 +3889,6 @@ typedef struct /******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
-#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
@@ -3965,10 +3937,12 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
@@ -3988,7 +3962,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -3997,7 +3971,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -4415,7 +4389,7 @@ typedef struct #define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000020)
+#define RTC_BKP_NUMBER 32
/******************************************************************************/
/* */
@@ -4785,7 +4759,7 @@ typedef struct #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00008000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
@@ -4872,9 +4846,9 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM15/16/17 */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM15/16/17 */
-#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
+#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
/******************************************************************************/
@@ -4899,7 +4873,6 @@ typedef struct #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
@@ -5561,7 +5534,7 @@ typedef struct /**************************** ISTR interrupt events *************************/
#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
@@ -5571,8 +5544,11 @@ typedef struct #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
+/* Legacy defines */
+#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR
+
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
@@ -5580,9 +5556,12 @@ typedef struct #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+/* Legacy defines */
+#define USB_CLR_PMAOVRM USB_CLR_PMAOVR
+
/************************* CNTR control register bits definitions ***********/
#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
@@ -5591,10 +5570,14 @@ typedef struct #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
-#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
+/* Legacy defines */
+#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR
+#define USB_CNTR_LP_MODE USB_CNTR_LPMODE
+
/******************** FNR Frame Number Register bit definitions ************/
#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
@@ -5728,7 +5711,7 @@ typedef struct /****************************** DAC Instances *********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
((INSTANCE) == DAC2))
-
+
#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == DAC1) && \
(((CHANNEL) == DAC_CHANNEL_1) || \
@@ -5752,12 +5735,23 @@ typedef struct ((INSTANCE) == DMA2_Channel5))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOE) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOD))
/****************************** I2C Instances *********************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
@@ -6155,6 +6149,9 @@ typedef struct ((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
+
/****************************** USB Instances *********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
@@ -6175,25 +6172,48 @@ typedef struct /******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
+#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
+#define USBWakeUp_IRQn CEC_IRQn
+#define COMP1_2_IRQn COMP_IRQn
+#define COMP1_2_3_IRQn COMP_IRQn
+#define COMP2_IRQn COMP_IRQn
+#define ADC4_IRQn SDADC1_IRQn
+#define TIM8_BRK_IRQn TIM12_IRQn
+#define TIM8_UP_IRQn TIM13_IRQn
+#define TIM8_TRG_COM_IRQn TIM14_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM15_IRQn
+#define TIM1_UP_TIM16_IRQn TIM16_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM17_IRQn
+#define TIM1_CC_IRQn TIM18_DAC2_IRQn
+#define TIM20_UP_IRQn TIM19_IRQn
+#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
+#define TIM7_DAC2_IRQn TIM7_IRQn
+#define USBWakeUp_RMP_IRQn USBWakeUp_IRQn
-#define ADC1_2_IRQn ADC1_IRQn
-#define TIM1_BRK_TIM15_IRQn TIM15_IRQn
-#define TIM1_UP_TIM16_IRQn TIM16_IRQn
-#define TIM1_TRG_COM_TIM17_IRQn TIM17_IRQn
-#define COMP2_IRQn COMP_IRQn
-#define COMP1_2_IRQn COMP_IRQn
-#define COMP1_2_3_IRQn COMP_IRQn
-#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_2_IRQHandler ADC1_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler TIM15_IRQHandler
-#define TIM1_UP_TIM16_IRQHandler TIM16_IRQHandler
-#define TIM1_TRG_COM_TIM17_IRQHandler TIM17_IRQHandler
-#define COMP2_IRQHandler COMP_IRQHandler
-#define COMP1_2_IRQHandler COMP_IRQHandler
-#define COMP1_2_3_IRQHandler COMP_IRQHandler
-#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
+#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
+#define USBWakeUp_IRQHandler CEC_IRQHandler
+#define COMP1_2_IRQHandler COMP_IRQHandler
+#define COMP1_2_3_IRQHandler COMP_IRQHandler
+#define COMP2_IRQHandler COMP_IRQHandler
+#define ADC4_IRQHandler SDADC1_IRQHandler
+#define TIM8_BRK_IRQHandler TIM12_IRQHandler
+#define TIM8_UP_IRQHandler TIM13_IRQHandler
+#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM15_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM16_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM17_IRQHandler
+#define TIM1_CC_IRQHandler TIM18_DAC2_IRQHandler
+#define TIM20_UP_IRQHandler TIM19_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
+#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
+#define USBWakeUp_RMP_IRQHandler USBWakeUp_IRQHandler
+
#ifdef __cplusplus
}
diff --git a/os/ext/CMSIS/ST/stm32f378xx.h b/os/ext/CMSIS/ST/stm32f378xx.h index a80b94c0d..f7c2ca021 100644 --- a/os/ext/CMSIS/ST/stm32f378xx.h +++ b/os/ext/CMSIS/ST/stm32f378xx.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f378xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
+ * @version V2.2.0
+ * @date 13-November-2015
* @brief CMSIS STM32F378xx Devices Peripheral Access Layer Header File.
*
* This file contains:
@@ -14,7 +14,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -140,7 +140,7 @@ typedef enum TIM14_IRQn = 45, /*!< TIM14 global interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/
+ TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
@@ -152,7 +152,7 @@ typedef enum SDADC3_IRQn = 63, /*!< ADC Sigma Delta 1 global Interrupt */
COMP_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt */
TIM19_IRQn = 78, /*!< TIM19 global Interrupt */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -194,8 +194,6 @@ typedef struct __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
} ADC_TypeDef;
-
-
/**
* @brief Controller Area Network TxMailBox
*/
@@ -411,8 +409,7 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
@@ -426,7 +423,7 @@ typedef struct {
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
uint32_t RESERVED; /*!< Reserved, 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG control register, Adress offset: 0x14-0x08 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
} SYSCFG_TypeDef;
@@ -589,13 +586,13 @@ typedef struct typedef struct
{
- __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
- __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
@@ -687,7 +684,6 @@ typedef struct #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
@@ -720,9 +716,9 @@ typedef struct #define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
+#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
#define DAC_BASE DAC1_BASE
#define CEC_BASE (APB1PERIPH_BASE + 0x00007800)
-#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
#define TIM18_BASE (APB1PERIPH_BASE + 0x00009C00)
/*!< APB2 peripherals */
@@ -807,14 +803,13 @@ typedef struct #define TIM18 ((TIM_TypeDef *) TIM18_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define TIM19 ((TIM_TypeDef *) TIM19_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define SDADC1 ((SDADC_TypeDef *) SDADC1_BASE)
#define SDADC2 ((SDADC_TypeDef *) SDADC2_BASE)
#define SDADC3 ((SDADC_TypeDef *) SDADC3_BASE)
@@ -843,6 +838,8 @@ typedef struct #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+
/**
* @}
*/
@@ -996,22 +993,22 @@ typedef struct #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
/****************** Bit definition for ADC_JOFR1 register *******************/
-#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
/****************** Bit definition for ADC_JOFR2 register *******************/
-#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
/****************** Bit definition for ADC_JOFR3 register *******************/
-#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
/****************** Bit definition for ADC_JOFR4 register *******************/
-#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
/******************* Bit definition for ADC_HTR register ********************/
-#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */
+#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
/******************* Bit definition for ADC_LTR register ********************/
-#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */
+#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
/******************* Bit definition for ADC_SQR1 register *******************/
#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
@@ -1212,25 +1209,25 @@ typedef struct #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
/* COMPx bits definition */
-#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
-#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
-#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
-#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
-#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
-#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
-#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
-#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
-#define COMP_CSR_COMPxWNDWEN ((uint16_t)0x0080) /*!< COMPx window mode enable */
-#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
-#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
-#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
-#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
-#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
-#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
-#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
-#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x2000) /*!< COMPx hysteresis bit 1 */
-#define COMP_CSR_COMPxOUT ((uint32_t)0x4000) /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
+#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
+#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
+#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
+#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000080) /*!< COMPx window mode enable */
+#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
+#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
+#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
+#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
/******************************************************************************/
/* */
@@ -2497,7 +2494,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -2835,17 +2832,7 @@ typedef struct #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@@ -2866,17 +2853,7 @@ typedef struct #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@@ -2897,17 +2874,7 @@ typedef struct #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
@@ -2928,18 +2895,7 @@ typedef struct #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
-
/******************************************************************************/
/* */
/* FLASH */
@@ -2994,13 +2950,18 @@ typedef struct #define FLASH_OBR_LEVEL2_PROT ((uint32_t)0x00000004) /*!< Level 2 Read protection status */
#define FLASH_OBR_USER ((uint32_t)0x0000F700) /*!< User Option Bytes */
-#define FLASH_OBR_WDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
#define FLASH_OBR_SDADC12_VDD_MONITOR ((uint32_t)0x00008000) /*!< SDADC12_VDD_MONITOR */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -3030,6 +2991,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -3344,7 +3306,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -3358,6 +3320,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -3377,9 +3342,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -3850,7 +3823,6 @@ typedef struct /******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
-#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
@@ -3899,10 +3871,12 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
@@ -3922,7 +3896,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -3931,7 +3905,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -4349,7 +4323,7 @@ typedef struct #define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000020)
+#define RTC_BKP_NUMBER 32
/******************************************************************************/
/* */
@@ -4719,7 +4693,7 @@ typedef struct #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00008000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
@@ -4806,8 +4780,8 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM15/16/17 */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM15/16/17 */
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
/******************************************************************************/
@@ -4832,7 +4806,6 @@ typedef struct #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
-
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
@@ -5554,7 +5527,7 @@ typedef struct /****************************** DAC Instances *********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
((INSTANCE) == DAC2))
-
+
#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == DAC1) && \
(((CHANNEL) == DAC_CHANNEL_1) || \
@@ -5578,12 +5551,23 @@ typedef struct ((INSTANCE) == DMA2_Channel5))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOE) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOD))
/****************************** I2C Instances *********************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
@@ -5981,6 +5965,9 @@ typedef struct ((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
+
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
@@ -5998,25 +5985,46 @@ typedef struct /******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_2_IRQn ADC1_IRQn
+#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
+#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
+#define USBWakeUp_IRQn CEC_IRQn
+#define COMP1_2_IRQn COMP_IRQn
+#define COMP1_2_3_IRQn COMP_IRQn
+#define COMP2_IRQn COMP_IRQn
+#define ADC4_IRQn SDADC1_IRQn
+#define TIM8_BRK_IRQn TIM12_IRQn
+#define TIM8_UP_IRQn TIM13_IRQn
+#define TIM8_TRG_COM_IRQn TIM14_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM15_IRQn
+#define TIM1_UP_TIM16_IRQn TIM16_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM17_IRQn
+#define TIM1_CC_IRQn TIM18_DAC2_IRQn
+#define TIM20_UP_IRQn TIM19_IRQn
+#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
+#define TIM7_DAC2_IRQn TIM7_IRQn
-#define ADC1_2_IRQn ADC1_IRQn
-#define TIM1_BRK_TIM15_IRQn TIM15_IRQn
-#define TIM1_UP_TIM16_IRQn TIM16_IRQn
-#define TIM1_TRG_COM_TIM17_IRQn TIM17_IRQn
-#define COMP2_IRQn COMP_IRQn
-#define COMP1_2_IRQn COMP_IRQn
-#define COMP1_2_3_IRQn COMP_IRQn
-#define TIM6_DAC_IRQn TIM6_DAC1_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_2_IRQHandler ADC1_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler TIM15_IRQHandler
-#define TIM1_UP_TIM16_IRQHandler TIM16_IRQHandler
-#define TIM1_TRG_COM_TIM17_IRQHandler TIM17_IRQHandler
-#define COMP2_IRQHandler COMP_IRQHandler
-#define COMP1_2_IRQHandler COMP_IRQHandler
-#define COMP1_2_3_IRQHandler COMP_IRQHandler
-#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
+#define ADC1_2_IRQHandler ADC1_IRQHandler
+#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
+#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
+#define USBWakeUp_IRQHandler CEC_IRQHandler
+#define COMP1_2_IRQHandler COMP_IRQHandler
+#define COMP1_2_3_IRQHandler COMP_IRQHandler
+#define COMP2_IRQHandler COMP_IRQHandler
+#define ADC4_IRQHandler SDADC1_IRQHandler
+#define TIM8_BRK_IRQHandler TIM12_IRQHandler
+#define TIM8_UP_IRQHandler TIM13_IRQHandler
+#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM15_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM16_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM17_IRQHandler
+#define TIM1_CC_IRQHandler TIM18_DAC2_IRQHandler
+#define TIM20_UP_IRQHandler TIM19_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler
+#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
+
#ifdef __cplusplus
}
diff --git a/os/ext/CMSIS/ST/stm32f398xx.h b/os/ext/CMSIS/ST/stm32f398xx.h new file mode 100644 index 000000000..b44454821 --- /dev/null +++ b/os/ext/CMSIS/ST/stm32f398xx.h @@ -0,0 +1,8139 @@ +/**
+ ******************************************************************************
+ * @file stm32f398xx.h
+ * @author MCD Application Team
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F398xx Devices Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32f398xx
+ * @{
+ */
+
+#ifndef __STM32F398xx_H
+#define __STM32F398xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F398xx devices provide an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32F398xx devices use 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F398xx devices provide an FPU */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32F398xx devices Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
+ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
+ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
+ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
+ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
+ COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
+ COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
+ TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */
+ TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */
+ TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */
+ TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f3xx.h" /* STM32F3xx System Header */
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
+ uint32_t RESERVED0; /*!< Reserved, 0x010 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x01C */
+ __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x02C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x044 */
+ uint32_t RESERVED4; /*!< Reserved, 0x048 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+ uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual
+ AND triple modes, Address offset: ADC1/3 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+/**
+ * @brief Analog Comparators
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
+ __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
+ __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
+
+} FLASH_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank2
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
+ uint32_t RESERVED1; /*!< Reserved, 0x78 */
+ uint32_t RESERVED2; /*!< Reserved, 0x7C */
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+ uint32_t RESERVED3; /*!< Reserved, 0x90 */
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
+} FMC_Bank2_3_TypeDef;
+
+/**
+ * @brief Flexible Memory Controller Bank4
+ */
+
+typedef struct
+{
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
+} FMC_Bank4_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
+ __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
+ uint16_t RESERVED0; /*!< Reserved, 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
+ __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
+ __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
+ __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
+} OB_TypeDef;
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
+} OPAMP_TypeDef;
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
+ __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
+ __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
+ __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
+ __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
+ __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
+ __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
+ __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
+ __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
+ __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
+ __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
+ __IO uint32_t CFGR4; /*!< SYSCFG configuration register 4, Address offset: 0x48 */
+ __IO uint32_t RESERVED12; /*!< Reserved, 0x4C */
+ __IO uint32_t RESERVED13; /*!< Reserved, 0x50 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
+ __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED0; /*!< Reserved, 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
+} TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED1; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED2; /*!< Reserved, 0x2A */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FMC_BASE ((uint32_t)0x60000000) /*!< FMC base address */
+#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
+#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
+#define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
+#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
+#define DAC_BASE DAC1_BASE
+#define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
+#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
+#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
+#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
+#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
+#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
+#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
+#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
+#define COMP_BASE COMP1_BASE
+#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
+#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
+#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
+#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
+#define OPAMP_BASE OPAMP1_BASE
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
+#define TIM20_BASE (APB2PERIPH_BASE + 0x00005000)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
+#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
+#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
+#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
+#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
+#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
+#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
+#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
+#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
+#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
+#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
+#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
+#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
+#define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800)
+#define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00)
+
+/*!< AHB3 peripherals */
+#define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
+#define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
+#define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
+#define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400)
+#define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
+#define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
+
+/*!< FMC Bankx base address */
+#define FMC_BANK1 (FMC_BASE) /*!< FMC Bank1 base address */
+#define FMC_BANK1_1 (FMC_BANK1) /*!< FMC Bank1_1 base address */
+#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000) /*!< FMC Bank1_2 base address */
+#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000) /*!< FMC Bank1_3 base address */
+#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000) /*!< FMC Bank1_4 base address */
+
+#define FMC_BANK2 (FMC_BASE + 0x10000000) /*!< FMC Bank2 base address */
+#define FMC_BANK3 (FMC_BASE + 0x20000000) /*!< FMC Bank3 base address */
+#define FMC_BANK4 (FMC_BASE + 0x30000000) /*!< FMC Bank4 base address */
+
+/*!< FMC Bankx registers base address */
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
+#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060)
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CAN ((CAN_TypeDef *) CAN_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
+#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
+#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
+#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
+#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
+#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
+#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
+#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
+#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
+#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
+#define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter SAR (ADC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_ISR register ********************/
+#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
+#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
+#define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
+
+/******************** Bit definition for ADC_IER register ********************/
+#define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
+#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
+#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
+#define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
+#define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
+#define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
+#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
+
+/******************** Bit definition for ADC_CFGR register ********************/
+#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
+#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
+
+#define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
+#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
+
+#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
+
+#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
+#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
+#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
+#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
+
+#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
+#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
+
+#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
+#define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
+#define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
+#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
+#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
+#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
+
+#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
+#define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
+#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
+#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
+#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
+#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
+
+/******************** Bit definition for ADC_SMPR1 register ********************/
+#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
+#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
+#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
+#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
+
+#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
+#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
+#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
+#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
+
+#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
+#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
+#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
+#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
+
+#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
+#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
+#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
+#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
+
+#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
+#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
+#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
+#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
+
+#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
+#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
+#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
+#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
+
+#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
+#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
+#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
+#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
+
+#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
+#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
+#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
+#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
+
+#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
+#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
+#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
+#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
+
+#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
+#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
+#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
+#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
+
+/******************** Bit definition for ADC_SMPR2 register ********************/
+#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
+#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
+#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
+#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
+
+#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
+#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
+#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
+#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
+
+#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
+#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
+#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
+#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
+
+#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
+#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
+#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
+#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
+
+#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
+#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
+#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
+#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
+
+#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
+#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
+#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
+#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
+
+#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
+#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
+#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
+#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
+
+#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
+#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
+#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
+#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
+
+#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
+#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
+#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
+#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
+
+/******************** Bit definition for ADC_TR1 register ********************/
+#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
+#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
+#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
+#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
+#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
+#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
+#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
+#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
+#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
+#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
+#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
+#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
+#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
+
+#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
+#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
+#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
+#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
+#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
+#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
+#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
+#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
+#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
+#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
+#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
+#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
+#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
+
+/******************** Bit definition for ADC_TR2 register ********************/
+#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
+#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
+#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
+#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
+#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
+#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
+#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
+#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
+#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
+
+#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
+#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
+#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
+#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
+#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
+#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
+#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
+#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
+#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
+
+/******************** Bit definition for ADC_TR3 register ********************/
+#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
+#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
+#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
+#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
+#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
+#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
+#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
+#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
+#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
+
+#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
+#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
+#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
+#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
+#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
+#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
+#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
+#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
+#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
+
+/******************** Bit definition for ADC_SQR1 register ********************/
+#define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
+#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
+
+#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
+#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
+#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
+#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
+#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
+
+#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
+#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
+#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
+#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
+#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
+
+#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
+#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
+#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
+#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
+#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
+
+#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
+#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
+#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
+#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
+#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
+
+/******************** Bit definition for ADC_SQR2 register ********************/
+#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
+#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
+#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
+#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
+#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
+
+#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
+#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
+#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
+#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
+#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
+
+#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
+
+#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
+
+#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
+
+/******************** Bit definition for ADC_SQR3 register ********************/
+#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
+#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
+#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
+#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
+#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
+
+#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
+#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
+#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
+#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
+#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
+
+#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
+#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
+#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
+#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
+#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
+
+#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
+#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
+#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
+#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
+#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
+
+#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
+#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
+#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
+#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
+#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
+
+/******************** Bit definition for ADC_SQR4 register ********************/
+#define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
+#define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
+#define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
+#define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
+#define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
+
+#define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
+#define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
+#define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
+#define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
+#define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
+#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
+#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
+#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
+#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
+#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
+#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
+#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
+#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
+#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
+#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
+#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
+#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
+#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
+#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
+#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
+#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
+
+/******************** Bit definition for ADC_JSQR register ********************/
+#define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
+
+#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
+#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
+#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
+#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
+
+#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
+#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
+
+#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
+
+/******************** Bit definition for ADC_OFR1 register ********************/
+#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
+#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
+#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
+#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
+#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
+#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
+#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
+#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
+#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
+#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
+#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
+#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
+
+#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
+#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
+#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
+#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
+#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
+
+#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
+
+/******************** Bit definition for ADC_OFR2 register ********************/
+#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
+#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
+#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
+#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
+#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
+#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
+#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
+#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
+#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
+#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
+#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
+#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
+
+#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
+#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
+#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
+#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
+#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
+
+#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
+
+/******************** Bit definition for ADC_OFR3 register ********************/
+#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
+#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
+#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
+#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
+#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
+#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
+#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
+#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
+#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
+#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
+#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
+#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
+
+#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
+#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
+#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
+#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
+#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
+
+#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
+
+/******************** Bit definition for ADC_OFR4 register ********************/
+#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
+#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
+#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
+#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
+#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
+#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
+#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
+#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
+#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
+#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
+#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
+#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
+
+#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
+#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
+#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
+#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
+#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
+
+#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
+
+/******************** Bit definition for ADC_JDR1 register ********************/
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR2 register ********************/
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR3 register ********************/
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_JDR4 register ********************/
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
+#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
+#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
+#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
+#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
+#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
+#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
+#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
+#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
+#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
+#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
+#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
+#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
+#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
+#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
+#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
+
+/******************** Bit definition for ADC_AWD2CR register ********************/
+#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
+#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
+#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
+#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
+#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
+#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
+#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
+#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
+#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
+#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
+#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
+#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
+#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
+#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
+#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
+#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
+#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
+#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
+
+/******************** Bit definition for ADC_AWD3CR register ********************/
+#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
+#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
+#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
+#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
+#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
+#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
+#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
+#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
+#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
+#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
+#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
+#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
+#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
+#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
+#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
+#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
+#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
+#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
+
+/******************** Bit definition for ADC_DIFSEL register ********************/
+#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
+#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
+#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
+#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
+#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
+#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
+#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
+#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
+#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
+#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
+#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
+#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
+#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
+#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
+#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
+#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
+#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
+#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
+#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
+#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
+#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
+#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
+#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
+#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
+#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
+#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
+#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
+#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
+#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
+#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
+#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC12_CSR register ********************/
+#define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
+#define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
+#define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
+#define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
+#define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
+#define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
+#define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
+#define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
+#define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
+#define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
+#define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
+#define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
+
+/******************** Bit definition for ADC34_CSR register ********************/
+#define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
+#define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
+#define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
+#define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
+#define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
+#define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
+#define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
+#define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
+#define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
+#define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
+#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
+#define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
+#define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
+
+/******************** Bit definition for ADC_CCR register ********************/
+#define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
+#define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
+#define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
+#define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
+#define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
+#define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
+#define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
+#define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
+#define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
+#define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
+#define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
+#define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
+#define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
+#define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
+#define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
+#define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
+#define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
+#define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
+#define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
+#define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
+#define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
+
+/******************** Bit definition for ADC_CCR register ********************/
+#define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
+#define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
+#define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
+#define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
+#define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
+#define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
+
+#define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
+#define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
+#define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
+#define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
+#define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
+
+#define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
+#define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
+#define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
+#define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
+
+#define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
+#define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
+#define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
+
+#define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
+#define ADC34_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
+#define ADC34_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
+
+/******************** Bit definition for ADC_CDR register ********************/
+#define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
+#define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
+#define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
+#define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
+#define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
+#define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
+#define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
+#define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
+#define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
+#define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
+#define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
+#define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
+#define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
+#define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
+#define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
+#define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
+
+#define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
+#define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
+#define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
+#define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
+#define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
+#define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
+#define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
+#define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
+#define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
+#define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
+#define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
+#define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
+#define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
+#define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
+#define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
+#define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
+#define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
+
+/******************** Bit definition for ADC_CDR register ********************/
+#define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
+#define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
+#define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
+#define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
+#define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
+#define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
+#define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
+#define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
+#define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
+#define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
+#define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
+#define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
+#define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
+#define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
+#define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
+#define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
+
+#define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
+#define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
+#define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
+#define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
+#define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
+#define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
+#define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
+#define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
+#define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
+#define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
+#define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
+#define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
+#define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
+#define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
+#define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
+#define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
+#define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+
+/********************** Bit definition for COMP1_CSR register ***************/
+#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
+#define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */
+#define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
+#define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
+#define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
+#define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
+#define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */
+#define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */
+#define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
+#define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
+#define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
+#define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */
+#define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
+
+/********************** Bit definition for COMP2_CSR register ***************/
+#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
+#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
+#define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
+#define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
+#define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
+#define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */
+#define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
+#define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
+#define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
+#define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
+#define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
+#define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
+#define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
+#define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
+#define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
+#define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
+#define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/********************** Bit definition for COMP3_CSR register ***************/
+#define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */
+#define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
+#define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
+#define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
+#define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
+#define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */
+#define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
+#define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
+#define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
+#define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
+#define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */
+#define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */
+#define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
+#define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
+#define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
+#define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */
+#define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */
+
+/********************** Bit definition for COMP4_CSR register ***************/
+#define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
+#define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */
+#define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
+#define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
+#define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
+#define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */
+#define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
+#define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
+#define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
+#define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
+#define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
+#define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
+#define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
+#define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
+#define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
+#define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
+#define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
+#define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
+
+/********************** Bit definition for COMP5_CSR register ***************/
+#define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */
+#define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
+#define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
+#define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
+#define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
+#define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */
+#define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
+#define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
+#define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
+#define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
+#define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */
+#define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */
+#define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
+#define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
+#define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
+#define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */
+#define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */
+
+/********************** Bit definition for COMP6_CSR register ***************/
+#define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
+#define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */
+#define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
+#define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
+#define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
+#define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */
+#define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
+#define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
+#define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
+#define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
+#define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
+#define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
+#define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
+#define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
+#define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
+#define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
+#define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
+#define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
+
+/********************** Bit definition for COMP7_CSR register ***************/
+#define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */
+#define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
+#define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
+#define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
+#define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
+#define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */
+#define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
+#define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
+#define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
+#define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
+#define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */
+#define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */
+#define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
+#define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
+#define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
+#define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */
+#define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */
+
+/********************** Bit definition for COMP_CSR register ****************/
+#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
+#define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */
+#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
+#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
+#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
+#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
+#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /*!< COMPx window mode enable */
+#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
+#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
+#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
+#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
+#define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
+#define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
+#define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
+#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
+#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
+#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
+#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
+
+/******************************************************************************/
+/* */
+/* Operational Amplifier (OPAMP) */
+/* */
+/******************************************************************************/
+/********************* Bit definition for OPAMP1_CSR register ***************/
+#define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */
+#define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP2_CSR register ***************/
+#define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
+#define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP3_CSR register ***************/
+#define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */
+#define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMP4_CSR register ***************/
+#define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */
+#define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/********************* Bit definition for OPAMPx_CSR register ***************/
+#define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
+#define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
+#define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+#define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
+#define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
+#define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
+#define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
+#define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
+#define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
+#define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
+#define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
+#define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
+#define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
+#define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
+#define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
+#define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
+#define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network (CAN ) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
+#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
+#define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
+#define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
+#define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
+#define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
+
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
+#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
+#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
+#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
+#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
+#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
+#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
+#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
+#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F0R2 register *******************/
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R2 register *******************/
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R2 register *******************/
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R2 register *******************/
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R2 register *******************/
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R2 register *******************/
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R2 register *******************/
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R2 register *******************/
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R2 register *******************/
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R2 register *******************/
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R2 register ******************/
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R2 register ******************/
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R2 register ******************/
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R2 register ******************/
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
+#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
+#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for DBGMCU_IDCODE register *************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
+
+/******************** Bit definition for DBGMCU_CR register *****************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
+
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x40000000)
+#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
+
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
+#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
+#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
+#define DBGMCU_APB2_FZ_DBG_TIM20_STOP ((uint32_t)0x00000020)
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
+#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
+#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
+#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
+#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+
+#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+
+#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
+#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
+#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
+#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
+#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
+
+/******************************************************************************/
+/* */
+/* FLASH */
+/* */
+/******************************************************************************/
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
+#define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
+#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
+
+/****************** Bit definition for FLASH_KEYR register ******************/
+#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
+
+#define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
+#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
+
+/***************** Bit definition for FLASH_OPTKEYR register ****************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
+
+#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
+#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
+#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
+
+/******************* Bit definition for FLASH_CR register *******************/
+#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
+#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
+#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
+#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
+#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
+#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
+#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
+#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
+#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
+#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
+
+/******************* Bit definition for FLASH_AR register *******************/
+#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
+#define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
+#define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
+#define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
+
+#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
+#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
+#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
+#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/****************** Bit definition for OB_RDP register **********************/
+#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
+#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
+
+/****************** Bit definition for OB_USER register *********************/
+#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
+#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
+
+/****************** Bit definition for FLASH_WRP0 register ******************/
+#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP1 register ******************/
+#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP2 register ******************/
+#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
+#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
+
+/****************** Bit definition for FLASH_WRP3 register ******************/
+#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
+#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/* */
+/* Flexible Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FMC_BCRx register *******************/
+#define FMC_BCRx_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCRx_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCRx_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCRx_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCRx_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCRx_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCRx_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCRx_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCRx_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCRx_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCRx_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCRx_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCRx_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCRx_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCRx_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCRx_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR1 register *******************/
+#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
+
+/****************** Bit definition for FMC_BCR2 register *******************/
+#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR3 register *******************/
+#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BCR4 register *******************/
+#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
+#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
+
+#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
+#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
+#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
+#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
+#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
+#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
+#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
+#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
+#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
+#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
+#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
+
+/****************** Bit definition for FMC_BTRx register ******************/
+#define FMC_BTRx_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTRx_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTRx_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTRx_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTRx_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTRx_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTRx_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTRx_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTRx_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTRx_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTRx_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTRx_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTRx_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTRx_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR1 register ******************/
+#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR2 register *******************/
+#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/******************* Bit definition for FMC_BTR3 register *******************/
+#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BTR4 register *******************/
+#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+
+#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTRx register ******************/
+#define FMC_BWTRx_ADDSETx ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSETx_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTRx_ADDSETx_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTRx_ADDSETx_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTRx_ADDSETx_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTRx_ADDHLDx ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLDx_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTRx_ADDHLDx_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTRx_ADDHLDx_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTRx_ADDHLDx_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTRx_DATASTx ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATASTx_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTRx_DATASTx_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTRx_DATASTx_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTRx_DATASTx_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTRx_DATASTx_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTRx_DATASTx_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTRx_DATASTx_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTRx_DATASTx_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTRx_ACCMODx ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMODx_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTRx_ACCMODx_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR1 register ******************/
+#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR2 register ******************/
+#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
+#define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR3 register ******************/
+#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_BWTR4 register ******************/
+#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
+
+#define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+
+/****************** Bit definition for FMC_PCRx register *******************/
+#define FMC_PCRx_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCRx_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCRx_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCRx_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCRx_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCRx_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCRx_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCRx_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCRx_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCRx_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCRx_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCRx_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCRx_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCRx_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCRx_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCRx_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCRx_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCRx_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCRx_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCRx_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCRx_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR2 register *******************/
+#define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
+#define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR3 register *******************/
+#define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/****************** Bit definition for FMC_PCR4 register *******************/
+#define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
+#define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
+
+#define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+
+#define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
+
+#define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
+#define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
+#define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
+#define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
+
+#define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
+#define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
+#define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
+#define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
+#define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+
+/******************* Bit definition for FMC_SRx register *******************/
+#define FMC_SRx_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SRx_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SRx_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SRx_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SRx_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SRx_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SRx_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR2 register *******************/
+#define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR3 register *******************/
+#define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/******************* Bit definition for FMC_SR4 register *******************/
+#define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
+#define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
+#define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
+#define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
+#define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
+#define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
+
+/****************** Bit definition for FMC_PMEMx register ******************/
+#define FMC_PMEMx_MEMSETx ((uint32_t)0x000000FF) /*!<MEMSETx[7:0] bits (Common memory x setup time) */
+#define FMC_PMEMx_MEMSETx_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEMx_MEMSETx_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEMx_MEMSETx_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEMx_MEMSETx_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEMx_MEMSETx_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEMx_MEMSETx_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEMx_MEMSETx_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEMx_MEMSETx_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEMx_MEMWAITx ((uint32_t)0x0000FF00) /*!<MEMWAITx[7:0] bits (Common memory x wait time) */
+#define FMC_PMEMx_MEMWAITx_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEMx_MEMHOLDx ((uint32_t)0x00FF0000) /*!<MEMHOLDx[7:0] bits (Common memory x hold time) */
+#define FMC_PMEMx_MEMHOLDx_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEMx_MEMHOLDx_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEMx_MEMHOLDx_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEMx_MEMHOLDx_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEMx_MEMHOLDx_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEMx_MEMHOLDx_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEMx_MEMHOLDx_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEMx_MEMHOLDx_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEMx_MEMHIZx ((uint32_t)0xFF000000) /*!<MEMHIZx[7:0] bits (Common memory x databus HiZ time) */
+#define FMC_PMEMx_MEMHIZx_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEMx_MEMHIZx_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEMx_MEMHIZx_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEMx_MEMHIZx_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEMx_MEMHIZx_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEMx_MEMHIZx_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEMx_MEMHIZx_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEMx_MEMHIZx_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM2 register ******************/
+#define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM3 register ******************/
+#define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PMEM4 register ******************/
+#define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATTx register ******************/
+#define FMC_PATTx_ATTSETx ((uint32_t)0x000000FF) /*!<ATTSETx[7:0] bits (Attribute memory x setup time) */
+#define FMC_PATTx_ATTSETx_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATTx_ATTSETx_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATTx_ATTSETx_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATTx_ATTSETx_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATTx_ATTSETx_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATTx_ATTSETx_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATTx_ATTSETx_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATTx_ATTSETx_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATTx_ATTWAITx ((uint32_t)0x0000FF00) /*!<ATTWAITx[7:0] bits (Attribute memory x wait time) */
+#define FMC_PATTx_ATTWAITx_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATTx_ATTWAITx_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATTx_ATTWAITx_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATTx_ATTWAITx_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATTx_ATTWAITx_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATTx_ATTWAITx_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATTx_ATTWAITx_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATTx_ATTWAITx_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATTx_ATTHOLDx ((uint32_t)0x00FF0000) /*!<ATTHOLDx[7:0] bits (Attribute memory x hold time) */
+#define FMC_PATTx_ATTHOLDx_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATTx_ATTHOLDx_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATTx_ATTHOLDx_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATTx_ATTHOLDx_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATTx_ATTHOLDx_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATTx_ATTHOLDx_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATTx_ATTHOLDx_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATTx_ATTHOLDx_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATTx_ATTHIZx ((uint32_t)0xFF000000) /*!<ATTHIZx[7:0] bits (Attribute memory x databus HiZ time) */
+#define FMC_PATTx_ATTHIZx_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATTx_ATTHIZx_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATTx_ATTHIZx_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATTx_ATTHIZx_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATTx_ATTHIZx_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATTx_ATTHIZx_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATTx_ATTHIZx_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATTx_ATTHIZx_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT2 register ******************/
+#define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT3 register ******************/
+#define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PATT4 register ******************/
+#define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_PIO4 register *******************/
+#define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+#define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
+#define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
+#define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
+
+#define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
+#define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
+#define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
+#define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
+#define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
+#define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
+#define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
+#define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
+
+#define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+#define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
+#define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
+#define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
+#define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
+
+/****************** Bit definition for FMC_ECCR2 register ******************/
+#define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/****************** Bit definition for FMC_ECCR3 register ******************/
+#define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
+
+/******************************************************************************/
+/* */
+/* General Purpose I/O (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_15 ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
+#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
+#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
+#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
+#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
+#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
+#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
+#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
+#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
+#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *****************/
+#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
+#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *****************/
+#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
+#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
+#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
+#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
+#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
+#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
+#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
+#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
+#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
+#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
+#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register ********************/
+#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
+
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Power Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
+
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
+#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001)
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
+
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
+
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000)
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
+#define RCC_CR_CSSON ((uint32_t)0x00080000)
+#define RCC_CR_PLLON ((uint32_t)0x01000000)
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
+
+/******************** Bit definition for RCC_CFGR register ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
+
+#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
+#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
+#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
+#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
+#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
+#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
+#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
+#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
+#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
+
+/*!< I2S configuration */
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
+
+#define RCC_CFGR_I2SSRC_SYSCLK ((uint32_t)0x00000000) /*!< System clock selected as I2S clock source */
+#define RCC_CFGR_I2SSRC_EXT ((uint32_t)0x00800000) /*!< External clock selected as I2S clock source */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler) */
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
+
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
+
+/********************* Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+/****************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00008000) /*!< SPI4 reset */
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
+#define RCC_APB2RSTR_TIM20RST ((uint32_t)0x00100000) /*!< TIM20 reset */
+
+/****************** Bit definition for RCC_APB1RSTR register ******************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
+#define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
+#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
+#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
+#define RCC_AHBENR_FMCEN ((uint32_t)0x00000020) /*!< FMC clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
+#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00010000) /*!< GPIOH clock enable */
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
+#define RCC_AHBENR_GPIOGEN ((uint32_t)0x00800000) /*!< GPIOG clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
+#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00008000) /*!< SPI4 clock enable */
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
+#define RCC_APB2ENR_TIM20EN ((uint32_t)0x00100000) /*!< TIM20 clock enable */
+
+/****************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
+#define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */
+
+/******************** Bit definition for RCC_BDCR register ******************/
+#define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/*!< RTC configuration */
+#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
+
+/******************** Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+/******************* Bit definition for RCC_AHBRSTR register ****************/
+#define RCC_AHBRSTR_FMCRST ((uint32_t)0x00000020) /*!< FMC reset */
+#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00010000) /*!< GPIOH reset */
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
+#define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00800000) /*!< GPIOG reset */
+#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
+#define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */
+#define RCC_AHBRSTR_ADC34RST ((uint32_t)0x20000000) /*!< ADC3 & ADC4 reset */
+
+/******************* Bit definition for RCC_CFGR2 register ******************/
+/*!< PREDIV configuration */
+#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
+#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
+#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
+#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
+#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
+#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
+#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
+#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
+#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
+#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
+#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
+#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
+#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
+#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
+#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
+#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
+#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
+
+/*!< ADCPRE12 configuration */
+#define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
+#define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+#define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
+
+#define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
+#define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
+#define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
+#define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
+#define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
+#define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
+#define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
+#define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
+#define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
+#define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
+#define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
+#define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
+#define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
+
+/*!< ADCPRE34 configuration */
+#define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */
+#define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+#define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */
+#define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */
+
+#define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
+#define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */
+#define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */
+#define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */
+#define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */
+#define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */
+#define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */
+#define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */
+#define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */
+#define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */
+#define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */
+#define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */
+#define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */
+
+/******************* Bit definition for RCC_CFGR3 register ******************/
+#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
+#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
+#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
+
+#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
+#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
+#define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
+#define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */
+
+#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
+#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
+#define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
+#define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
+#define RCC_CFGR3_I2C3SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C3 clock source */
+#define RCC_CFGR3_I2C3SW_SYSCLK ((uint32_t)0x00000040) /*!< System clock selected as I2C3 clock source */
+
+#define RCC_CFGR3_TIMSW ((uint32_t)0x0000AF00) /*!< TIMSW bits */
+#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
+#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
+#define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
+#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
+#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
+#define RCC_CFGR3_TIM20SW ((uint32_t)0x00008000) /*!< TIM20SW bits */
+#define RCC_CFGR3_TIM2SW ((uint32_t)0x01000000) /*!< TIM2SW bits */
+#define RCC_CFGR3_TIM34SW ((uint32_t)0x02000000) /*!< TIM34SW bits */
+#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
+#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
+#define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
+#define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
+#define RCC_CFGR3_TIM15SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM15 clock source */
+#define RCC_CFGR3_TIM15SW_PLL ((uint32_t)0x00000400) /*!< PLL clock used as TIM15 clock source */
+#define RCC_CFGR3_TIM16SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM16 clock source */
+#define RCC_CFGR3_TIM16SW_PLL ((uint32_t)0x00000800) /*!< PLL clock used as TIM16 clock source */
+#define RCC_CFGR3_TIM17SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM17 clock source */
+#define RCC_CFGR3_TIM17SW_PLL ((uint32_t)0x00002000) /*!< PLL clock used as TIM17 clock source */
+#define RCC_CFGR3_TIM20SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM20 clock source */
+#define RCC_CFGR3_TIM20SW_PLL ((uint32_t)0x00008000) /*!< PLL clock used as TIM20 clock source */
+
+#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
+#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
+#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
+
+#define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
+#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
+#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
+
+#define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */
+#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
+#define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
+
+#define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */
+#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
+#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
+
+#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
+#define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
+
+#define RCC_CFGR3_TIM2SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM2 clock source */
+#define RCC_CFGR3_TIM2SW_PLL ((uint32_t)0x01000000) /*!< PLL clock used as TIM2 clock source */
+
+#define RCC_CFGR3_TIM34SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM3/TIM4 clock source */
+#define RCC_CFGR3_TIM34SW_PLL ((uint32_t)0x02000000) /*!< PLL clock used as TIM3/TIM4 clock source */
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 16
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
+#define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+#define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
+#define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
+#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
+#define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
+#define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
+#define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
+#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
+#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
+#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
+#define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
+#define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
+#define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
+#define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
+#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
+#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
+#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration(SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_CFGR1_MEM_MODE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
+#define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
+#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00007900) /*!< DMA remap mask */
+#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
+#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
+#define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
+#define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
+#define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x01000000) /*!< I2C3 Fast mode plus */
+#define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
+#define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
+#define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
+#define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
+#define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
+#define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
+#define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
+
+/***************** Bit definition for SYSCFG_RCR register *******************/
+#define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
+#define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
+#define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
+#define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
+#define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
+#define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
+#define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
+#define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
+#define SYSCFG_RCR_PAGE8 ((uint32_t)0x00000100) /*!< ICODE SRAM Write protection page 8 */
+#define SYSCFG_RCR_PAGE9 ((uint32_t)0x00000200) /*!< ICODE SRAM Write protection page 9 */
+#define SYSCFG_RCR_PAGE10 ((uint32_t)0x00000400) /*!< ICODE SRAM Write protection page 10 */
+#define SYSCFG_RCR_PAGE11 ((uint32_t)0x00000800) /*!< ICODE SRAM Write protection page 11 */
+#define SYSCFG_RCR_PAGE12 ((uint32_t)0x00001000) /*!< ICODE SRAM Write protection page 12 */
+#define SYSCFG_RCR_PAGE13 ((uint32_t)0x00002000) /*!< ICODE SRAM Write protection page 13 */
+#define SYSCFG_RCR_PAGE14 ((uint32_t)0x00004000) /*!< ICODE SRAM Write protection page 14 */
+#define SYSCFG_RCR_PAGE15 ((uint32_t)0x00008000) /*!< ICODE SRAM Write protection page 15 */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
+
+/*!<*
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!< PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!< PH[0] pin */
+
+/*!<*
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!< PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!< PH[1] pin */
+
+/*!<*
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!< PG[2] pin */
+
+/*!<*
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!< PG[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
+
+/*!<*
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!< PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!< PH[4] pin */
+
+/*!<*
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!< PG[5] pin */
+
+/*!<*
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!< PG[6] pin */
+
+/*!<*
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!< PG[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
+
+/*!<*
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!< PG[8] pin */
+
+/*!<*
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!< PG[9] pin */
+
+/*!<*
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!< PG[10] pin */
+
+/*!<*
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!< PG[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
+
+/*!<*
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!< PG[12] pin */
+
+/*!<*
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!< PG[13] pin */
+
+/*!<*
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!< PG[14] pin */
+
+/*!<*
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!< PG[15] pin */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
+#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
+#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+/***************** Bit definition for SYSCFG_CFGR4 register *****************/
+#define SYSCFG_CFGR4_ADC12_EXT2_RMP ((uint32_t)0x00000001) /*!< ADC12 regular channel EXT2 remap */
+#define SYSCFG_CFGR4_ADC12_EXT3_RMP ((uint32_t)0x00000002) /*!< ADC12 regular channel EXT3 remap */
+#define SYSCFG_CFGR4_ADC12_EXT5_RMP ((uint32_t)0x00000004) /*!< ADC12 regular channel EXT5 remap */
+#define SYSCFG_CFGR4_ADC12_EXT13_RMP ((uint32_t)0x00000008) /*!< ADC12 regular channel EXT13 remap */
+#define SYSCFG_CFGR4_ADC12_EXT15_RMP ((uint32_t)0x00000010) /*!< ADC12 regular channel EXT15 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT3_RMP ((uint32_t)0x00000020) /*!< ADC12 injected channel JEXT3 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT6_RMP ((uint32_t)0x00000040) /*!< ADC12 injected channel JEXT6 remap */
+#define SYSCFG_CFGR4_ADC12_JEXT13_RMP ((uint32_t)0x00000080) /*!< ADC12 injected channel JEXT13 remap */
+#define SYSCFG_CFGR4_ADC34_EXT5_RMP ((uint32_t)0x00000100) /*!< ADC34 regular channel EXT5 remap */
+#define SYSCFG_CFGR4_ADC34_EXT6_RMP ((uint32_t)0x00000200) /*!< ADC34 regular channel EXT6 remap */
+#define SYSCFG_CFGR4_ADC34_EXT15_RMP ((uint32_t)0x00000400) /*!< ADC34 regular channel EXT15 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT5_RMP ((uint32_t)0x00000800) /*!< ADC34 injected channel JEXT5 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT11_RMP ((uint32_t)0x00001000) /*!< ADC34 injected channel JEXT11 remap */
+#define SYSCFG_CFGR4_ADC34_JEXT14_RMP ((uint32_t)0x00002000) /*!< ADC34 injected channel JEXT14 remap */
+
+/******************************************************************************/
+/* */
+/* TIM */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
+#define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
+#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
+#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
+#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
+#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
+#define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
+#define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
+#define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
+#define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
+#define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
+#define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
+#define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
+#define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_RCR register ********************/
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_CCR5 register *******************/
+#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
+
+/******************* Bit definition for TIM_CCR6 register *******************/
+#define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
+
+/******************* Bit definition for TIM_BDTR register *******************/
+#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
+#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
+
+#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+
+#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
+#define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
+
+#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM16_OR register *********************/
+#define TIM16_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
+#define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+
+/******************* Bit definition for TIM1_OR register *********************/
+#define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
+#define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+/******************* Bit definition for TIM8_OR register *********************/
+#define TIM8_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
+#define TIM8_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM8_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM8_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM8_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+/******************* Bit definition for TIM20_OR register *******************/
+#define TIM20_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM20 ETR remap) */
+#define TIM20_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define TIM20_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define TIM20_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define TIM20_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR3 register *******************/
+#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
+#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
+#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
+#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
+
+#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
+#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
+
+#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
+#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
+
+#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
+#define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
+#define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
+
+#define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
+#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
+#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
+
+#define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
+#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
+#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
+
+#define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
+#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
+#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
+#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
+#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
+#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
+#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
+
+#define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
+#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
+#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
+#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
+#define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
+#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
+#define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
+#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
+#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
+#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
+#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
+#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
+#define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
+#define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
+#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
+#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
+#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
+#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
+#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
+#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
+#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
+#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
+#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
+#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
+#define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
+#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
+#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
+#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
+#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
+#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
+#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
+#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
+#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
+#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
+#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
+#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
+#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
+#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
+#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG */
+/* */
+/******************************************************************************/
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
+#define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
+#define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
+#define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
+#define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
+#define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
+#define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
+
+#define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC2) || \
+ ((INSTANCE) == ADC3) || \
+ ((INSTANCE) == ADC4))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+ ((INSTANCE) == ADC3))
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON) || \
+ ((INSTANCE) == ADC3_4_COMMON))
+
+/****************************** CAN Instances *********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
+
+/****************************** COMP Instances ********************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2) || \
+ ((INSTANCE) == COMP3) || \
+ ((INSTANCE) == COMP4) || \
+ ((INSTANCE) == COMP5) || \
+ ((INSTANCE) == COMP6) || \
+ ((INSTANCE) == COMP7))
+
+
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
+ ((INSTANCE) == COMP4) || \
+ ((INSTANCE) == COMP6))
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == DAC1) && \
+ (((CHANNEL) == DAC_CHANNEL_1) || \
+ ((CHANNEL) == DAC_CHANNEL_2))))
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7) || \
+ ((INSTANCE) == DMA2_Channel1) || \
+ ((INSTANCE) == DMA2_Channel2) || \
+ ((INSTANCE) == DMA2_Channel3) || \
+ ((INSTANCE) == DMA2_Channel4) || \
+ ((INSTANCE) == DMA2_Channel5))
+
+/****************************** GPIO Instances ********************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF) || \
+ ((INSTANCE) == GPIOG) || \
+ ((INSTANCE) == GPIOH))
+
+/****************************** I2C Instances *********************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************************** I2S Instances *********************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3))
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+ ((INSTANCE) == OPAMP2) || \
+ ((INSTANCE) == OPAMP3) || \
+ ((INSTANCE) == OPAMP4))
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************************** SPI Instances *********************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2) || \
+ ((INSTANCE) == SPI3) || \
+ ((INSTANCE) == SPI4))
+
+/******************* TIM Instances : All supported instances ******************/
+#define IS_TIM_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/******************* TIM Instances : at least 1 capture/compare channel *******/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 2 capture/compare channels *******/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 3 capture/compare channels *******/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 4 capture/compare channels *******/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 5 capture/compare channels *******/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : at least 6 capture/compare channels *******/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/************************** TIM Instances : Advanced-control timers ***********/
+
+/****************** TIM Instances : supporting clock selection ****************/
+#define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting Hall interface *****************/
+#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting input XOR function *************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting master mode ********************/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting slave mode *********************/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting 32 bits counter ****************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+ ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : supporting DMA burst **********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting input/output channel(s) ********/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ (((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM3) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM4) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM20) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM1) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM8) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))) \
+ || \
+ (((INSTANCE) == TIM15) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM16) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM17) && \
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM20) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting 2 break inputs *****************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting DMA generation on Update events*/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting DMA generation on Capture/Compare events */
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting remapping capability ***********/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM20))
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/****************** UART Instances : Driver Enable ****************************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART3) || \
+ ((INSTANCE) == UART4) || \
+ ((INSTANCE) == UART5))
+
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32F3xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32F3 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define SDADC1_IRQn ADC4_IRQn
+#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
+#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
+#define COMP1_2_IRQn COMP1_2_3_IRQn
+#define COMP2_IRQn COMP1_2_3_IRQn
+#define COMP_IRQn COMP1_2_3_IRQn
+#define COMP4_6_IRQn COMP4_5_6_IRQn
+#define HRTIM1_FLT_IRQn I2C3_ER_IRQn
+#define HRTIM1_TIME_IRQn I2C3_EV_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM19_IRQn TIM20_UP_IRQn
+#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
+#define TIM7_DAC2_IRQn TIM7_IRQn
+#define TIM12_IRQn TIM8_BRK_IRQn
+#define TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM13_IRQn TIM8_UP_IRQn
+
+
+/* Aliases for __IRQHandler */
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define SDADC1_IRQHandler ADC4_IRQHandler
+#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
+#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
+#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP_IRQHandler COMP1_2_3_IRQHandler
+#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
+#define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
+#define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM19_IRQHandler TIM20_UP_IRQHandler
+#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
+#define TIM12_IRQHandler TIM8_BRK_IRQHandler
+#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM13_IRQHandler TIM8_UP_IRQHandler
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F398xx_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/os/ext/CMSIS/ST/stm32f3xx.h b/os/ext/CMSIS/ST/stm32f3xx.h index a196a62c3..54705ec7c 100644 --- a/os/ext/CMSIS/ST/stm32f3xx.h +++ b/os/ext/CMSIS/ST/stm32f3xx.h @@ -2,8 +2,8 @@ ******************************************************************************
* @file stm32f3xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
+ * @version V2.2.0
+ * @date 13-November-2015
* @brief CMSIS STM32F3xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -64,31 +64,47 @@ * @{
*/
+/**
+ * @brief STM32 Family
+ */
+#if !defined (STM32F3)
+#define STM32F3
+#endif /* STM32F3 */
+
/* Uncomment the line below according to the target STM32 device used in your
application
*/
-#if !defined (STM32F301x8) && !defined (STM32F318xx) && \
- !defined (STM32F302x8) && !defined (STM32F302xC) && \
- !defined (STM32F303x8) && \
- !defined (STM32F303xC) && !defined (STM32F358xx) && \
- !defined (STM32F373xC) && !defined (STM32F378xx) && \
- !defined (STM32F334x8) && !defined (STM32F328xx)
+#if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \
+ !defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \
+ !defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \
+ !defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \
+ !defined (STM32F373xC) && !defined (STM32F378xx)
+
/* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8,
STM32F301R6 and STM32F301R8 Devices */
/* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8,
STM32F302R6 and STM32F302R8 Devices */
- /* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB and STM32F302VC Devices */
+ /* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC,
+ STM32F302VB and STM32F302VC Devices */
+ /* #define STM32F302xE */ /*!< STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD,
+ STM32F302VD and STM32F302ZD Devices */
/* #define STM32F303x8 */ /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8,
STM32F303R6 and STM32F303R8 Devices */
- /* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */
- /* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC, STM32F373R8, STM32F373RB, STM32F373RC,
+ /* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC,
+ STM32F303VB and STM32F303VC Devices */
+ /* #define STM32F303xE */ /*!< STM32F303RE, STM32F303VE, STM32F303ZE, STM32F303RD,
+ STM32F303VD and STM32F303ZD Devices */
+ /* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC,
+ STM32F373R8, STM32F373RB, STM32F373RC,
STM32F373V8, STM32F373VB and STM32F373VC Devices */
- /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
+ /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8,
+ STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
/* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */
/* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */
/* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */
/* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */
+ /* #define STM32F398xx */ /*!< STM32F398CE, STM32F398RE, STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -104,11 +120,11 @@ #endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V2.0.1
+ * @brief CMSIS Device version number V2.2.0
*/
#define __STM32F3xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
-#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
+#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F3xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F3xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
@@ -129,10 +145,14 @@ #include "stm32f302x8.h"
#elif defined(STM32F302xC)
#include "stm32f302xc.h"
+#elif defined(STM32F302xE)
+ #include "stm32f302xe.h"
#elif defined(STM32F303x8)
#include "stm32f303x8.h"
#elif defined(STM32F303xC)
#include "stm32f303xc.h"
+#elif defined(STM32F303xE)
+ #include "stm32f303xe.h"
#elif defined(STM32F373xC)
#include "stm32f373xc.h"
#elif defined(STM32F334x8)
@@ -145,6 +165,8 @@ #include "stm32f358xx.h"
#elif defined(STM32F378xx)
#include "stm32f378xx.h"
+#elif defined(STM32F398xx)
+ #include "stm32f398xx.h"
#else
#error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)"
#endif
diff --git a/os/ext/CMSIS/ST/system_stm32f3xx.h b/os/ext/CMSIS/ST/system_stm32f3xx.h index 90869e53a..91d3861ea 100644 --- a/os/ext/CMSIS/ST/system_stm32f3xx.h +++ b/os/ext/CMSIS/ST/system_stm32f3xx.h @@ -2,13 +2,13 @@ ******************************************************************************
* @file system_stm32f3xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
+ * @version V2.2.0
+ * @date 13-November-2015
* @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.h b/os/hal/ports/STM32/STM32F3xx/hal_lld.h index efedb4b9a..5c241cac3 100644 --- a/os/hal/ports/STM32/STM32F3xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.h @@ -29,12 +29,15 @@ * - STM32F301x8 for Analog & DSP devices.
* - STM32F302x8 for Analog & DSP devices.
* - STM32F302xC for Analog & DSP devices.
+ * - STM32F302xE for Analog & DSP devices.
* - STM32F303x8 for Analog & DSP devices.
* - STM32F303xC for Analog & DSP devices.
+ * - STM32F303xE for Analog & DSP devices.
* - STM32F318xx for Analog & DSP devices.
* - STM32F328xx for Analog & DSP devices.
* - STM32F334x8 for Analog & DSP devices.
* - STM32F358xx for Analog & DSP devices.
+ * - STM32F398xx for Analog & DSP devices.
* .
*
* @addtogroup HAL
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_isr.h b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h index 24ed66492..95b2d05bc 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h @@ -59,6 +59,11 @@ #define STM32_I2C2_EVENT_NUMBER 33
#define STM32_I2C2_ERROR_NUMBER 34
+#define STM32_I2C3_EVENT_HANDLER Vector160
+#define STM32_I2C3_ERROR_HANDLER Vector164
+#define STM32_I2C3_EVENT_NUMBER 72
+#define STM32_I2C3_ERROR_NUMBER 73
+
/*
* TIM units.
*/
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h index 36ceae28e..25de802d8 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h @@ -208,11 +208,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM9 FALSE
@@ -278,6 +278,256 @@ #endif /* defined(STM32F303xC) */
/*===========================================================================*/
+/* STM32F303xE. */
+/*===========================================================================*/
+#if defined(STM32F303xE)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 TRUE
+#define STM32_HAS_ADC4 TRUE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN | \
+ RCC_AHBENR_GPIOGEN | \
+ RCC_AHBENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM20 TRUE
+#define STM32_TIM20_IS_32BITS FALSE
+#define STM32_TIM20_CHANNELS 4
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 768
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F303xE) */
+
+/*===========================================================================*/
/* STM32F303x8. */
/*===========================================================================*/
#if defined(STM32F303x8)
@@ -420,11 +670,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM8 FALSE
@@ -622,11 +872,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM3 FALSE
#define STM32_HAS_TIM4 FALSE
@@ -827,11 +1077,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM3 FALSE
#define STM32_HAS_TIM4 FALSE
@@ -1055,11 +1305,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM7 FALSE
@@ -1127,6 +1377,245 @@ #endif /* defined(STM32F302xC) */
/*===========================================================================*/
+/* STM32F302xE. */
+/*===========================================================================*/
+#if defined(STM32F302xE)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 FALSE
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN | \
+ RCC_AHBENR_GPIOGEN | \
+ RCC_AHBENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM20 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB TRUE
+#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
+#define STM32_USB_PMA_SIZE 768
+#define STM32_USB_HAS_BCDR FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F302xE) */
+
+/*===========================================================================*/
/* STM32F318x8. */
/*===========================================================================*/
#if defined(STM32F318x8)
@@ -1264,11 +1753,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM3 FALSE
#define STM32_HAS_TIM4 FALSE
@@ -1469,11 +1958,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM4 FALSE
#define STM32_HAS_TIM5 FALSE
@@ -1536,7 +2025,7 @@ /*===========================================================================*/
/* STM32F358xC. */
/*===========================================================================*/
-#if defined(STM32F358xC) || defined(__DOXYGEN__)
+#if defined(STM32F358xC)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE
@@ -1694,11 +2183,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM7 FALSE
@@ -1768,7 +2257,7 @@ /*===========================================================================*/
/* STM32F334x8. */
/*===========================================================================*/
-#if defined(STM32F334x8) || defined(__DOXYGEN__)
+#if defined(STM32F334x8)
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 TRUE
@@ -1904,11 +2393,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM4 FALSE
#define STM32_HAS_TIM5 FALSE
@@ -1968,6 +2457,254 @@ #define STM32_CRC_PROGRAMMABLE TRUE
#endif /* defined(STM32F334x8) */
+/*===========================================================================*/
+/* STM32F398xx. */
+/*===========================================================================*/
+#if defined(STM32F398xx)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 TRUE
+#define STM32_HAS_ADC3 TRUE
+#define STM32_HAS_ADC4 TRUE
+
+#define STM32_HAS_SDADC1 FALSE
+#define STM32_HAS_SDADC2 FALSE
+#define STM32_HAS_SDADC3 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 TRUE
+#define STM32_HAS_CAN2 FALSE
+#define STM32_CAN_MAX_FILTERS 14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1_CH1 TRUE
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#define STM32_HAS_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+
+#define STM32_HAS_DAC2_CH1 FALSE
+#define STM32_HAS_DAC2_CH2 FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_DMA_SUPPORTS_CSELR FALSE
+
+#define STM32_DMA1_NUM_CHANNELS 7
+#define STM32_DMA1_CH1_HANDLER Vector6C
+#define STM32_DMA1_CH2_HANDLER Vector70
+#define STM32_DMA1_CH3_HANDLER Vector74
+#define STM32_DMA1_CH4_HANDLER Vector78
+#define STM32_DMA1_CH5_HANDLER Vector7C
+#define STM32_DMA1_CH6_HANDLER Vector80
+#define STM32_DMA1_CH7_HANDLER Vector84
+#define STM32_DMA1_CH1_NUMBER 11
+#define STM32_DMA1_CH2_NUMBER 12
+#define STM32_DMA1_CH3_NUMBER 13
+#define STM32_DMA1_CH4_NUMBER 14
+#define STM32_DMA1_CH5_NUMBER 15
+#define STM32_DMA1_CH6_NUMBER 16
+#define STM32_DMA1_CH7_NUMBER 17
+
+#define STM32_DMA2_NUM_CHANNELS 5
+#define STM32_DMA2_CH1_HANDLER Vector120
+#define STM32_DMA2_CH2_HANDLER Vector124
+#define STM32_DMA2_CH3_HANDLER Vector128
+#define STM32_DMA2_CH4_HANDLER Vector12C
+#define STM32_DMA2_CH5_HANDLER Vector130
+#define STM32_DMA2_CH1_NUMBER 56
+#define STM32_DMA2_CH2_NUMBER 57
+#define STM32_DMA2_CH3_NUMBER 58
+#define STM32_DMA2_CH4_NUMBER 59
+#define STM32_DMA2_CH5_NUMBER 60
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_LINES 34
+#define STM32_EXTI_IMR_MASK 0x1F800000U
+#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE TRUE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG TRUE
+#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI FALSE
+#define STM32_HAS_GPIOJ FALSE
+#define STM32_HAS_GPIOK FALSE
+#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
+ RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | \
+ RCC_AHBENR_GPIODEN | \
+ RCC_AHBENR_GPIOEEN | \
+ RCC_AHBENR_GPIOFEN | \
+ RCC_AHBENR_GPIOGEN | \
+ RCC_AHBENR_GPIOHEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#define STM32_HAS_I2C4 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_HAS_INTERRUPTS FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI1_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI2_SUPPORTS_I2S TRUE
+#define STM32_SPI2_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 TRUE
+#define STM32_SPI3_SUPPORTS_I2S TRUE
+#define STM32_SPI3_I2S_FULLDUPLEX TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4 TRUE
+#define STM32_SPI4_SUPPORTS_I2S FALSE
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS 6
+
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 6
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM4 TRUE
+#define STM32_TIM4_IS_32BITS FALSE
+#define STM32_TIM4_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM7 TRUE
+#define STM32_TIM7_IS_32BITS FALSE
+#define STM32_TIM7_CHANNELS 0
+
+#define STM32_HAS_TIM8 TRUE
+#define STM32_TIM8_IS_32BITS FALSE
+#define STM32_TIM8_CHANNELS 6
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 1
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 1
+
+#define STM32_HAS_TIM20 TRUE
+#define STM32_TIM20_IS_32BITS FALSE
+#define STM32_TIM20_CHANNELS 4
+
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM14 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+#define STM32_HAS_TIM21 FALSE
+#define STM32_HAS_TIM22 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3 TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4 TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5 TRUE
+
+#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
+#define STM32_HAS_LPUART1 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+/* IWDG attributes.*/
+#define STM32_HAS_IWDG TRUE
+#define STM32_IWDG_IS_WINDOWED TRUE
+
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
+/* FSMC attributes.*/
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC FALSE
+
+/* CRC attributes.*/
+#define STM32_HAS_CRC TRUE
+#define STM32_CRC_PROGRAMMABLE TRUE
+#endif /* defined(STM32F398xx) */
+
/** @} */
#endif /* _STM32_REGISTRY_H_ */
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index 2afd17b9a..cd5b0ccc5 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -746,6 +746,7 @@ /* FSMC attributes.*/
#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_IS_FMC FALSE
#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 1) |\
STM32_DMA_STREAM_ID_MSK(2, 2) |\
diff --git a/readme.txt b/readme.txt index 3995ed119..89b6ff12e 100644 --- a/readme.txt +++ b/readme.txt @@ -85,6 +85,7 @@ - HAL: Added "lines" handling to PAL driver, lines are identifiers of both
ports and pins encoded in a single value. Added a set of macros
operating on lines.
+- HAL: Merged the latest STM32F3xx CMSIS headers.
- HAL: Merged the latest STM32F2xx CMSIS headers and fixed the support
broken in 3.0.x.
- RT: Added new function chVTGetTimersStateI() returning the state of the
|