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-rw-r--r--os/ext/CMSIS/ST/stm32f358xx.h362
1 files changed, 213 insertions, 149 deletions
diff --git a/os/ext/CMSIS/ST/stm32f358xx.h b/os/ext/CMSIS/ST/stm32f358xx.h
index c6f4db0aa..b9e7d773a 100644
--- a/os/ext/CMSIS/ST/stm32f358xx.h
+++ b/os/ext/CMSIS/ST/stm32f358xx.h
@@ -2,9 +2,9 @@
******************************************************************************
* @file stm32f358xx.h
* @author MCD Application Team
- * @version V2.0.1
- * @date 18-June-2014
- * @brief CMSIS STM32F358xx Device Peripheral Access Layer Header File.
+ * @version V2.2.0
+ * @date 13-November-2015
+ * @brief CMSIS STM32F358xx Devices Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+ * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -63,11 +63,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32F358xx devices provide an MPU */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32F358xx devices provide an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32F358xx devices use 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< STM32F358xx devices provide an FPU */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< STM32F358xx devices provide an FPU */
/**
* @}
@@ -111,8 +111,8 @@ typedef enum
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
- CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */
- CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */
+ CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */
+ CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */
CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
@@ -142,7 +142,7 @@ typedef enum
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
@@ -153,7 +153,7 @@ typedef enum
COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
- FPU_IRQn = 81 /*!< Floating point Interrupt */
+ FPU_IRQn = 81, /*!< Floating point Interrupt */
} IRQn_Type;
/**
@@ -356,8 +356,8 @@ typedef struct
typedef struct
{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
@@ -366,20 +366,20 @@ typedef struct
typedef struct
{
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
- __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
- __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
- __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
- __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
- __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
}EXTI_TypeDef;
/**
@@ -427,8 +427,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
@@ -449,10 +448,10 @@ typedef struct
typedef struct
{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
__IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
} SYSCFG_TypeDef;
/**
@@ -568,13 +567,13 @@ typedef struct
typedef struct
{
- __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
- __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
@@ -666,14 +665,12 @@ typedef struct
* @{
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 256KB) base address in the alias region */
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 40KB) base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the bit-band region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 40KB) base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
@@ -768,7 +765,7 @@ typedef struct
#define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
#define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
/**
* @}
*/
@@ -796,9 +793,9 @@ typedef struct
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define CAN ((CAN_TypeDef *) CAN_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
@@ -806,12 +803,12 @@ typedef struct
#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
-#define COMP ((COMP_TypeDef *) COMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
-#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
@@ -852,6 +849,7 @@ typedef struct
#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
#define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
#define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
+
/**
* @}
*/
@@ -873,6 +871,7 @@ typedef struct
/* Analog to Digital Converter SAR (ADC) */
/* */
/******************************************************************************/
+
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
@@ -1739,6 +1738,7 @@ typedef struct
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
+
/********************** Bit definition for COMP1_CSR register ***************/
#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
@@ -1954,7 +1954,6 @@ typedef struct
#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
-#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
@@ -3378,7 +3377,7 @@ typedef struct
#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
@@ -3631,7 +3630,7 @@ typedef struct
/* External Interrupt/Event Controller (EXTI) */
/* */
/******************************************************************************/
-/******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
+/******************* Bit definition for EXTI_IMR register *******************/
#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
@@ -3661,8 +3660,11 @@ typedef struct
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-/******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
+/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
@@ -3692,8 +3694,11 @@ typedef struct
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
+#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
+#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
+#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-/****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
+/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
@@ -3717,14 +3722,11 @@ typedef struct
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
-#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
-#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
-#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
-#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
-#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
+#define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */
+#define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */
+#define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
@@ -3748,14 +3750,11 @@ typedef struct
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
-#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
-#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
-#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
-#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
-#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
-
-/****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
+#define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */
+#define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */
+#define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
@@ -3779,14 +3778,11 @@ typedef struct
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
-#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
-#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
-#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
-#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
-#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
-
-/******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
+#define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */
+#define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */
+#define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */
+
+/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
@@ -3810,12 +3806,37 @@ typedef struct
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
-#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
-#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
-#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
-#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
-#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
-#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
+#define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */
+#define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */
+#define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */
+
+/******************* Bit definition for EXTI_IMR2 register ******************/
+#define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */
+
+/******************* Bit definition for EXTI_EMR2 ****************************/
+#define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */
+#define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */
+#define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */
+#define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 34 */
+
+/****************** Bit definition for EXTI_RTSR2 register ********************/
+#define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */
+#define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_FTSR2 register ******************/
+#define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */
+#define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 33 */
+
+/****************** Bit definition for EXTI_SWIER2 register *****************/
+#define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */
+#define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 33 */
+
+/******************* Bit definition for EXTI_PR2 register *******************/
+#define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */
+#define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 33 */
/******************************************************************************/
/* */
@@ -3880,6 +3901,11 @@ typedef struct
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
#define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
+#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */
+#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */
+
+/* Legacy defines */
+#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW
/****************** Bit definition for FLASH_WRPR register ******************/
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
@@ -3909,6 +3935,7 @@ typedef struct
/****************** Bit definition for FLASH_WRP3 register ******************/
#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
+
/******************************************************************************/
/* */
/* General Purpose I/O (GPIO) */
@@ -4223,7 +4250,7 @@ typedef struct
#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
+#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
@@ -4237,6 +4264,9 @@ typedef struct
#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
+/* Legacy defines */
+#define I2C_CR1_DFN I2C_CR1_DNF
+
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
@@ -4256,9 +4286,17 @@ typedef struct
#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
+#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
+#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *****************/
#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
@@ -4506,7 +4544,7 @@ typedef struct
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
-#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< Do not divide PLL to MCO */
/********************* Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
@@ -4568,7 +4606,7 @@ typedef struct
#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
+#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
@@ -4721,10 +4759,12 @@ typedef struct
#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
+#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
+/* Legacy defines */
+#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2
#define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
@@ -4734,14 +4774,11 @@ typedef struct
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
#define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
#define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
-
#define RCC_CFGR3_TIMSW ((uint32_t)0x00000300) /*!< TIMSW bits */
#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
-
#define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
#define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
-
#define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
#define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
@@ -4749,7 +4786,7 @@ typedef struct
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
+#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
@@ -4758,7 +4795,7 @@ typedef struct
#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
+#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
#define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
#define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
@@ -4767,7 +4804,7 @@ typedef struct
#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
+#define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART4 clock source */
#define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
#define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
#define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
@@ -4776,7 +4813,7 @@ typedef struct
#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
+#define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as UART5 clock source */
#define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
#define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
#define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
@@ -5146,7 +5183,7 @@ typedef struct
#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER ((uint32_t)0x00000010)
+#define RTC_BKP_NUMBER 16
/******************************************************************************/
/* */
@@ -5245,7 +5282,7 @@ typedef struct
/* System Configuration(SYSCFG) */
/* */
/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register *****************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
@@ -5255,8 +5292,8 @@ typedef struct
#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
-#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
+#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 Ch1 DMA remap */
+#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 Ch2 DMA remap */
#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
@@ -5460,9 +5497,9 @@ typedef struct
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
-/***************** Bit definition for SYSCFG_CFGR2 register *****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/8/15/16/17 */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
@@ -5729,7 +5766,7 @@ typedef struct
#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
+#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
@@ -6294,9 +6331,9 @@ typedef struct
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
#define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
- (((INSTANCE) == DAC1) && \
+ ((((INSTANCE) == DAC1) && \
(((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2)))
+ ((CHANNEL) == DAC_CHANNEL_2))))
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -6313,12 +6350,23 @@ typedef struct
((INSTANCE) == DMA2_Channel5))
/****************************** GPIO Instances ********************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOE) || \
- ((INSTANCE) == GPIOF))
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOD))
/****************************** I2C Instances *********************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
@@ -6328,15 +6376,15 @@ typedef struct
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
-
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3) || \
((INSTANCE) == OPAMP4))
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -6407,7 +6455,7 @@ typedef struct
#define IS_TIM_CC6_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
-
+
/************************** TIM Instances : Advanced-control timers ***********/
/****************** TIM Instances : supporting clock selection ****************/
@@ -6522,11 +6570,11 @@ typedef struct
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
- ((INSTANCE) == TIM15) || \
- ((INSTANCE) == TIM16) || \
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting the break function *************/
@@ -6589,10 +6637,10 @@ typedef struct
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))) \
- || \
+ || \
(((INSTANCE) == TIM8) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))) \
|| \
(((INSTANCE) == TIM15) && \
@@ -6710,7 +6758,7 @@ typedef struct
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
-
+
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
@@ -6752,6 +6800,9 @@ typedef struct
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
+/******************** UART Instances : Support of continuous communication using DMA ****/
+#define IS_UART_DMA_INSTANCE(INSTANCE) (1)
+
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
@@ -6769,31 +6820,44 @@ typedef struct
/******************************************************************************/
/* Aliases for __IRQn */
+#define ADC1_IRQn ADC1_2_IRQn
+#define SDADC1_IRQn ADC4_IRQn
+#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
+#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
+#define COMP1_2_IRQn COMP1_2_3_IRQn
+#define COMP2_IRQn COMP1_2_3_IRQn
+#define COMP_IRQn COMP1_2_3_IRQn
+#define COMP4_6_IRQn COMP4_5_6_IRQn
+#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM18_DAC2_IRQn TIM1_CC_IRQn
+#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM16_IRQn TIM1_UP_TIM16_IRQn
+#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
+#define TIM7_DAC2_IRQn TIM7_IRQn
+#define TIM12_IRQn TIM8_BRK_IRQn
+#define TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM13_IRQn TIM8_UP_IRQn
-#define ADC1_IRQn ADC1_2_IRQn
-#define USB_HP_CAN_TX_IRQn CAN_TX_IRQn
-#define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn
-#define TIM15_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM16_IRQn TIM1_UP_TIM16_IRQn
-#define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define COMP_IRQn COMP1_2_3_IRQn
-#define COMP2_IRQn COMP1_2_3_IRQn
-#define COMP1_2_IRQn COMP1_2_3_IRQn
-#define COMP4_6_IRQn COMP4_5_6_IRQn
-#define TIM6_DAC1_IRQn TIM6_DAC_IRQn
/* Aliases for __IRQHandler */
-#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
-#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
-#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define COMP_IRQHandler COMP1_2_3_IRQHandler
-#define COMP2_IRQHandler COMP1_2_3_IRQHandler
-#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
-#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
-#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define SDADC1_IRQHandler ADC4_IRQHandler
+#define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler
+#define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler
+#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP2_IRQHandler COMP1_2_3_IRQHandler
+#define COMP_IRQHandler COMP1_2_3_IRQHandler
+#define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
+#define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
+#define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
+#define TIM7_DAC2_IRQHandler TIM7_IRQHandler
+#define TIM12_IRQHandler TIM8_BRK_IRQHandler
+#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM13_IRQHandler TIM8_UP_IRQHandler
+
#ifdef __cplusplus
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-22 11:01:51 +0000