From c246d898d2d2c16972182dab3e7201c359c8b7da Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sat, 12 Dec 2015 16:26:56 +0000 Subject: New STM32F3xx CMSIS headers. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8587 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/ext/CMSIS/ST/stm32f301x8.h | 359 +- os/ext/CMSIS/ST/stm32f302x8.h | 398 +- os/ext/CMSIS/ST/stm32f302xc.h | 436 +- os/ext/CMSIS/ST/stm32f302xe.h | 7856 +++++++++++++++++++++++ os/ext/CMSIS/ST/stm32f303x8.h | 398 +- os/ext/CMSIS/ST/stm32f303xc.h | 391 +- os/ext/CMSIS/ST/stm32f303xe.h | 8346 +++++++++++++++++++++++++ os/ext/CMSIS/ST/stm32f318xx.h | 350 +- os/ext/CMSIS/ST/stm32f328xx.h | 384 +- os/ext/CMSIS/ST/stm32f334x8.h | 422 +- os/ext/CMSIS/ST/stm32f358xx.h | 362 +- os/ext/CMSIS/ST/stm32f373xc.h | 286 +- os/ext/CMSIS/ST/stm32f378xx.h | 252 +- os/ext/CMSIS/ST/stm32f398xx.h | 8139 ++++++++++++++++++++++++ os/ext/CMSIS/ST/stm32f3xx.h | 54 +- os/ext/CMSIS/ST/system_stm32f3xx.h | 6 +- os/hal/ports/STM32/STM32F3xx/hal_lld.h | 3 + os/hal/ports/STM32/STM32F3xx/stm32_isr.h | 5 + os/hal/ports/STM32/STM32F3xx/stm32_registry.h | 807 ++- os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 1 + readme.txt | 1 + 21 files changed, 27422 insertions(+), 1834 deletions(-) create mode 100644 os/ext/CMSIS/ST/stm32f302xe.h create mode 100644 os/ext/CMSIS/ST/stm32f303xe.h create mode 100644 os/ext/CMSIS/ST/stm32f398xx.h diff --git a/os/ext/CMSIS/ST/stm32f301x8.h b/os/ext/CMSIS/ST/stm32f301x8.h index 24ba4edac..40f595ae5 100644 --- a/os/ext/CMSIS/ST/stm32f301x8.h +++ b/os/ext/CMSIS/ST/stm32f301x8.h @@ -2,9 +2,9 @@ ****************************************************************************** * @file stm32f301x8.h * @author MCD Application Team - * @version V2.0.1 - * @date 18-June-2014 - * @brief CMSIS STM32F301x6/STM32F301x8 Devices Peripheral Access Layer Header File. + * @version V2.2.0 + * @date 13-November-2015 + * @brief CMSIS STM32F301x8 Devices Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals @@ -14,7 +14,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,11 +63,11 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< STM32F301x6/STM32F301x8 devices do not provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F301x6/STM32F301x8 devices use 4 Bits for the Priority Levels */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< STM32F301x8 devices do not provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F301x8 devices use 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< STM32F301x6/STM32F301x8 devices provide an FPU */ +#define __FPU_PRESENT 1 /*!< STM32F301x8 devices provide an FPU */ /** * @} @@ -78,7 +78,7 @@ */ /** - * @brief STM32F301x6/STM32F301x8 device Interrupt Number Definition, according to the selected device + * @brief STM32F301x8 devices Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum @@ -129,12 +129,12 @@ typedef enum EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel1 underrun error Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -235,20 +235,20 @@ typedef struct typedef struct { - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */ __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */ __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; /** @@ -277,8 +277,8 @@ typedef struct typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** @@ -287,20 +287,20 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,11 +63,11 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< STM32F302x6/STM32F302x8 devices do not provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F302x6/STM32F302x8 devices use 4 Bits for the Priority Levels */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< STM32F302x8 devices do not provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F302x8 devices use 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< STM32F302x6/STM32F302x8 devices provide an FPU */ +#define __FPU_PRESENT 1 /*!< STM32F302x8 devices provide an FPU */ /** * @} @@ -78,7 +78,7 @@ */ /** - * @brief STM32F302x6/STM32F302x8 device Interrupt Number Definition, according to the selected device + * @brief STM32F302x8 devices Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum @@ -134,15 +134,15 @@ typedef enum RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel1 underrun error Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */ - USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ - USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -303,20 +303,20 @@ typedef struct typedef struct { - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */ __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */ __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; /** @@ -345,8 +345,8 @@ typedef struct typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** @@ -355,20 +355,20 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,11 +63,11 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F302xB/STM32F302xC devices provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F302xB/STM32F302xC devices use 4 Bits for the Priority Levels */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F302xC devices provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F302xC devices use 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< STM32F302xB/STM32F302xC devices provide an FPU */ +#define __FPU_PRESENT 1 /*!< STM32F302xC devices provide an FPU */ /** * @} @@ -78,7 +78,7 @@ */ /** - * @brief STM32F302xB/STM32F302xC device Interrupt Number Definition, according to the selected device + * @brief STM32F302xC devices Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum @@ -139,7 +139,7 @@ typedef enum SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error Interrupts */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ @@ -147,10 +147,10 @@ typedef enum DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ COMP1_2_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt via EXTI Line21 and 22 */ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ - USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ - USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -316,14 +316,14 @@ typedef struct __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */ + __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; @@ -353,8 +353,8 @@ typedef struct typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** @@ -363,20 +363,20 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2015 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f302xe + * @{ + */ + +#ifndef __STM32F302xE_H +#define __STM32F302xE_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F302xE devices provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F302xE devices use 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< STM32F302xE devices provide an FPU */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F302xE devices Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ + USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */ + USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */ + CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ + CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ + USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */ + UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + COMP1_2_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt via EXTI Line21 and 22 */ + COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */ + USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f3xx.h" /* STM32F3xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, 0x010 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x01C */ + __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1/3 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief Analog Comparators + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */ + __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,11 +63,11 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< STM32F303x6/STM32F303x8 devices do not provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F303x6/STM32F303x8 devices use 4 Bits for the Priority Levels */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< STM32F303x8 devices do not provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F303x8 devices use 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< STM32F303x6/STM32F303x8 devices provide an FPU */ +#define __FPU_PRESENT 1 /*!< STM32F303x8 devices provide an FPU */ /** * @} @@ -78,7 +78,7 @@ */ /** - * @brief STM32F303x6/STM32F303x8 device Interrupt Number Definition, according to the selected device + * @brief STM32F303x8 devices Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum @@ -112,8 +112,8 @@ typedef enum DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ - CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */ - CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */ + CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */ + CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ @@ -130,12 +130,12 @@ typedef enum USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ - TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ + TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/ TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */ - COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */ - COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */ + COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -338,8 +338,8 @@ typedef struct typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** @@ -348,20 +348,20 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,11 +63,11 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F303xB/STM32F303xC devices provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F303xB/STM32F303xC devices use 4 Bits for the Priority Levels */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F303xC devices provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F303xC devices use 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< STM32F303xB/STM32F303xC devices provide an FPU */ +#define __FPU_PRESENT 1 /*!< STM32F303xC devices provide an FPU */ /** * @} @@ -78,7 +78,7 @@ */ /** - * @brief STM32F303xB/STM32F303xC devices Interrupt Number Definition, according to the selected device + * @brief STM32F303xC devices Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum @@ -144,7 +144,7 @@ typedef enum SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ @@ -155,10 +155,10 @@ typedef enum COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/ COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/ COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */ - USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ - USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */ USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -361,8 +361,8 @@ typedef struct typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** @@ -371,20 +371,20 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2015 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f303xe + * @{ + */ + +#ifndef __STM32F303xE_H +#define __STM32F303xE_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F303xE devices provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F303xE devices use 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< STM32F303xE devices provide an FPU */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F303xE devices Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ + USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */ + USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */ + CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ + CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ + USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */ + UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/ + COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/ + COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */ + USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */ + USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */ + USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f3xx.h" /* STM32F3xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, 0x010 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x01C */ + __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1/3 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief Analog Comparators + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,7 +63,7 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< STM32F318xx devices do not provide an MPU */ #define __NVIC_PRIO_BITS 4 /*!< STM32F318xx devices use 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ @@ -78,7 +78,7 @@ */ /** - * @brief STM32F318xx device Interrupt Number Definition, according to the selected device + * @brief STM32F318xx devices Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum @@ -128,12 +128,12 @@ typedef enum EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel1 underrun error Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */ COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt & EXTI Line27 Interrupt (I2C3 wakeup) */ I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -234,20 +234,20 @@ typedef struct typedef struct { - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t RESERVED0; /*!< Reserved, 0x14 */ __IO uint32_t RESERVED1; /*!< Reserved, 0x18 */ __IO uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t RESERVED3; /*!< Reserved, 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; /** @@ -276,8 +276,8 @@ typedef struct typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** @@ -286,20 +286,20 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,7 +63,7 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ #define __MPU_PRESENT 0 /*!< STM32F328xx devices do not provide an MPU */ #define __NVIC_PRIO_BITS 4 /*!< STM32F328xx devices use 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ @@ -78,7 +78,7 @@ */ /** - * @brief STM32F328xx device Interrupt Number Definition, according to the selected device + * @brief STM32F328xx devices Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum @@ -111,8 +111,8 @@ typedef enum DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ - CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */ - CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */ + CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */ + CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ @@ -129,12 +129,12 @@ typedef enum USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ - TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ + TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/ TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */ - COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */ - COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */ + COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -337,8 +337,8 @@ typedef struct typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** @@ -347,20 +347,20 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,11 +63,11 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices do not provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices use 4 Bits for the Priority Levels */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< STM32F334x8 devices do not provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F334x8 devices use 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices provide an FPU */ +#define __FPU_PRESENT 1 /*!< STM32F334x8 devices provide an FPU */ /** * @} @@ -78,7 +78,7 @@ */ /** - * @brief STM32F334x4/STM32F334x6/STM32F334x8 device Interrupt Number Definition, according to the selected device + * @brief STM32F334x8 devices Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum @@ -112,8 +112,8 @@ typedef enum DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ - CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */ - CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */ + CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */ + CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ @@ -130,11 +130,11 @@ typedef enum USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ - TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ + TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/ TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */ - COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */ - COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */ + COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXTI Line22 */ + COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXTI Line30 and 32 */ HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */ HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */ HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */ @@ -142,7 +142,7 @@ typedef enum HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */ HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */ HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -345,8 +345,8 @@ typedef struct typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** @@ -355,20 +355,20 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,11 +63,11 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F358xx devices provide an MPU */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F358xx devices provide an MPU */ #define __NVIC_PRIO_BITS 4 /*!< STM32F358xx devices use 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< STM32F358xx devices provide an FPU */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< STM32F358xx devices provide an FPU */ /** * @} @@ -111,8 +111,8 @@ typedef enum DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ - CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */ - CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */ + CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */ + CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */ CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ @@ -142,7 +142,7 @@ typedef enum SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */ UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ @@ -153,7 +153,7 @@ typedef enum COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/ COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/ COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -356,8 +356,8 @@ typedef struct typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** @@ -366,20 +366,20 @@ typedef struct typedef struct { - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ - __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ - __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ - __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ - __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ - __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,10 +64,10 @@ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ #define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F373xB/STM32F373xC devices provide an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F373xB/STM32F373xC devices use 4 Bits for the Priority Levels */ +#define __MPU_PRESENT 1 /*!< STM32F373xC devices provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F373xC devices use 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< STM32F373xB/STM32F373xC devices provide an FPU */ +#define __FPU_PRESENT 1 /*!< STM32F373xC devices provide an FPU */ /** * @} @@ -78,7 +78,7 @@ */ /** - * @brief STM32F373xB/STM32F373xC devices Interrupt Number Definition, according to the selected device + * @brief STM32F373xC devices Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum @@ -141,7 +141,7 @@ typedef enum TIM14_IRQn = 45, /*!< TIM14 global interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/ + TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ @@ -156,7 +156,7 @@ typedef enum USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */ USBWakeUp_IRQn = 76, /*!< USB Wakeup Interrupt */ TIM19_IRQn = 78, /*!< TIM19 global Interrupt */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -198,8 +198,6 @@ typedef struct __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ } ADC_TypeDef; - - /** * @brief Controller Area Network TxMailBox */ @@ -415,8 +413,7 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ @@ -430,7 +427,7 @@ typedef struct { __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ uint32_t RESERVED; /*!< Reserved, 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG control register, Adress offset: 0x14-0x08 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ } SYSCFG_TypeDef; @@ -593,13 +590,13 @@ typedef struct typedef struct { - __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; @@ -705,7 +702,7 @@ typedef struct __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ __IO uint16_t RESERVEDB; /*!< Reserved */ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ - __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t RESERVEDC; /*!< Reserved */ } USB_TypeDef; /** @@ -725,7 +722,6 @@ typedef struct #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ @@ -760,9 +756,9 @@ typedef struct #define CAN_BASE (APB1PERIPH_BASE + 0x00006400) #define PWR_BASE (APB1PERIPH_BASE + 0x00007000) #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400) +#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800) #define DAC_BASE DAC1_BASE #define CEC_BASE (APB1PERIPH_BASE + 0x00007800) -#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800) #define TIM18_BASE (APB1PERIPH_BASE + 0x00009C00) /*!< APB2 peripherals */ @@ -847,14 +843,13 @@ typedef struct #define TIM18 ((TIM_TypeDef *) TIM18_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #define TIM19 ((TIM_TypeDef *) TIM19_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #define SDADC1 ((SDADC_TypeDef *) SDADC1_BASE) #define SDADC2 ((SDADC_TypeDef *) SDADC2_BASE) #define SDADC3 ((SDADC_TypeDef *) SDADC3_BASE) @@ -883,7 +878,9 @@ typedef struct #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define USB ((USB_TypeDef *) USB_BASE) + /** * @} */ @@ -1037,22 +1034,22 @@ typedef struct #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ /****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ /****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ /****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ /****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ /******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ +#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ /******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ +#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ /******************* Bit definition for ADC_SQR1 register *******************/ #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ @@ -1253,25 +1250,25 @@ typedef struct #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */ #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */ /* COMPx bits definition */ -#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */ -#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */ -#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */ -#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */ -#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */ -#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */ -#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */ -#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */ -#define COMP_CSR_COMPxWNDWEN ((uint16_t)0x0080) /*!< COMPx window mode enable */ -#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */ -#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */ -#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */ -#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */ -#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */ -#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */ -#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x2000) /*!< COMPx hysteresis bit 1 */ -#define COMP_CSR_COMPxOUT ((uint32_t)0x4000) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */ +#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */ +#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */ +#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */ +#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */ +#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */ +#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */ +#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */ +#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */ +#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000080) /*!< COMPx window mode enable */ +#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */ +#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */ +#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */ +#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */ +#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */ +#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */ +#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */ +#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */ +#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */ /******************************************************************************/ /* */ @@ -2538,7 +2535,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */ @@ -2876,17 +2873,7 @@ typedef struct #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ -#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */ -#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */ -#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */ -#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */ -#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */ -#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */ /****************** Bit definition for EXTI_FTSR register *******************/ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ @@ -2907,17 +2894,7 @@ typedef struct #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ -#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ -#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ -#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ -#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */ -#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */ -#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */ -#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */ -#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */ -#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */ /****************** Bit definition for EXTI_SWIER register ******************/ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ @@ -2938,17 +2915,7 @@ typedef struct #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ -#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ -#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ -#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ -#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */ -#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */ -#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */ -#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */ -#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */ -#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */ /******************* Bit definition for EXTI_PR register ********************/ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ @@ -2969,18 +2936,7 @@ typedef struct #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ -#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */ -#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */ -#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */ -#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */ -#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */ -#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */ -#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */ -#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */ -#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */ - /******************************************************************************/ /* */ /* FLASH */ @@ -3035,13 +2991,18 @@ typedef struct #define FLASH_OBR_LEVEL2_PROT ((uint32_t)0x00000004) /*!< Level 2 Read protection status */ #define FLASH_OBR_USER ((uint32_t)0x0000F700) /*!< User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ +#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */ #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */ #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */ #define FLASH_OBR_SDADC12_VDD_MONITOR ((uint32_t)0x00008000) /*!< SDADC12_VDD_MONITOR */ +#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */ +#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */ + +/* Legacy defines */ +#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW /****************** Bit definition for FLASH_WRPR register ******************/ #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ @@ -3071,6 +3032,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/ #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + /******************************************************************************/ /* */ /* General Purpose I/O (GPIO) */ @@ -3385,7 +3347,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */ #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */ #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */ -#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */ +#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */ #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */ #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */ #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */ @@ -3399,6 +3361,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */ #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */ +/* Legacy defines */ +#define I2C_CR1_DFN I2C_CR1_DNF + /****************** Bit definition for I2C_CR2 register ********************/ #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */ #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */ @@ -3418,9 +3383,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */ -#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */ +#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */ +#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register *****************/ #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */ @@ -3916,7 +3889,6 @@ typedef struct /******************** Bit definition for RCC_CSR register *******************/ #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */ #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */ #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ @@ -3965,10 +3937,12 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */ +#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */ #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */ #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */ #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */ +/* Legacy defines */ +#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */ #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */ @@ -3988,7 +3962,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */ #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */ +#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */ #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */ #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */ #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */ @@ -3997,7 +3971,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */ #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */ +#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */ #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */ #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */ #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */ @@ -4415,7 +4389,7 @@ typedef struct #define RTC_BKP31R ((uint32_t)0xFFFFFFFF) /******************** Number of backup registers ******************************/ -#define RTC_BKP_NUMBER ((uint32_t)0x00000020) +#define RTC_BKP_NUMBER 32 /******************************************************************************/ /* */ @@ -4785,7 +4759,7 @@ typedef struct #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00008000) /*!< PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */ @@ -4872,9 +4846,9 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */ /***************** Bit definition for SYSCFG_CFGR2 register ****************/ -#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM15/16/17 */ -#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM15/16/17 */ -#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */ +#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */ +#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */ +#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */ #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */ /******************************************************************************/ @@ -4899,7 +4873,6 @@ typedef struct #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -140,7 +140,7 @@ typedef enum TIM14_IRQn = 45, /*!< TIM14 global interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 Cahnnel1 & Cahnnel2 underrun error Interrupts*/ + TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error Interrupts*/ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ @@ -152,7 +152,7 @@ typedef enum SDADC3_IRQn = 63, /*!< ADC Sigma Delta 1 global Interrupt */ COMP_IRQn = 64, /*!< COMP1 and COMP2 global Interrupt */ TIM19_IRQn = 78, /*!< TIM19 global Interrupt */ - FPU_IRQn = 81 /*!< Floating point Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ } IRQn_Type; /** @@ -194,8 +194,6 @@ typedef struct __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ } ADC_TypeDef; - - /** * @brief Controller Area Network TxMailBox */ @@ -411,8 +409,7 @@ typedef struct __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ @@ -426,7 +423,7 @@ typedef struct { __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ uint32_t RESERVED; /*!< Reserved, 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG control register, Adress offset: 0x14-0x08 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ } SYSCFG_TypeDef; @@ -589,13 +586,13 @@ typedef struct typedef struct { - __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; @@ -687,7 +684,6 @@ typedef struct #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ @@ -720,9 +716,9 @@ typedef struct #define CAN_BASE (APB1PERIPH_BASE + 0x00006400) #define PWR_BASE (APB1PERIPH_BASE + 0x00007000) #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400) +#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800) #define DAC_BASE DAC1_BASE #define CEC_BASE (APB1PERIPH_BASE + 0x00007800) -#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800) #define TIM18_BASE (APB1PERIPH_BASE + 0x00009C00) /*!< APB2 peripherals */ @@ -807,14 +803,13 @@ typedef struct #define TIM18 ((TIM_TypeDef *) TIM18_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #define TIM19 ((TIM_TypeDef *) TIM19_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #define SDADC1 ((SDADC_TypeDef *) SDADC1_BASE) #define SDADC2 ((SDADC_TypeDef *) SDADC2_BASE) #define SDADC3 ((SDADC_TypeDef *) SDADC3_BASE) @@ -843,6 +838,8 @@ typedef struct #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) + /** * @} */ @@ -996,22 +993,22 @@ typedef struct #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ /****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ /****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ /****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ /****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ /******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ +#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ /******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ +#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ /******************* Bit definition for ADC_SQR1 register *******************/ #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ @@ -1212,25 +1209,25 @@ typedef struct #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */ #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */ /* COMPx bits definition */ -#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */ -#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */ -#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */ -#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */ -#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */ -#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */ -#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */ -#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */ -#define COMP_CSR_COMPxWNDWEN ((uint16_t)0x0080) /*!< COMPx window mode enable */ -#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */ -#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */ -#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */ -#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */ -#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */ -#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */ -#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */ -#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x2000) /*!< COMPx hysteresis bit 1 */ -#define COMP_CSR_COMPxOUT ((uint32_t)0x4000) /*!< COMPx output level */ -#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */ +#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */ +#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */ +#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */ +#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */ +#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */ +#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */ +#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */ +#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */ +#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000080) /*!< COMPx window mode enable */ +#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */ +#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */ +#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */ +#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */ +#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */ +#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */ +#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */ +#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */ +#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */ +#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */ /******************************************************************************/ /* */ @@ -2497,7 +2494,7 @@ typedef struct #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */ @@ -2835,17 +2832,7 @@ typedef struct #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ -#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ -#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ -#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ -#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */ -#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */ -#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */ -#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */ -#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */ -#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */ /****************** Bit definition for EXTI_FTSR register *******************/ #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ @@ -2866,17 +2853,7 @@ typedef struct #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ -#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ -#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ -#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ -#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */ -#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */ -#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */ -#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */ -#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */ -#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */ /****************** Bit definition for EXTI_SWIER register ******************/ #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ @@ -2897,17 +2874,7 @@ typedef struct #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ -#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ -#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ -#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ -#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */ -#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */ -#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */ -#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */ -#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */ -#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */ /******************* Bit definition for EXTI_PR register ********************/ #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ @@ -2928,18 +2895,7 @@ typedef struct #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ -#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */ -#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */ -#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */ -#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */ -#define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */ -#define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */ -#define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */ -#define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */ -#define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */ - /******************************************************************************/ /* */ /* FLASH */ @@ -2994,13 +2950,18 @@ typedef struct #define FLASH_OBR_LEVEL2_PROT ((uint32_t)0x00000004) /*!< Level 2 Read protection status */ #define FLASH_OBR_USER ((uint32_t)0x0000F700) /*!< User Option Bytes */ -#define FLASH_OBR_WDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ +#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */ #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */ #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */ #define FLASH_OBR_SDADC12_VDD_MONITOR ((uint32_t)0x00008000) /*!< SDADC12_VDD_MONITOR */ +#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< Data0 */ +#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< Data1 */ + +/* Legacy defines */ +#define FLASH_OBR_WDG_SW FLASH_OBR_IWDG_SW /****************** Bit definition for FLASH_WRPR register ******************/ #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ @@ -3030,6 +2991,7 @@ typedef struct /****************** Bit definition for FLASH_WRP3 register ******************/ #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + /******************************************************************************/ /* */ /* General Purpose I/O (GPIO) */ @@ -3344,7 +3306,7 @@ typedef struct #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */ #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */ #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */ -#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */ +#define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */ #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */ #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */ #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */ @@ -3358,6 +3320,9 @@ typedef struct #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */ #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */ +/* Legacy defines */ +#define I2C_CR1_DFN I2C_CR1_DNF + /****************** Bit definition for I2C_CR2 register ********************/ #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */ #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */ @@ -3377,9 +3342,17 @@ typedef struct #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */ /******************* Bit definition for I2C_OAR2 register *******************/ -#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */ -#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */ -#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */ +#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */ +#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */ /******************* Bit definition for I2C_TIMINGR register *****************/ #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */ @@ -3850,7 +3823,6 @@ typedef struct /******************** Bit definition for RCC_CSR register *******************/ #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */ #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */ #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ @@ -3899,10 +3871,12 @@ typedef struct #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */ +#define RCC_CFGR3_USART1SW_PCLK2 ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART1 clock source */ #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */ #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */ #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */ +/* Legacy defines */ +#define RCC_CFGR3_USART1SW_PCLK RCC_CFGR3_USART1SW_PCLK2 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */ #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */ @@ -3922,7 +3896,7 @@ typedef struct #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */ #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */ +#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART2 clock source */ #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */ #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */ #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */ @@ -3931,7 +3905,7 @@ typedef struct #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */ #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */ +#define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART3 clock source */ #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */ #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */ #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */ @@ -4349,7 +4323,7 @@ typedef struct #define RTC_BKP31R ((uint32_t)0xFFFFFFFF) /******************** Number of backup registers ******************************/ -#define RTC_BKP_NUMBER ((uint32_t)0x00000020) +#define RTC_BKP_NUMBER 32 /******************************************************************************/ /* */ @@ -4719,7 +4693,7 @@ typedef struct #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00008000) /*!< PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */ @@ -4806,8 +4780,8 @@ typedef struct #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */ /***************** Bit definition for SYSCFG_CFGR2 register ****************/ -#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM15/16/17 */ -#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM15/16/17 */ +#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx */ +#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */ #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */ /******************************************************************************/ @@ -4832,7 +4806,6 @@ typedef struct #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!
© COPYRIGHT(c) 2015 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32f398xx + * @{ + */ + +#ifndef __STM32F398xx_H +#define __STM32F398xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32F398xx devices provide an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32F398xx devices use 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< STM32F398xx devices provide an FPU */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32F398xx devices Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ + CAN_TX_IRQn = 19, /*!< CAN TX Interrupt */ + CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupt */ + CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ + CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ + USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ + USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */ + UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ + COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/ + COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/ + COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */ + FPU_IRQn = 81, /*!< Floating point Interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32f3xx.h" /* STM32F3xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + uint32_t RESERVED0; /*!< Reserved, 0x010 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x01C */ + __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1/3 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief Analog Comparators + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2014 STMicroelectronics
+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,31 +64,47 @@ * @{ */ +/** + * @brief STM32 Family + */ +#if !defined (STM32F3) +#define STM32F3 +#endif /* STM32F3 */ + /* Uncomment the line below according to the target STM32 device used in your application */ -#if !defined (STM32F301x8) && !defined (STM32F318xx) && \ - !defined (STM32F302x8) && !defined (STM32F302xC) && \ - !defined (STM32F303x8) && \ - !defined (STM32F303xC) && !defined (STM32F358xx) && \ - !defined (STM32F373xC) && !defined (STM32F378xx) && \ - !defined (STM32F334x8) && !defined (STM32F328xx) +#if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \ + !defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \ + !defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \ + !defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \ + !defined (STM32F373xC) && !defined (STM32F378xx) + /* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8, STM32F301R6 and STM32F301R8 Devices */ /* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8, STM32F302R6 and STM32F302R8 Devices */ - /* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, STM32F302VB and STM32F302VC Devices */ + /* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC, + STM32F302VB and STM32F302VC Devices */ + /* #define STM32F302xE */ /*!< STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD, + STM32F302VD and STM32F302ZD Devices */ /* #define STM32F303x8 */ /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8, STM32F303R6 and STM32F303R8 Devices */ - /* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */ - /* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC, STM32F373R8, STM32F373RB, STM32F373RC, + /* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, + STM32F303VB and STM32F303VC Devices */ + /* #define STM32F303xE */ /*!< STM32F303RE, STM32F303VE, STM32F303ZE, STM32F303RD, + STM32F303VD and STM32F303ZD Devices */ + /* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC, + STM32F373R8, STM32F373RB, STM32F373RC, STM32F373V8, STM32F373VB and STM32F373VC Devices */ - /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */ + /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8, + STM32F334R4, STM32F334R6 and STM32F334R8 Devices */ /* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */ /* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */ /* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */ /* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */ + /* #define STM32F398xx */ /*!< STM32F398CE, STM32F398RE, STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */ #endif /* Tip: To avoid modifying this file each time you need to switch between these @@ -104,11 +120,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.0.1 + * @brief CMSIS Device version number V2.2.0 */ #define __STM32F3xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __STM32F3xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F3xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F3xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ @@ -129,10 +145,14 @@ #include "stm32f302x8.h" #elif defined(STM32F302xC) #include "stm32f302xc.h" +#elif defined(STM32F302xE) + #include "stm32f302xe.h" #elif defined(STM32F303x8) #include "stm32f303x8.h" #elif defined(STM32F303xC) #include "stm32f303xc.h" +#elif defined(STM32F303xE) + #include "stm32f303xe.h" #elif defined(STM32F373xC) #include "stm32f373xc.h" #elif defined(STM32F334x8) @@ -145,6 +165,8 @@ #include "stm32f358xx.h" #elif defined(STM32F378xx) #include "stm32f378xx.h" +#elif defined(STM32F398xx) + #include "stm32f398xx.h" #else #error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)" #endif diff --git a/os/ext/CMSIS/ST/system_stm32f3xx.h b/os/ext/CMSIS/ST/system_stm32f3xx.h index 90869e53a..91d3861ea 100644 --- a/os/ext/CMSIS/ST/system_stm32f3xx.h +++ b/os/ext/CMSIS/ST/system_stm32f3xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f3xx.h * @author MCD Application Team - * @version V2.0.1 - * @date 18-June-2014 + * @version V2.2.0 + * @date 13-November-2015 * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.h b/os/hal/ports/STM32/STM32F3xx/hal_lld.h index efedb4b9a..5c241cac3 100644 --- a/os/hal/ports/STM32/STM32F3xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.h @@ -29,12 +29,15 @@ * - STM32F301x8 for Analog & DSP devices. * - STM32F302x8 for Analog & DSP devices. * - STM32F302xC for Analog & DSP devices. + * - STM32F302xE for Analog & DSP devices. * - STM32F303x8 for Analog & DSP devices. * - STM32F303xC for Analog & DSP devices. + * - STM32F303xE for Analog & DSP devices. * - STM32F318xx for Analog & DSP devices. * - STM32F328xx for Analog & DSP devices. * - STM32F334x8 for Analog & DSP devices. * - STM32F358xx for Analog & DSP devices. + * - STM32F398xx for Analog & DSP devices. * . * * @addtogroup HAL diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_isr.h b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h index 24ed66492..95b2d05bc 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h @@ -59,6 +59,11 @@ #define STM32_I2C2_EVENT_NUMBER 33 #define STM32_I2C2_ERROR_NUMBER 34 +#define STM32_I2C3_EVENT_HANDLER Vector160 +#define STM32_I2C3_ERROR_HANDLER Vector164 +#define STM32_I2C3_EVENT_NUMBER 72 +#define STM32_I2C3_ERROR_NUMBER 73 + /* * TIM units. */ diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h index 36ceae28e..25de802d8 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h @@ -208,11 +208,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM9 FALSE @@ -277,6 +277,256 @@ #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F303xC) */ +/*===========================================================================*/ +/* STM32F303xE. */ +/*===========================================================================*/ +#if defined(STM32F303xE) +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 TRUE +#define STM32_HAS_ADC4 TRUE + +#define STM32_HAS_SDADC1 FALSE +#define STM32_HAS_SDADC2 FALSE +#define STM32_HAS_SDADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) + +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 5 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH4_HANDLER Vector12C +#define STM32_DMA2_CH5_HANDLER Vector130 +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH4_NUMBER 59 +#define STM32_DMA2_CH5_NUMBER 60 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 34 +#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ + RCC_AHBENR_GPIOBEN | \ + RCC_AHBENR_GPIOCEN | \ + RCC_AHBENR_GPIODEN | \ + RCC_AHBENR_GPIOEEN | \ + RCC_AHBENR_GPIOFEN | \ + RCC_AHBENR_GPIOGEN | \ + RCC_AHBENR_GPIOHEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) + +#define STM32_HAS_I2C4 FALSE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_HAS_INTERRUPTS FALSE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE +#define STM32_SPI2_I2S_FULLDUPLEX TRUE +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE +#define STM32_SPI3_I2S_FULLDUPLEX TRUE +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) + +#define STM32_HAS_SPI4 TRUE +#define STM32_SPI4_SUPPORTS_I2S FALSE +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) + +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 6 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM8 TRUE +#define STM32_TIM8_IS_32BITS FALSE +#define STM32_TIM8_CHANNELS 6 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 1 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 1 + +#define STM32_HAS_TIM20 TRUE +#define STM32_TIM20_IS_32BITS FALSE +#define STM32_TIM20_CHANNELS 4 + +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#define STM32_HAS_USART2 TRUE +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) + +#define STM32_HAS_USART3 TRUE +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#define STM32_HAS_UART4 TRUE +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) + +#define STM32_HAS_UART5 TRUE + +#define STM32_HAS_USART6 FALSE +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE +#define STM32_HAS_LPUART1 FALSE + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_USB_ACCESS_SCHEME_2x16 TRUE +#define STM32_USB_PMA_SIZE 768 +#define STM32_USB_HAS_BCDR FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE TRUE +#endif /* defined(STM32F303xE) */ + /*===========================================================================*/ /* STM32F303x8. */ /*===========================================================================*/ @@ -420,11 +670,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM8 FALSE @@ -622,11 +872,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM3 FALSE #define STM32_HAS_TIM4 FALSE @@ -827,11 +1077,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM3 FALSE #define STM32_HAS_TIM4 FALSE @@ -863,8 +1113,238 @@ #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) -#define STM32_HAS_UART4 FALSE -#define STM32_HAS_UART5 FALSE +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE +#define STM32_HAS_LPUART1 FALSE + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_USB_ACCESS_SCHEME_2x16 TRUE +#define STM32_USB_PMA_SIZE 768 +#define STM32_USB_HAS_BCDR FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE TRUE +#endif /* defined(STM32F302x8) */ + +/*===========================================================================*/ +/* STM32F302xC. */ +/*===========================================================================*/ +#if defined(STM32F302xC) +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +#define STM32_HAS_SDADC1 FALSE +#define STM32_HAS_SDADC2 FALSE +#define STM32_HAS_SDADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +#define STM32_HAS_DAC1_CH2 FALSE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 5 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH4_HANDLER Vector12C +#define STM32_DMA2_CH5_HANDLER Vector130 +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH4_NUMBER 59 +#define STM32_DMA2_CH5_NUMBER 60 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 34 +#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ + RCC_AHBENR_GPIOBEN | \ + RCC_AHBENR_GPIOCEN | \ + RCC_AHBENR_GPIODEN | \ + RCC_AHBENR_GPIOEEN | \ + RCC_AHBENR_GPIOFEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#define STM32_HAS_I2C3 FALSE +#define STM32_HAS_I2C4 FALSE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_HAS_INTERRUPTS FALSE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE +#define STM32_SPI2_I2S_FULLDUPLEX TRUE +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE +#define STM32_SPI3_I2S_FULLDUPLEX TRUE +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) + +#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 6 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 1 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 1 + +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM7 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#define STM32_HAS_USART2 TRUE +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) + +#define STM32_HAS_USART3 TRUE +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#define STM32_HAS_UART4 TRUE +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) + +#define STM32_HAS_UART5 TRUE + #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE @@ -872,8 +1352,8 @@ /* USB attributes.*/ #define STM32_HAS_USB TRUE -#define STM32_USB_ACCESS_SCHEME_2x16 TRUE -#define STM32_USB_PMA_SIZE 768 +#define STM32_USB_ACCESS_SCHEME_2x16 FALSE +#define STM32_USB_PMA_SIZE 512 #define STM32_USB_HAS_BCDR FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -894,12 +1374,12 @@ /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE -#endif /* defined(STM32F302x8) */ +#endif /* defined(STM32F302xC) */ /*===========================================================================*/ -/* STM32F302xC. */ +/* STM32F302xE. */ /*===========================================================================*/ -#if defined(STM32F302xC) +#if defined(STM32F302xE) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE @@ -970,8 +1450,8 @@ #define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE TRUE #define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH TRUE #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE @@ -980,7 +1460,9 @@ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOEEN | \ - RCC_AHBENR_GPIOFEN) + RCC_AHBENR_GPIOFEN | \ + RCC_AHBENR_GPIOGEN | \ + RCC_AHBENR_GPIOHEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE @@ -991,7 +1473,10 @@ #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) -#define STM32_HAS_I2C3 FALSE +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) + #define STM32_HAS_I2C4 FALSE /* RTC attributes.*/ @@ -1022,7 +1507,11 @@ #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) -#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI4 TRUE +#define STM32_SPI4_SUPPORTS_I2S FALSE +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) + #define STM32_HAS_SPI5 FALSE #define STM32_HAS_SPI6 FALSE @@ -1055,11 +1544,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM7 FALSE @@ -1102,8 +1591,8 @@ /* USB attributes.*/ #define STM32_HAS_USB TRUE -#define STM32_USB_ACCESS_SCHEME_2x16 FALSE -#define STM32_USB_PMA_SIZE 512 +#define STM32_USB_ACCESS_SCHEME_2x16 TRUE +#define STM32_USB_PMA_SIZE 768 #define STM32_USB_HAS_BCDR FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -1124,7 +1613,7 @@ /* CRC attributes.*/ #define STM32_HAS_CRC TRUE #define STM32_CRC_PROGRAMMABLE TRUE -#endif /* defined(STM32F302xC) */ +#endif /* defined(STM32F302xE) */ /*===========================================================================*/ /* STM32F318x8. */ @@ -1264,11 +1753,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM3 FALSE #define STM32_HAS_TIM4 FALSE @@ -1469,11 +1958,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE @@ -1536,7 +2025,7 @@ /*===========================================================================*/ /* STM32F358xC. */ /*===========================================================================*/ -#if defined(STM32F358xC) || defined(__DOXYGEN__) +#if defined(STM32F358xC) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE @@ -1694,11 +2183,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM7 FALSE @@ -1768,7 +2257,7 @@ /*===========================================================================*/ /* STM32F334x8. */ /*===========================================================================*/ -#if defined(STM32F334x8) || defined(__DOXYGEN__) +#if defined(STM32F334x8) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_HAS_ADC2 TRUE @@ -1904,11 +2393,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE @@ -1968,6 +2457,254 @@ #define STM32_CRC_PROGRAMMABLE TRUE #endif /* defined(STM32F334x8) */ +/*===========================================================================*/ +/* STM32F398xx. */ +/*===========================================================================*/ +#if defined(STM32F398xx) +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 TRUE +#define STM32_HAS_ADC4 TRUE + +#define STM32_HAS_SDADC1 FALSE +#define STM32_HAS_SDADC2 FALSE +#define STM32_HAS_SDADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) + +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA FALSE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 5 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH4_HANDLER Vector12C +#define STM32_DMA2_CH5_HANDLER Vector130 +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH4_NUMBER 59 +#define STM32_DMA2_CH5_NUMBER 60 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 34 +#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ + RCC_AHBENR_GPIOBEN | \ + RCC_AHBENR_GPIOCEN | \ + RCC_AHBENR_GPIODEN | \ + RCC_AHBENR_GPIOEEN | \ + RCC_AHBENR_GPIOFEN | \ + RCC_AHBENR_GPIOGEN | \ + RCC_AHBENR_GPIOHEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) + +#define STM32_HAS_I2C4 FALSE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_HAS_INTERRUPTS FALSE + +/* SDIO attributes.*/ +#define STM32_HAS_SDIO FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE +#define STM32_SPI2_I2S_FULLDUPLEX TRUE +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE +#define STM32_SPI3_I2S_FULLDUPLEX TRUE +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) + +#define STM32_HAS_SPI4 TRUE +#define STM32_SPI4_SUPPORTS_I2S FALSE +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) + +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 6 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM8 TRUE +#define STM32_TIM8_IS_32BITS FALSE +#define STM32_TIM8_CHANNELS 6 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 1 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 1 + +#define STM32_HAS_TIM20 TRUE +#define STM32_TIM20_IS_32BITS FALSE +#define STM32_TIM20_CHANNELS 4 + +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +#define STM32_HAS_USART2 TRUE +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) + +#define STM32_HAS_USART3 TRUE +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) + +#define STM32_HAS_UART4 TRUE +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) + +#define STM32_HAS_UART5 TRUE + +#define STM32_HAS_USART6 FALSE +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE +#define STM32_HAS_LPUART1 FALSE + +/* USB attributes.*/ +#define STM32_HAS_USB FALSE +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC TRUE +#define STM32_FSMC_IS_FMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE TRUE +#endif /* defined(STM32F398xx) */ + /** @} */ #endif /* _STM32_REGISTRY_H_ */ diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index 2afd17b9a..cd5b0ccc5 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -746,6 +746,7 @@ /* FSMC attributes.*/ #define STM32_HAS_FSMC TRUE +#define STM32_FSMC_IS_FMC FALSE #define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\ STM32_DMA_STREAM_ID_MSK(2, 1) |\ STM32_DMA_STREAM_ID_MSK(2, 2) |\ diff --git a/readme.txt b/readme.txt index 3995ed119..89b6ff12e 100644 --- a/readme.txt +++ b/readme.txt @@ -85,6 +85,7 @@ - HAL: Added "lines" handling to PAL driver, lines are identifiers of both ports and pins encoded in a single value. Added a set of macros operating on lines. +- HAL: Merged the latest STM32F3xx CMSIS headers. - HAL: Merged the latest STM32F2xx CMSIS headers and fixed the support broken in 3.0.x. - RT: Added new function chVTGetTimersStateI() returning the state of the -- cgit v1.2.3