diff options
Diffstat (limited to 'os/hal/ports/TIVA')
51 files changed, 6276 insertions, 7072 deletions
diff --git a/os/hal/ports/TIVA/LLD/ADC/driver.mk b/os/hal/ports/TIVA/LLD/ADC/driver.mk new file mode 100644 index 0000000..5a1c80b --- /dev/null +++ b/os/hal/ports/TIVA/LLD/ADC/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/ADC diff --git a/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.c b/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.c new file mode 100644 index 0000000..6c1be30 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.c @@ -0,0 +1,351 @@ +/* + Copyright (C) 2014..2017 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_adc_lld.c + * @brief PLATFORM ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC0 driver identifier.*/ +#if TIVA_ADC_USE_ADC0 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/** @brief ADC1 driver identifier.*/ +#if TIVA_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Common IRQ handler. + * + * @param[in] adcp pointer to the @p ADCDriver object + */ +static void serve_interrupt(ADCDriver *adcp) +{ + tiva_udma_table_entry_t *pri = &udmaControlTable.primary[adcp->dmanr]; + tiva_udma_table_entry_t *alt = &udmaControlTable.alternate[adcp->dmanr]; + + if ((pri->chctl & UDMA_CHCTL_XFERMODE_M) == UDMA_CHCTL_XFERMODE_STOP) { + /* Primary is used only for circular transfers */ + if (adcp->grpp->circular) { + if (adcp->depth > 1) { + _adc_isr_half_code(adcp); + } + + /* Reconfigure DMA for new lower half transfer */ + pri->chctl = adcp->prictl; + } + } + + if ((alt->chctl & UDMA_CHCTL_XFERMODE_M) == UDMA_CHCTL_XFERMODE_STOP) { + /* Alternate is used for both linear and circular transfers */ + _adc_isr_full_code(adcp); + + if (adcp->grpp->circular) { + /* Reconfigure DMA for new upper half transfer */ + alt->chctl = adcp->altctl; + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_ADC_USE_ADC0 +/** + * @brief ADC0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_ADC0_SEQ0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + serve_interrupt(&ADCD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_ADC_USE_ADC1 +/** + * @brief ADC1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_ADC1_SEQ0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + serve_interrupt(&ADCD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) +{ +#if TIVA_ADC_USE_ADC0 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC0_BASE; + ADCD1.dmanr = TIVA_ADC_ADC0_SS0_UDMA_CHANNEL; + ADCD1.chnmap = TIVA_ADC_ADC0_SS0_UDMA_MAPPING; +#endif + +#if TIVA_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD2); + ADCD2.adc = ADC1_BASE; + ADCD2.dmanr = TIVA_ADC_ADC1_SS0_UDMA_CHANNEL; + ADCD2.chnmap = TIVA_ADC_ADC1_SS0_UDMA_MAPPING; +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) +{ + if (adcp->state == ADC_STOP) { + /* Enables the peripheral.*/ +#if TIVA_ADC_USE_ADC0 + if (&ADCD1 == adcp) { + bool b; + b = udmaChannelAllocate(adcp->dmanr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCADC) |= (1 << 0); + + while (!(HWREG(SYSCTL_PRADC) & (1 << 0))) + ; + + /* Only sequencer 0 is supported */ + nvicEnableVector(TIVA_ADC0_SEQ0_NUMBER, TIVA_ADC0_SEQ0_PRIORITY); + } +#endif + +#if TIVA_ADC_USE_ADC1 + if (&ADCD2 == adcp) { + bool b; + b = udmaChannelAllocate(adcp->dmanr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCADC) |= (1 << 1); + + while (!(HWREG(SYSCTL_PRADC) & (1 << 1))) + ; + + /* Only sequencer 0 is supported */ + nvicEnableVector(TIVA_ADC1_SEQ0_NUMBER, TIVA_ADC1_SEQ0_PRIORITY); + } +#endif + + HWREG(UDMA_CHMAP0 + (adcp->dmanr / 8) * 4) |= (adcp->chnmap << (adcp->dmanr % 8)); + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) +{ + if (adcp->state == ADC_READY) { + /* Resets the peripheral.*/ + + udmaChannelRelease(adcp->dmanr); + + /* Disables the peripheral.*/ +#if TIVA_ADC_USE_ADC0 + if (&ADCD1 == adcp) { + nvicDisableVector(TIVA_ADC0_SEQ0_NUMBER); + } +#endif + +#if TIVA_ADC_USE_ADC1 + if (&ADCD2 == adcp) { + nvicDisableVector(TIVA_ADC1_SEQ0_NUMBER); + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) +{ + uint32_t adc = adcp->adc; + tiva_udma_table_entry_t *primary = &udmaControlTable.primary[adcp->dmanr]; + tiva_udma_table_entry_t *alternate = &udmaControlTable.alternate[adcp->dmanr]; + + /* Disable sample sequencer 0 */ + HWREG(adc + ADC_O_ACTSS) &= (1 << 0); + + /* Configure the sample sequencer 0 trigger */ + HWREG(adc + ADC_O_EMUX) = adcp->grpp->emux & 0xff; + + /* If pwm is used as trigger, select in which block the pwm generator is + located */ + if (adcp->grpp->emux >= 6 && adcp->grpp->emux <= 9) { + HWREG(adc + ADC_O_TSSEL) = 0; + } + + /* For each sample in the sample sequencer, select the input source */ + HWREG(adc + ADC_O_SSMUX0) = adcp->grpp->ssmux; + + /* Configure the sample control bits */ + HWREG(adc + ADC_O_SSCTL0) = adcp->grpp->ssctl | 0x44444444; /* Enforce IEn bits */ + + /* Alternate source endpoint is the same for all transfers */ + alternate->srcendp = (void *)(adcp->adc + ADC_O_SSFIFO0); + + /* Configure DMA */ + if ((adcp->grpp->circular) && (adcp->depth > 1)) { + /* Configure DMA in ping-pong mode. + Ping (1st half) is configured in the primary control structure. + Pong (2nd half) is configured in the alternate control structure. */ + + uint32_t ctl; + + /* configure the primary source endpoint */ + primary->srcendp = (void *)(adcp->adc + ADC_O_SSFIFO0); + + /* sample buffer is split in half, the upper half is used here */ + primary->dstendp = (void *)(adcp->samples + + (adcp->grpp->num_channels * adcp->depth / 2) - 1); + /* the lower half is used here */ + alternate->dstendp = (void *)(adcp->samples + + (adcp->grpp->num_channels * adcp->depth) - 1); + + ctl = UDMA_CHCTL_DSTSIZE_32 | UDMA_CHCTL_DSTINC_32 | + UDMA_CHCTL_SRCSIZE_32 | UDMA_CHCTL_SRCINC_NONE | + UDMA_CHCTL_ARBSIZE_1 | + UDMA_CHCTL_XFERSIZE(adcp->grpp->num_channels * adcp->depth / 2) | + UDMA_CHCTL_XFERMODE_PINGPONG; + + adcp->prictl = ctl; + adcp->altctl = ctl; + + dmaChannelPrimary(adcp->dmanr); + } + else { + /* Configure the DMA in basic mode. + This is used for both circular buffers with a depth of 1 and linear + buffers.*/ + alternate->dstendp = (void *)(adcp->samples + + (adcp->grpp->num_channels * adcp->depth) - 1); + adcp->prictl = UDMA_CHCTL_XFERMODE_STOP; + adcp->altctl = UDMA_CHCTL_DSTSIZE_32 | UDMA_CHCTL_DSTINC_32 | + UDMA_CHCTL_SRCSIZE_32 | UDMA_CHCTL_SRCINC_NONE | + UDMA_CHCTL_ARBSIZE_1 | + UDMA_CHCTL_XFERSIZE(adcp->grpp->num_channels * adcp->depth) | + UDMA_CHCTL_XFERMODE_BASIC; + + dmaChannelAlternate(adcp->dmanr); + } + + /* Configure primary and alternate channel control fields */ + primary->chctl = adcp->prictl; + alternate->chctl = adcp->altctl; + + /* Configure DMA channel */ + dmaChannelBurstOnly(adcp->dmanr); + dmaChannelPriorityDefault(adcp->dmanr); + dmaChannelEnableRequest(adcp->dmanr); + + /* Enable DMA channel */ + dmaChannelEnable(adcp->dmanr); + + /* Enable the sample sequencer */ + HWREG(adc + ADC_O_ACTSS) |= (1 << 0); + + /* Enable DMA on the sample sequencer, is this for 129x only?*/ + //HWREG(adc + ADC_O_ACTSS) |= (1 << 8); + + /* Start conversion if configured for CPU trigger */ + if ((adcp->grpp->emux & 0xff) == 0) { + HWREG(adc + ADC_O_PSSI) = ADC_PSSI_SS0; + } +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) +{ + uint32_t adc = adcp->adc; + + /* Stop ongoing DMA transfer */ + dmaChannelDisable(adcp->dmanr); + + /* Stop ongoing ADC conversion by disabling the active sample sequencer */ + HWREG(adc + ADC_O_ACTSS) &= ~(1 << 0); +} + +#endif /* HAL_USE_ADC == TRUE */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.h b/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.h new file mode 100644 index 0000000..81916b8 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/ADC/hal_adc_lld.h @@ -0,0 +1,230 @@ +/* + Copyright (C) 2014..2017 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_adc_lld.h + * @brief PLATFORM ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef HAL_ADC_LLD_H +#define HAL_ADC_LLD_H + +#if (HAL_USE_ADC == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name PLATFORM configuration options + * @{ + */ +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p FALSE. + */ +#if !defined(PLATFORM_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define PLATFORM_ADC_USE_ADC1 FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(TIVA_UDMA_REQUIRED) +#define TIVA_UDMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint32_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Possible ADC failure causes. + * @note Error codes are architecture dependent and should not relied + * upon. + */ +typedef enum { + ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */ + ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */ + ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */ +} adcerror_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief ADC error callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] err ADC error code + */ +typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * PLATFORM ADC cell registers interface, please refer to the PLATFORM + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /** + * @brief Error callback or @p NULL. + */ + adcerrorcallback_t error_cb; + /* End of the mandatory fields.*/ + uint32_t emux; + uint32_t ssmux; + uint32_t ssctl; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if (ADC_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif +#if (ADC_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + mutex_t mutex; +#endif +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADC registers block. + */ + uint32_t adc; + uint8_t dmanr; + uint8_t chnmap; + uint32_t prictl; + uint32_t altctl; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if TIVA_ADC_USE_ADC0 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#if TIVA_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC == TRUE */ + +#endif /* HAL_ADC_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/GPIO/driver.mk b/os/hal/ports/TIVA/LLD/GPIO/driver.mk new file mode 100644 index 0000000..486fe73 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPIO/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c new file mode 100644 index 0000000..7a222e4 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c @@ -0,0 +1,1135 @@ +/* + Copyright (C) 2014..2017 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIO/hal_pal_lld.c + * @brief TM4C123x/TM4C129x PAL subsystem low level driver. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) +#define GPIOA_BIT (1 << 0) +#else +#define GPIOA_BIT 0 +#endif + +#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) +#define GPIOB_BIT (1 << 1) +#else +#define GPIOB_BIT 0 +#endif + +#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) +#define GPIOC_BIT (1 << 2) +#else +#define GPIOC_BIT 0 +#endif + +#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) +#define GPIOD_BIT (1 << 3) +#else +#define GPIOD_BIT 0 +#endif + +#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) +#define GPIOE_BIT (1 << 4) +#else +#define GPIOE_BIT 0 +#endif + +#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) +#define GPIOF_BIT (1 << 5) +#else +#define GPIOF_BIT 0 +#endif + +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) +#define GPIOG_BIT (1 << 6) +#else +#define GPIOG_BIT 0 +#endif + +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) +#define GPIOH_BIT (1 << 7) +#else +#define GPIOH_BIT 0 +#endif + +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) +#define GPIOJ_BIT (1 << 8) +#else +#define GPIOJ_BIT 0 +#endif + +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) +#define GPIOK_BIT (1 << 9) +#else +#define GPIOK_BIT 0 +#endif + +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) +#define GPIOL_BIT (1 << 10) +#else +#define GPIOL_BIT 0 +#endif + +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) +#define GPIOM_BIT (1 << 11) +#else +#define GPIOM_BIT 0 +#endif + +#if TIVA_HAS_GPION || defined(__DOXYGEN__) +#define GPION_BIT (1 << 12) +#else +#define GPION_BIT 0 +#endif + +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) +#define GPIOP_BIT (1 << 13) +#else +#define GPIOP_BIT 0 +#endif + +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) +#define GPIOQ_BIT (1 << 14) +#else +#define GPIOQ_BIT 0 +#endif + +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) +#define GPIOR_BIT (1 << 15) +#else +#define GPIOR_BIT 0 +#endif + +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) +#define GPIOS_BIT (1 << 16) +#else +#define GPIOS_BIT 0 +#endif + +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) +#define GPIOT_BIT (1 << 17) +#else +#define GPIOT_BIT 0 +#endif + +#define RCGCGPIO_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ + GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ + GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT | \ + GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT | \ + GPIOS_BIT | GPIOT_BIT) + +#define GPIOHBCTL_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ + GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ + GPIOJ_BIT) + +#define GPIOC_JTAG_MASK (0x0F) +#define GPIOD_NMI_MASK (0x80) +#define GPIOF_NMI_MASK (0x01) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Event records for all GPIO channels. + */ +palevent_t _pal_events[TIVA_GPIO_PINS]; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the port with the port configuration. + * + * @param[in] port the port identifier + * @param[in] config the port configuration + */ +static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config) +{ + HWREG(port + GPIO_O_DATA) = config->data; + HWREG(port + GPIO_O_DIR) = config->dir; + HWREG(port + GPIO_O_AFSEL) = config->afsel; + HWREG(port + GPIO_O_DR2R) = config->dr2r; + HWREG(port + GPIO_O_DR4R) = config->dr4r; + HWREG(port + GPIO_O_DR8R) = config->dr8r; + HWREG(port + GPIO_O_ODR) = config->odr; + HWREG(port + GPIO_O_PUR) = config->pur; + HWREG(port + GPIO_O_PDR) = config->pdr; + HWREG(port + GPIO_O_SLR) = config->slr; + HWREG(port + GPIO_O_DEN) = config->den; + HWREG(port + GPIO_O_AMSEL) = config->amsel; + HWREG(port + GPIO_O_PCTL) = config->pctl; +} + +/** + * @brief Unlocks the masked pins of the GPIO peripheral. + * @note This function is only useful for PORTC0-3, PORTD7 and PORTF0. + * + * @param[in] port the port identifier + * @param[in] mask the pin mask + */ +static void gpio_unlock(ioportid_t port, ioportmask_t mask) +{ + + HWREG(port + GPIO_O_LOCK) = GPIO_LOCK_KEY; + HWREG(port + GPIO_O_CR) = mask; +} + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT +/** + * @brief Enables GPIO IRQ sources. + */ +static void gpio_irq_enable(void) +{ +#if TIVA_HAS_GPIOA + nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_PAL_GPIOA_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOB + nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_PAL_GPIOB_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOC + nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_PAL_GPIOC_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOD + nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_PAL_GPIOD_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOE + nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_PAL_GPIOE_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOF + nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_PAL_GPIOF_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOG + nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_PAL_GPIOG_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOH + nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_PAL_GPIOH_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOJ + nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_PAL_GPIOJ_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOK + nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_PAL_GPIOK_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOL + nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_PAL_GPIOL_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOM + nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_PAL_GPIOM_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPION + nvicEnableVector(TIVA_GPION_NUMBER, TIVA_PAL_GPION_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOP + nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_PAL_GPIOP0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_PAL_GPIOP1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_PAL_GPIOP2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_PAL_GPIOP3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_PAL_GPIOP4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_PAL_GPIOP5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_PAL_GPIOP6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_PAL_GPIOP7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOQ + nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_PAL_GPIOQ0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_PAL_GPIOQ1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_PAL_GPIOQ2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_PAL_GPIOQ3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_PAL_GPIOQ4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_PAL_GPIOQ5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_PAL_GPIOQ6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_PAL_GPIOQ7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOR + nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_PAL_GPIOR_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOS + nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_PAL_GPIOS_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOT + nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_PAL_GPIOT_IRQ_PRIORITY); +#endif +} +#endif + +#define gpio_serve_irq(mask, pin, channel) { \ + \ + if ((mask) & (1U << (pin))) { \ + _pal_isr_code(channel); \ + } \ +} + +/** + * @brief Generic interrupt serving code for multiple pins per interrupt + * handler. + */ +#define ext_lld_serve_port_interrupt(gpio, start) \ + do { \ + uint32_t mis = HWREG(gpio + GPIO_O_MIS); \ + \ + HWREG(gpio + GPIO_O_ICR) = mis; \ + \ + gpio_serve_irq(mis, 0, start + 0); \ + gpio_serve_irq(mis, 1, start + 1); \ + gpio_serve_irq(mis, 2, start + 2); \ + gpio_serve_irq(mis, 3, start + 3); \ + gpio_serve_irq(mis, 4, start + 4); \ + gpio_serve_irq(mis, 5, start + 5); \ + gpio_serve_irq(mis, 6, start + 6); \ + gpio_serve_irq(mis, 7, start + 7); \ + } while (0); + +/** + * @brief Generic interrupt serving code for single pin per interrupt + * handler. + */ +#define ext_lld_serve_pin_interrupt(gpio, start, pin) \ + do { \ + HWREG(gpio + GPIO_O_ICR) = (1 << pin); \ + gpio_serve_irq((1 << pin), pin, start) \ + } while (0); + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) +/** + * @brief GPIOA interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOA, 0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) +/** + * @brief GPIOB interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOB, 8); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) +/** + * @brief GPIOC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOC, 16); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) +/** + * @brief GPIOD interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOD, 24); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) +/** + * @brief GPIOE interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOE, 32); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) +/** + * @brief GPIOF interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOF, 40); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) +/** + * @brief GPIOG interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOG, 48); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) +/** + * @brief GPIOH interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOH, 56); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) +/** + * @brief GPIOJ interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOJ, 64); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) +/** + * @brief GPIOK interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOK, 72); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) +/** + * @brief GPIOL interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOL, 80); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) +/** + * @brief GPIOM interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOM, 88); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPION || defined(__DOXYGEN__) +/** + * @brief GPION interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPION, 96); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) +/** + * @brief GPIOP0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 104, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 105, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 106, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 107, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 108, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 109, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 110, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 111, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) +/** + * @brief GPIOQ0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 112, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 113, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 114, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 115, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 116, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 117, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 118, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 119, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) +/** + * @brief GPIOR interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOR, 120); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) +/** + * @brief GPIOS interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOS, 128); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) +/** + * @brief GPIOT interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOT, 132); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Tiva I/O ports configuration. + * @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled. + * + * @param[in] config the Tiva ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) +{ +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) + unsigned i; + + for (i = 0; i < TIVA_GPIO_PINS; i++) { + _pal_init_event(i); + } +#endif + + /* + * Enables all GPIO clocks. + */ + HWREG(SYSCTL_RCGCGPIO) = RCGCGPIO_MASK; +#if defined(TM4C123x) + HWREG(SYSCTL_GPIOHBCTL) = GPIOHBCTL_MASK; +#endif + + /* Wait until all GPIO modules are ready */ + while (!((HWREG(SYSCTL_PRGPIO) & RCGCGPIO_MASK) == RCGCGPIO_MASK)) + ; + +#if TIVA_HAS_GPIOA + gpio_init(GPIOA, &config->PAData); +#endif +#if TIVA_HAS_GPIOB + gpio_init(GPIOB, &config->PBData); +#endif +#if TIVA_HAS_GPIOC + /* Unlock JTAG pins.*/ + gpio_unlock(GPIOC, GPIOC_JTAG_MASK); + gpio_init(GPIOC, &config->PCData); +#endif +#if TIVA_HAS_GPIOD + /* Unlock NMI pin.*/ + gpio_unlock(GPIOD, GPIOD_NMI_MASK); + gpio_init(GPIOD, &config->PDData); +#endif +#if TIVA_HAS_GPIOE + gpio_init(GPIOE, &config->PEData); +#endif +#if TIVA_HAS_GPIOF + /* Unlock NMI pin.*/ + gpio_unlock(GPIOF, GPIOF_NMI_MASK); + gpio_init(GPIOF, &config->PFData); +#endif +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) + gpio_init(GPIOG, &config->PGData); +#endif +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) + gpio_init(GPIOH, &config->PHData); +#endif +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_init(GPIOJ, &config->PJData); +#endif +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) + gpio_init(GPIOK, &config->PKData); +#endif +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) + gpio_init(GPIOL, &config->PLData); +#endif +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) + gpio_init(GPIOM, &config->PMData); +#endif +#if TIVA_HAS_GPION || defined(__DOXYGEN__) + gpio_init(GPION, &config->PNData); +#endif +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) + gpio_init(GPIOP, &config->PPData); +#endif +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) + gpio_init(GPIOQ, &config->PQData); +#endif +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) + gpio_init(GPIOR, &config->PRData); +#endif +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) + gpio_init(GPIOS, &config->PSData); +#endif +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) + gpio_init(GPIOT, &config->PTData); +#endif +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + gpio_irq_enable(); +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) +{ + uint32_t dir = (mode & PAL_TIVA_DIR_MASK) >> 0; + uint32_t afsel = (mode & PAL_TIVA_AFSEL_MASK) >> 1; + uint32_t dr2r = (mode & PAL_TIVA_DR2R_MASK) >> 2; + uint32_t dr4r = (mode & PAL_TIVA_DR4R_MASK) >> 3; + uint32_t dr8r = (mode & PAL_TIVA_DR8R_MASK) >> 4; + uint32_t odr = (mode & PAL_TIVA_ODR_MASK) >> 5; + uint32_t pur = (mode & PAL_TIVA_PUR_MASK) >> 6; + uint32_t pdr = (mode & PAL_TIVA_PDR_MASK) >> 7; + uint32_t slr = (mode & PAL_TIVA_SLR_MASK) >> 8; + uint32_t den = (mode & PAL_TIVA_DEN_MASK) >> 9; + uint32_t amsel = (mode & PAL_TIVA_AMSEL_MASK) >> 10; + uint32_t pctl = (mode & PAL_TIVA_PCTL_MASK) >> 11; + uint32_t bit = 0; + + while(TRUE) { + uint32_t pctl_mask = (7 << (4 * bit)); + uint32_t bit_mask = (1 << bit); + + if ((mask & 1) != 0) { + HWREG(port + GPIO_O_DIR) = (HWREG(port + GPIO_O_DIR) & ~bit_mask) | dir; + HWREG(port + GPIO_O_AFSEL) = (HWREG(port + GPIO_O_AFSEL) & ~bit_mask) | afsel; + HWREG(port + GPIO_O_DR2R) = (HWREG(port + GPIO_O_DR2R) & ~bit_mask) | dr2r; + HWREG(port + GPIO_O_DR4R) = (HWREG(port + GPIO_O_DR4R) & ~bit_mask) | dr4r; + HWREG(port + GPIO_O_DR8R) = (HWREG(port + GPIO_O_DR8R) & ~bit_mask) | dr8r; + HWREG(port + GPIO_O_ODR) = (HWREG(port + GPIO_O_ODR) & ~bit_mask) | odr; + HWREG(port + GPIO_O_PUR) = (HWREG(port + GPIO_O_PUR) & ~bit_mask) | pur; + HWREG(port + GPIO_O_PDR) = (HWREG(port + GPIO_O_PDR) & ~bit_mask) | pdr; + HWREG(port + GPIO_O_SLR) = (HWREG(port + GPIO_O_SLR) & ~bit_mask) | slr; + HWREG(port + GPIO_O_DEN) = (HWREG(port + GPIO_O_DEN) & ~bit_mask) | den; + HWREG(port + GPIO_O_AMSEL) = (HWREG(port + GPIO_O_AMSEL) & ~bit_mask) | amsel; + HWREG(port + GPIO_O_PCTL) = (HWREG(port + GPIO_O_PCTL) & ~pctl_mask) | pctl; + } + + mask >>= 1; + if (!mask) { + return; + } + + dir <<= 1; + afsel <<= 1; + dr2r <<= 1; + dr4r <<= 1; + dr8r <<= 1; + odr <<= 1; + pur <<= 1; + pdr <<= 1; + slr <<= 1; + den <<= 1; + amsel <<= 1; + pctl <<= 4; + + bit++; + } +} + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode) +{ + //uint8_t portidx; + uint32_t padmask; + + //portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU; + padmask = (1 << pad); + + /* Disable interrupt before changing edge configuration.*/ + HWREG(port + GPIO_O_IM) &= ~padmask; + + /* Configure pin to be edge-sensitive.*/ + HWREG(port + GPIO_O_IS) &= ~(1 << pad); + + /* Configure edges */ + switch(mode & PAL_EVENT_MODE_EDGES_MASK) { + case PAL_EVENT_MODE_BOTH_EDGES: + HWREG(port + GPIO_O_IBE) |= padmask; + break; + case PAL_EVENT_MODE_RISING_EDGE: + HWREG(port + GPIO_O_IBE) &= ~padmask; + HWREG(port + GPIO_O_IEV) &= ~padmask; + break; + case PAL_EVENT_MODE_FALLING_EDGE: + HWREG(port + GPIO_O_IBE) &= ~padmask; + HWREG(port + GPIO_O_IEV) |= padmask; + break; + default: + /* Interrupt is already disabled */ + break; + } + + if (mode & PAL_EVENT_MODE_EDGES_MASK) { + /* Enable interrupt for this pad */ + HWREG(port + GPIO_O_IM) |= padmask; + } +} + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) +{ + uint8_t portidx; + uint8_t eventidx; + + portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU; + + eventidx = portidx * 8 + pad; + + HWREG(port + GPIO_O_IM) &= ~(1 << pad); + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + /* Callback cleared and/or thread reset.*/ + _pal_clear_event(eventidx); +#endif +} + +/** + * @brief Disables GPIO IRQ sources. + */ +void pal_lld_disable_irqs(void) +{ +#if TIVA_HAS_GPIOA + nvicDisableVector(TIVA_GPIOA_NUMBER); +#endif +#if TIVA_HAS_GPIOB + nvicDisableVector(TIVA_GPIOB_NUMBER); +#endif +#if TIVA_HAS_GPIOC + nvicDisableVector(TIVA_GPIOC_NUMBER); +#endif +#if TIVA_HAS_GPIOD + nvicDisableVector(TIVA_GPIOD_NUMBER); +#endif +#if TIVA_HAS_GPIOE + nvicDisableVector(TIVA_GPIOE_NUMBER); +#endif +#if TIVA_HAS_GPIOF + nvicDisableVector(TIVA_GPIOF_NUMBER); +#endif +#if TIVA_HAS_GPIOG + nvicDisableVector(TIVA_GPIOG_NUMBER); +#endif +#if TIVA_HAS_GPIOH + nvicDisableVector(TIVA_GPIOH_NUMBER); +#endif +#if TIVA_HAS_GPIOJ + nvicDisableVector(TIVA_GPIOJ_NUMBER); +#endif +#if TIVA_HAS_GPIOK + nvicDisableVector(TIVA_GPIOK_NUMBER); +#endif +#if TIVA_HAS_GPIOL + nvicDisableVector(TIVA_GPIOL_NUMBER); +#endif +#if TIVA_HAS_GPIOM + nvicDisableVector(TIVA_GPIOM_NUMBER); +#endif +#if TIVA_HAS_GPION + nvicDisableVector(TIVA_GPION_NUMBER); +#endif +#if TIVA_HAS_GPIOP + nvicDisableVector(TIVA_GPIOP0_NUMBER); + nvicDisableVector(TIVA_GPIOP1_NUMBER); + nvicDisableVector(TIVA_GPIOP2_NUMBER); + nvicDisableVector(TIVA_GPIOP3_NUMBER); + nvicDisableVector(TIVA_GPIOP4_NUMBER); + nvicDisableVector(TIVA_GPIOP5_NUMBER); + nvicDisableVector(TIVA_GPIOP6_NUMBER); + nvicDisableVector(TIVA_GPIOP7_NUMBER); +#endif +#if TIVA_HAS_GPIOQ + nvicDisableVector(TIVA_GPIOQ0_NUMBER); + nvicDisableVector(TIVA_GPIOQ1_NUMBER); + nvicDisableVector(TIVA_GPIOQ2_NUMBER); + nvicDisableVector(TIVA_GPIOQ3_NUMBER); + nvicDisableVector(TIVA_GPIOQ4_NUMBER); + nvicDisableVector(TIVA_GPIOQ5_NUMBER); + nvicDisableVector(TIVA_GPIOQ6_NUMBER); + nvicDisableVector(TIVA_GPIOQ7_NUMBER); +#endif +#if TIVA_HAS_GPIOR + nvicDisableVector(TIVA_GPIOR_NUMBER); +#endif +#if TIVA_HAS_GPIOS + nvicDisableVector(TIVA_GPIOS_NUMBER); +#endif +#if TIVA_HAS_GPIOT + nvicDisableVector(TIVA_GPIOT_NUMBER); +#endif +} +#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */ + +#endif /* HAL_USE_PAL */ + +/** + * @} + */ diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h new file mode 100644 index 0000000..e884a92 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h @@ -0,0 +1,1141 @@ +/* + Copyright (C) 2014..2017 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIO/hal_pal_lld.h + * @brief TM4C123x/TM4C129x PAL subsystem low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name TIVA-specific I/O mode flags + * @{ + */ +#define PAL_TIVA_DIR_MASK (1 << 0) +#define PAL_TIVA_DIR_INPUT (0 << 0) +#define PAL_TIVA_DIR_OUTPUT (1 << 0) + +#define PAL_TIVA_AFSEL_MASK (1 << 1) +#define PAL_TIVA_AFSEL_GPIO (0 << 1) +#define PAL_TIVA_AFSEL_ALTERNATE (1 << 1) + +#define PAL_TIVA_DR2R_MASK (1 << 2) +#define PAL_TIVA_DR2R_DISABLE (0 << 2) +#define PAL_TIVA_DR2R_ENABLE (1 << 2) + +#define PAL_TIVA_DR4R_MASK (1 << 3) +#define PAL_TIVA_DR4R_DISABLE (0 << 3) +#define PAL_TIVA_DR4R_ENABLE (1 << 3) + +#define PAL_TIVA_DR8R_MASK (1 << 4) +#define PAL_TIVA_DR8R_DISABLE (0 << 4) +#define PAL_TIVA_DR8R_ENABLE (1 << 4) + +#define PAL_TIVA_ODR_MASK (1 << 5) +#define PAL_TIVA_ODR_PUSHPULL (0 << 5) +#define PAL_TIVA_ODR_OPENDRAIN (1 << 5) + +#define PAL_TIVA_PUR_MASK (1 << 6) +#define PAL_TIVA_PUR_DISABLE (0 << 6) +#define PAL_TIVA_PUR_ENABLE (1 << 6) + +#define PAL_TIVA_PDR_MASK (1 << 7) +#define PAL_TIVA_PDR_DISABLE (0 << 7) +#define PAL_TIVA_PDR_ENABLE (1 << 7) + +#define PAL_TIVA_SLR_MASK (1 << 8) +#define PAL_TIVA_SLR_DISABLE (0 << 8) +#define PAL_TIVA_SLR_ENABLE (1 << 8) + +#define PAL_TIVA_DEN_MASK (1 << 9) +#define PAL_TIVA_DEN_DISABLE (0 << 9) +#define PAL_TIVA_DEN_ENABLE (1 << 9) + +#define PAL_TIVA_AMSEL_MASK (1 << 10) +#define PAL_TIVA_AMSEL_DISABLE (0 << 10) +#define PAL_TIVA_AMSEL_ENABLE (1 << 10) + +#define PAL_TIVA_PCTL_MASK (7 << 11) +#define PAL_TIVA_PCTL(n) ((n) << 11) + +/** + * @brief Alternate function. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALTERNATE(n) (PAL_TIVA_AFSEL_ALTERNATE | \ + PAL_TIVA_PCTL(n)) +/** @} */ + +/** + * @name Standard I/O mode flags + * @{ + */ +/** + * @brief This mode is implemented as input. + */ +#define PAL_MODE_RESET PAL_MODE_INPUT + +/** + * @brief This mode is implemented as input with pull-up. + */ +#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT (PAL_TIVA_DEN_ENABLE | \ + PAL_TIVA_DIR_INPUT) + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_TIVA_DIR_INPUT | \ + PAL_TIVA_PUR_ENABLE | \ + PAL_TIVA_DEN_ENABLE) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_TIVA_DIR_INPUT | \ + PAL_TIVA_PDR_ENABLE | \ + PAL_TIVA_DEN_ENABLE) + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG (PAL_TIVA_DEN_DISABLE | \ + PAL_TIVA_AMSEL_ENABLE) + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_TIVA_DIR_OUTPUT | \ + PAL_TIVA_DR2R_ENABLE | \ + PAL_TIVA_ODR_PUSHPULL | \ + PAL_TIVA_DEN_ENABLE) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_TIVA_DIR_OUTPUT | \ + PAL_TIVA_DR2R_ENABLE | \ + PAL_TIVA_ODR_OPENDRAIN | \ + PAL_TIVA_DEN_ENABLE) +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @name Port related definitions + * @{ + */ +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) +/** @} */ + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + * @note In this driver the pad number is encoded in the lower 4 bits of + * the GPIO address which are guaranteed to be zero. + */ +#define PAL_LINE(port, pad) \ + ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) \ + ((ioportid_t)(((uint32_t)(line)) & 0xFFFFFFF0U)) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) \ + ((uint32_t)((uint32_t)(line) & 0x0000000FU)) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/** + * @brief GPIO port setup info. + */ +typedef struct +{ + /** @brief Initial value for DATA register.*/ + uint32_t data; + /** @brief Initial value for DIR register.*/ + uint32_t dir; + /** @brief Initial value for AFSEL register.*/ + uint32_t afsel; + /** @brief Initial value for DR2R register.*/ + uint32_t dr2r; + /** @brief Initial value for DR4R register.*/ + uint32_t dr4r; + /** @brief Initial value for DR8R register.*/ + uint32_t dr8r; + /** @brief Initial value for ODR register.*/ + uint32_t odr; + /** @brief Initial value for PUR register.*/ + uint32_t pur; + /** @brief Initial value for PDR register.*/ + uint32_t pdr; + /** @brief Initial value for SLR register.*/ + uint32_t slr; + /** @brief Initial value for DEN register.*/ + uint32_t den; + /** @brief Initial value for AMSEL register.*/ + uint32_t amsel; + /** @brief Initial value for PCTL register.*/ + uint32_t pctl; +} tiva_gpio_setup_t; + +/** + * @brief Tiva GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct +{ + /** @brief GPIO port A setup data.*/ + tiva_gpio_setup_t PAData; + /** @brief GPIO port B setup data.*/ + tiva_gpio_setup_t PBData; + /** @brief GPIO port C setup data.*/ + tiva_gpio_setup_t PCData; + /** @brief GPIO port D setup data.*/ + tiva_gpio_setup_t PDData; + /** @brief GPIO port E setup data.*/ + tiva_gpio_setup_t PEData; + /** @brief GPIO port F setup data.*/ + tiva_gpio_setup_t PFData; +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) + /** @brief GPIO port G setup data.*/ + tiva_gpio_setup_t PGData; +#endif +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) + /** @brief GPIO port H setup data.*/ + tiva_gpio_setup_t PHData; +#endif +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) + /** @brief GPIO port J setup data.*/ + tiva_gpio_setup_t PJData; +#endif +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) + /** @brief GPIO port K setup data.*/ + tiva_gpio_setup_t PKData; +#endif +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) + /** @brief GPIO port L setup data.*/ + tiva_gpio_setup_t PLData; +#endif +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) + /** @brief GPIO port M setup data.*/ + tiva_gpio_setup_t PMData; +#endif +#if TIVA_HAS_GPION || defined(__DOXYGEN__) + /** @brief GPIO port N setup data.*/ + tiva_gpio_setup_t PNData; +#endif +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) + /** @brief GPIO port P setup data.*/ + tiva_gpio_setup_t PPData; +#endif +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) + /** @brief GPIO port Q setup data.*/ + tiva_gpio_setup_t PQData; +#endif +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) + /** @brief GPIO port R setup data.*/ + tiva_gpio_setup_t PRData; +#endif +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) + /** @brief GPIO port S setup data.*/ + tiva_gpio_setup_t PSData; +#endif +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) + /** @brief GPIO port T setup data.*/ + tiva_gpio_setup_t PTData; +#endif +} PALConfig; + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Type of an event mode. + */ +typedef uint32_t ioeventmode_t; + +/** + * @brief Port Identifier. + */ +typedef uint32_t ioportid_t; + +/** + * @brief Type of an pad identifier. + */ +typedef uint32_t iopadid_t; + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPIOA interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOA_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOB interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOB_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOC interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOC_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOD interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOD_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOE interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOE_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOF interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOF_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOG interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOG_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOH interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOH_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOJ interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOJ_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOK interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOK_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOL interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOL_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOM interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOM_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPION interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPION_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP0 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP0_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP1 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP1_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP2 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP2_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP3 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP3_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP4 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP4_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP5 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP5_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP6 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP6_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP7 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP7_IRQ_PRIORITY 3 +#endif +/** @} */ + +/** + * @brief GPIOQ0 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ0_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ1 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ1_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ2 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ2_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ3 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ3_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ4 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ4_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ5 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ5_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ6 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ6_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ7 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ7_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOR interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOR_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOS interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOS_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOT interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOT_IRQ_PRIORITY 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#define GPIOA GPIO_PORTA_AHB_BASE +#define GPIOB GPIO_PORTB_AHB_BASE +#define GPIOC GPIO_PORTC_AHB_BASE +#define GPIOD GPIO_PORTD_AHB_BASE +#define GPIOE GPIO_PORTE_AHB_BASE +#define GPIOF GPIO_PORTF_AHB_BASE +#define GPIOG GPIO_PORTG_AHB_BASE +#define GPIOH GPIO_PORTH_AHB_BASE +#define GPIOJ GPIO_PORTJ_AHB_BASE +#define GPIOK GPIO_PORTK_BASE +#define GPIOL GPIO_PORTL_BASE +#define GPIOM GPIO_PORTM_BASE +#define GPION GPIO_PORTN_BASE +#define GPIOP GPIO_PORTP_BASE +#define GPIOQ GPIO_PORTQ_BASE +#define GPIOR GPIO_PORTR_BASE +#define GPIOS GPIO_PORTS_BASE +#define GPIOT GPIO_PORTT_BASE + +#if TIVA_HAS_GPIOA && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOA" +#endif + +#if TIVA_HAS_GPIOB && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOB_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOB" +#endif + +#if TIVA_HAS_GPIOC && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOC" +#endif + +#if TIVA_HAS_GPIOD && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOD_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOD" +#endif + +#if TIVA_HAS_GPIOE && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOE_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOE" +#endif + +#if TIVA_HAS_GPIOF && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOF_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOF" +#endif + +#if TIVA_HAS_GPIOG && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOG_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOG" +#endif + +#if TIVA_HAS_GPIOH && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOH_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOH" +#endif + +#if TIVA_HAS_GPIOJ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOJ_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOJ" +#endif + +#if TIVA_HAS_GPIOK && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOK_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOK" +#endif + +#if TIVA_HAS_GPIOL && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOL_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOL" +#endif + +#if TIVA_HAS_GPIOM && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOM_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOM" +#endif + +#if TIVA_HAS_GPION && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPION_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPION" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP0" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP1" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP2" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP3" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP4" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP5" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP6" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP7" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ0" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ1" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ2" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ3" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ4" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ5" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ6" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ7" +#endif + +#if TIVA_HAS_GPIOR && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOR_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOR" +#endif + +#if TIVA_HAS_GPIOS && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOS_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOS" +#endif + +#if TIVA_HAS_GPIOT && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOT_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOT" +#endif + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#define IOPORT1 GPIOA + +/** + * @brief GPIO port B identifier. + */ +#define IOPORT2 GPIOB + +/** + * @brief GPIO port C identifier. + */ +#define IOPORT3 GPIOC + +/** + * @brief GPIO port D identifier. + */ +#define IOPORT4 GPIOD + +/** + * @brief GPIO port E identifier. + */ +#define IOPORT5 GPIOE + +/** + * @brief GPIO port F identifier. + */ +#define IOPORT6 GPIOF + +/** + * @brief GPIO port G identifier. + */ +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) +#define IOPORT7 GPIOG +#endif + +/** + * @brief GPIO port H identifier. + */ +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) +#define IOPORT8 GPIOH +#endif + +/** + * @brief GPIO port J identifier. + */ +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) +#define IOPORT9 GPIOJ +#endif + +/** + * @brief GPIO port K identifier. + */ +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) +#define IOPORT10 GPIOK +#endif + +/** + * @brief GPIO port L identifier. + */ +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) +#define IOPORT11 GPIOL +#endif + +/** + * @brief GPIO port M identifier. + */ +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) +#define IOPORT12 GPIOM +#endif + +/** + * @brief GPIO port N identifier. + */ +#if TIVA_HAS_GPION || defined(__DOXYGEN__) +#define IOPORT13 GPION +#endif + +/** + * @brief GPIO port P identifier. + */ +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) +#define IOPORT14 GPIOP +#endif + +/** + * @brief GPIO port Q identifier. + */ +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) +#define IOPORT15 GPIOQ +#endif + +/** + * @brief GPIO port R identifier. + */ +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) +#define IOPORT16 GPIOR +#endif + +/** + * @brief GPIO port S identifier. + */ +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) +#define IOPORT17 GPIOS +#endif + +/** + * @brief GPIO port T identifier. + */ +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) +#define IOPORT18 GPIOT +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) (HWREG((port) + GPIO_O_DATA + (0xff << 2))) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) pal_lld_readport(port) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) (HWREG((port) + GPIO_O_DATA + (0xff << 2)) = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) (HWREG((port) + (GPIO_O_DATA + (bits << 2))) = 0xFF) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) (HWREG((port) + (GPIO_O_DATA + (bits << 2))) = 0) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + (HWREG((port) + (GPIO_O_DATA + (((mask) << (offset)) << 2)))) + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + (HWREG((port) + (GPIO_O_DATA + (((mask) << (offset)) << 2))) = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2)))) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 1 << (bit)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 1 << (pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 0) + +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +#define pal_lld_enablepadevent(port, pad, mode) \ + _pal_lld_enablepadevent(port, pad, mode) + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_disablepadevent(port, pad) \ + _pal_lld_disablepadevent(port, pad) + +/** + * @brief Returns a PAL event structure associated to a pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_get_pad_event(port, pad) \ + &_pal_events[((((((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU) * 8) + pad)]; + +/** + * @brief Returns a PAL event structure associated to a line. + * + * @param[in] line line identifier + * + * @notapi + */ +#define pal_lld_get_line_event(line) \ + &_pal_events[((((((uint32_t)PAL_PORT(line) - (uint32_t)GPIOA) >> 12) & 0x1FU) * 8) + PAL_PAD(line))] + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +extern palevent_t _pal_events[TIVA_GPIO_PINS]; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode); + void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad); + void pal_lld_disable_irqs(void); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* HAL_PAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/GPTM/driver.mk b/os/hal/ports/TIVA/LLD/GPTM/driver.mk new file mode 100644 index 0000000..f003ce4 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPTM/driver.mk @@ -0,0 +1,11 @@ +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c + +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_GPT TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c index 86f2303..8fb02f5 100644 --- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/gpt_lld.c + * @file GPTM/hal_gpt_lld.c * @brief TM4C123x/TM4C129x GPT subsystem low level driver source. * * @addtogroup GPT @@ -133,7 +133,7 @@ GPTDriver GPTD12; */ static void gpt_lld_serve_interrupt(GPTDriver *gptp) { - gptp->gpt->ICR = 0xffffffff; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff; if (gptp->state == GPT_ONESHOT) { gptp->state = GPT_READY; @@ -388,62 +388,62 @@ void gpt_lld_init(void) { /* Driver initialization.*/ #if TIVA_GPT_USE_GPT0 - GPTD1.gpt = GPT0; + GPTD1.gpt = TIMER0_BASE; gptObjectInit(&GPTD1); #endif #if TIVA_GPT_USE_GPT1 - GPTD2.gpt = GPT1; + GPTD2.gpt = TIMER1_BASE; gptObjectInit(&GPTD2); #endif #if TIVA_GPT_USE_GPT2 - GPTD3.gpt = GPT2; + GPTD3.gpt = TIMER2_BASE; gptObjectInit(&GPTD3); #endif #if TIVA_GPT_USE_GPT3 - GPTD4.gpt = GPT3; + GPTD4.gpt = TIMER3_BASE; gptObjectInit(&GPTD4); #endif #if TIVA_GPT_USE_GPT4 - GPTD5.gpt = GPT4; + GPTD5.gpt = TIMER4_BASE; gptObjectInit(&GPTD5); #endif #if TIVA_GPT_USE_GPT5 - GPTD6.gpt = GPT5; + GPTD6.gpt = TIMER5_BASE; gptObjectInit(&GPTD6); #endif #if TIVA_GPT_USE_WGPT0 - GPTD7.gpt = WGPT0; + GPTD7.gpt = WTIMER0_BASE; gptObjectInit(&GPTD7); #endif #if TIVA_GPT_USE_WGPT1 - GPTD8.gpt = WGPT1; + GPTD8.gpt = WTIMER1_BASE; gptObjectInit(&GPTD8); #endif #if TIVA_GPT_USE_WGPT2 - GPTD9.gpt = WGPT2; + GPTD9.gpt = WTIMER2_BASE; gptObjectInit(&GPTD9); #endif #if TIVA_GPT_USE_WGPT3 - GPTD10.gpt = WGPT3; + GPTD10.gpt = WTIMER3_BASE; gptObjectInit(&GPTD10); #endif #if TIVA_GPT_USE_WGPT4 - GPTD11.gpt = WGPT4; + GPTD11.gpt = WTIMER4_BASE; gptObjectInit(&GPTD11); #endif #if TIVA_GPT_USE_WGPT5 - GPTD12.gpt = WGPT5; + GPTD12.gpt = WTIMER5_BASE; gptObjectInit(&GPTD12); #endif } @@ -461,93 +461,141 @@ void gpt_lld_start(GPTDriver *gptp) /* Clock activation.*/ #if TIVA_GPT_USE_GPT0 if (&GPTD1 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 0); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 0); + + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 0))) + ; + nvicEnableVector(TIVA_GPT0A_NUMBER, TIVA_GPT_GPT0A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_GPT1 if (&GPTD2 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 1); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 1); + + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 1))) + ; + nvicEnableVector(TIVA_GPT1A_NUMBER, TIVA_GPT_GPT1A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_GPT2 if (&GPTD3 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 2); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 2); + + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 2))) + ; + nvicEnableVector(TIVA_GPT2A_NUMBER, TIVA_GPT_GPT2A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_GPT3 if (&GPTD4 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 3); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 3); + + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 3))) + ; + nvicEnableVector(TIVA_GPT3A_NUMBER, TIVA_GPT_GPT3A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_GPT4 if (&GPTD5 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 4); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 4); + + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 4))) + ; + nvicEnableVector(TIVA_GPT4A_NUMBER, TIVA_GPT_GPT4A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_GPT5 if (&GPTD6 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 5); + HWREG(SYSCTL_RCGCTIMER) |= (1 << 5); + + while (!(HWREG(SYSCTL_PRTIMER) & (1 << 5))) + ; + nvicEnableVector(TIVA_GPT5A_NUMBER, TIVA_GPT_GPT5A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT0 if (&GPTD7 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 0); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 0); + + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 0))) + ; + nvicEnableVector(TIVA_WGPT0A_NUMBER, TIVA_GPT_WGPT0A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT1 if (&GPTD8 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 1); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 1); + + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 1))) + ; + nvicEnableVector(TIVA_WGPT1A_NUMBER, TIVA_GPT_WGPT1A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT2 if (&GPTD9 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 2); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 2); + + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 2))) + ; + nvicEnableVector(TIVA_WGPT2A_NUMBER, TIVA_GPT_WGPT2A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT3 if (&GPTD10 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 3); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 3); + + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 3))) + ; + nvicEnableVector(TIVA_WGPT3A_NUMBER, TIVA_GPT_WGPT3A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT4 if (&GPTD11 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 4); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 4); + + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 4))) + ; + nvicEnableVector(TIVA_WGPT4A_NUMBER, TIVA_GPT_WGPT4A_IRQ_PRIORITY); } #endif #if TIVA_GPT_USE_WGPT5 if (&GPTD12 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 5); + HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5); + + while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5))) + ; + nvicEnableVector(TIVA_WGPT5A_NUMBER, TIVA_GPT_WGPT5A_IRQ_PRIORITY); } #endif } /* Timer configuration.*/ - gptp->gpt->CTL = 0; - gptp->gpt->CFG = GPTM_CFG_CFG_SPLIT; - gptp->gpt->TAPR = ((TIVA_SYSCLK / gptp->config->frequency) - 1); + HWREG(gptp->gpt + TIMER_O_CTL) = 0; + HWREG(gptp->gpt + TIMER_O_CFG) = TIMER_CFG_16_BIT; + HWREG(gptp->gpt + TIMER_O_TAPR) = ((TIVA_SYSCLK / gptp->config->frequency) - 1); } /** @@ -560,91 +608,91 @@ void gpt_lld_start(GPTDriver *gptp) void gpt_lld_stop(GPTDriver *gptp) { if (gptp->state == GPT_READY) { - gptp->gpt->IMR = 0; - gptp->gpt->TAILR = 0; - gptp->gpt->CTL = 0; + HWREG(gptp->gpt + TIMER_O_IMR) = 0; + HWREG(gptp->gpt + TIMER_O_TAILR) = 0; + HWREG(gptp->gpt + TIMER_O_CTL) = 0; #if TIVA_GPT_USE_GPT0 if (&GPTD1 == gptp) { nvicDisableVector(TIVA_GPT0A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 0); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 0); } #endif #if TIVA_GPT_USE_GPT1 if (&GPTD2 == gptp) { nvicDisableVector(TIVA_GPT1A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 1); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 1); } #endif #if TIVA_GPT_USE_GPT2 if (&GPTD3 == gptp) { nvicDisableVector(TIVA_GPT2A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 2); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 2); } #endif #if TIVA_GPT_USE_GPT3 if (&GPTD4 == gptp) { nvicDisableVector(TIVA_GPT3A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 3); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 3); } #endif #if TIVA_GPT_USE_GPT4 if (&GPTD5 == gptp) { nvicDisableVector(TIVA_GPT4A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 4); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 4); } #endif #if TIVA_GPT_USE_GPT5 if (&GPTD6 == gptp) { nvicDisableVector(TIVA_GPT5A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 5); + HWREG(SYSCTL_RCGCTIMER) &= ~(1 << 5); } #endif #if TIVA_GPT_USE_WGPT0 if (&GPTD7 == gptp) { nvicDisableVector(TIVA_WGPT0A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 0); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 0); } #endif #if TIVA_GPT_USE_WGPT1 if (&GPTD8 == gptp) { nvicDisableVector(TIVA_WGPT1A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 1); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 1); } #endif #if TIVA_GPT_USE_WGPT2 if (&GPTD9 == gptp) { nvicDisableVector(TIVA_WGPT2A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 2); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 2); } #endif #if TIVA_GPT_USE_WGPT3 if (&GPTD10 == gptp) { nvicDisableVector(TIVA_WGPT3A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 3); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 3); } #endif #if TIVA_GPT_USE_WGPT4 if (&GPTD11 == gptp) { nvicDisableVector(TIVA_WGPT4A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 4); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 4); } #endif #if TIVA_GPT_USE_WGPT5 if (&GPTD12 == gptp) { nvicDisableVector(TIVA_WGPT5A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 5); + HWREG(SYSCTL_RCGCWTIMER) &= ~(1 << 5); } #endif } @@ -660,11 +708,11 @@ void gpt_lld_stop(GPTDriver *gptp) */ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { - gptp->gpt->TAILR = interval - 1; - gptp->gpt->ICR = 0xfffffff; - gptp->gpt->IMR = GPTM_IMR_TATOIM; - gptp->gpt->TAMR = GPTM_TAMR_TAMR_PERIODIC | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; - gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; + HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xfffffff; + HWREG(gptp->gpt + TIMER_O_IMR) = TIMER_IMR_TATOIM; + HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_PERIOD | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS; + HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL; } /** @@ -676,9 +724,9 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) */ void gpt_lld_stop_timer(GPTDriver *gptp) { - gptp->gpt->IMR = 0; - gptp->gpt->TAILR = 0; - gptp->gpt->CTL &= ~GPTM_CTL_TAEN; + HWREG(gptp->gpt + TIMER_O_IMR) = 0; + HWREG(gptp->gpt + TIMER_O_TAILR) = 0; + HWREG(gptp->gpt + TIMER_O_CTL) &= ~TIMER_CTL_TAEN; } /** @@ -694,13 +742,13 @@ void gpt_lld_stop_timer(GPTDriver *gptp) */ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { - gptp->gpt->TAMR = GPTM_TAMR_TAMR_ONESHOT | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; - gptp->gpt->TAILR = interval - 1; - gptp->gpt->ICR = 0xffffffff; - gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; - while (!(gptp->gpt->RIS & GPTM_IMR_TATOIM)) + HWREG(gptp->gpt + TIMER_O_TAMR) = TIMER_TAMR_TAMR_1_SHOT | TIMER_TAMR_TAILD | TIMER_TAMR_TASNAPS; + HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff; + HWREG(gptp->gpt + TIMER_O_CTL) = TIMER_CTL_TAEN | TIMER_CTL_TASTALL; + while (!(HWREG(gptp->gpt + TIMER_O_RIS) & TIMER_IMR_TATOIM)) ; - gptp->gpt->ICR = 0xffffffff; + HWREG(gptp->gpt + TIMER_O_ICR) = 0xffffffff; } #endif /* HAL_USE_GPT */ diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h index e518e58..6b4196f 100644 --- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/gpt_lld.h + * @file GPTM/hal_gpt_lld.h * @brief TM4C123x/TM4C129x GPT subsystem low level driver header. * * @addtogroup GPT @@ -405,7 +405,7 @@ struct GPTDriver { /** * @brief Pointer to the GPT registers block. */ - GPT_TypeDef *gpt; + uint32_t gpt; }; /*===========================================================================*/ @@ -426,7 +426,7 @@ struct GPTDriver { * @notapi */ #define gpt_lld_change_interval(gptp, interval) { \ - gptp->gpt->TAILR = interval - 1; \ + HWREG(gptp->gpt + TIMER_O_TAILR) = interval - 1; \ } /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c index 30fdb8a..0f9576a 100644 --- a/os/hal/ports/TIVA/LLD/hal_st_lld.c +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file Tiva/LLD/st_lld.c + * @file GPTM/hal_st_lld.c * @brief ST Driver subsystem low level driver code. * * @addtogroup ST @@ -37,44 +37,44 @@ #if TIVA_ST_TIMER_NUMBER == 0 #define ST_HANDLER TIVA_WGPT0A_HANDLER #define ST_NUMBER TIVA_WGPT0A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 0)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 0))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 0))) #elif TIVA_ST_TIMER_NUMBER == 1 #define ST_HANDLER TIVA_WGPT1A_HANDLER #define ST_NUMBER TIVA_WGPT1A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 1)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 1))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 1))) #elif TIVA_ST_TIMER_NUMBER == 2 #define ST_HANDLER TIVA_WGPT2A_HANDLER #define ST_NUMBER TIVA_WGPT2A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 2)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 2))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 2))) #elif TIVA_ST_TIMER_NUMBER == 3 #define ST_HANDLER TIVA_WGPT3A_HANDLER #define ST_NUMBER TIVA_WGPT3A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 3)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 3))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 3))) #elif TIVA_ST_TIMER_NUMBER == 4 #define ST_HANDLER TIVA_WGPT4A_HANDLER #define ST_NUMBER TIVA_WGPT4A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 4)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 4))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 4))) #elif TIVA_ST_TIMER_NUMBER == 5 #define ST_HANDLER TIVA_WGPT5A_HANDLER #define ST_NUMBER TIVA_WGPT5A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 5)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 5))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5))) #else #error "TIVA_ST_USE_TIMER specifies an unsupported timer" #endif -#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF +#if (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1 > 0xFFFF #error "the selected ST frequency is not obtainable because TIM timer prescaler limits" #endif @@ -83,38 +83,38 @@ #if TIVA_ST_TIMER_NUMBER == 0 #define ST_HANDLER TIVA_GPT0A_HANDLER #define ST_NUMBER TIVA_GPT0A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 0)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 0))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 0))) #elif TIVA_ST_TIMER_NUMBER == 1 #define ST_HANDLER TIVA_GPT1A_HANDLER #define ST_NUMBER TIVA_GPT1A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 1)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 1))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 1))) #elif TIVA_ST_TIMER_NUMBER == 2 #define ST_HANDLER TIVA_GPT2A_HANDLER #define ST_NUMBER TIVA_GPT2A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 2)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 2))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 2))) #elif TIVA_ST_TIMER_NUMBER == 3 #define ST_HANDLER TIVA_GPT3A_HANDLER #define ST_NUMBER TIVA_GPT3A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 3)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 3))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 3))) #elif TIVA_ST_TIMER_NUMBER == 4 #define ST_HANDLER TIVA_GPT4A_HANDLER #define ST_NUMBER TIVA_GPT4A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 4)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 4))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 4))) #elif TIVA_ST_TIMER_NUMBER == 5 #define ST_HANDLER TIVA_GPT5A_HANDLER #define ST_NUMBER TIVA_GPT5A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 5)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 5))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 5))) #else #error "TIVA_ST_USE_TIMER specifies an unsupported timer" @@ -184,10 +184,10 @@ OSAL_IRQ_HANDLER(ST_HANDLER) OSAL_IRQ_PROLOGUE(); - mis = TIVA_ST_TIM->MIS; - TIVA_ST_TIM->ICR = mis; + mis = HWREG(TIVA_ST_TIM + TIMER_O_MIS); + HWREG(TIVA_ST_TIM + TIMER_O_ICR) = mis; - if (mis & GPTM_IMR_TAMIM) { + if (mis & TIMER_IMR_TAMIM) { osalSysLockFromISR(); osalOsTimerHandlerI(); osalSysUnlockFromISR(); @@ -218,15 +218,17 @@ void st_lld_init(void) ST_WAIT_CLOCK(); /* Initializing the counter in free running down mode.*/ - TIVA_ST_TIM->CTL = 0; - TIVA_ST_TIM->CFG = GPTM_CFG_CFG_SPLIT; /* Timer split mode */ - TIVA_ST_TIM->TAMR = (GPTM_TAMR_TAMR_PERIODIC |/* Periodic mode */ - GPTM_TAMR_TAMIE | /* Match interrupt enable */ - GPTM_TAMR_TASNAPS); /* Snapshot mode */ - - TIVA_ST_TIM->TAPR = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; - TIVA_ST_TIM->CTL = (GPTM_CTL_TAEN | /* Timer A enable */ - GPTM_CTL_TASTALL); /* Timer A stall when paused */ + HWREG(TIVA_ST_TIM + TIMER_O_CTL) = 0; + HWREG(TIVA_ST_TIM + TIMER_O_CFG) = TIMER_CFG_16_BIT; /* Timer split mode */ + HWREG(TIVA_ST_TIM + TIMER_O_TAMR) = ( + TIMER_TAMR_TAMR_PERIOD | /* Periodic mode */ + TIMER_TAMR_TAMIE | /* Match interrupt enable */ + TIMER_TAMR_TASNAPS); /* Snapshot mode */ + + HWREG(TIVA_ST_TIM + TIMER_O_TAPR) = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; + HWREG(TIVA_ST_TIM + TIMER_O_CTL) = ( + TIMER_CTL_TAEN | /* Timer A enable */ + TIMER_CTL_TASTALL); /* Timer A stall when paused */ /* IRQ enabled.*/ nvicEnableVector(ST_NUMBER, TIVA_ST_IRQ_PRIORITY); diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h index 35bf008..a0b4dfc 100644 --- a/os/hal/ports/TIVA/LLD/hal_st_lld.h +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file Tiva/LLD/st_lld.h + * @file GPTM/hal_st_lld.h * @brief ST Driver subsystem low level driver header. * @details This header is designed to be include-able without having to * include other files from the HAL. @@ -29,7 +29,6 @@ #include "mcuconf.h" #include "tiva_registry.h" -#include "tiva_gpt.h" /*===========================================================================*/ /* Driver constants. */ @@ -82,37 +81,37 @@ #if !TIVA_HAS_WGPT0 #error "WGPT0 not present" #endif -#define TIVA_ST_TIM WGPT0 +#define TIVA_ST_TIM WTIMER0_BASE #elif TIVA_ST_TIMER_NUMBER == 1 #if !TIVA_HAS_WGPT1 #error "WGPT1 not present" #endif -#define TIVA_ST_TIM WGPT1 +#define TIVA_ST_TIM WTIMER1_BASE #elif TIVA_ST_TIMER_NUMBER == 2 #if !TIVA_HAS_WGPT2 #error "WGPT2 not present" #endif -#define TIVA_ST_TIM WGPT2 +#define TIVA_ST_TIM WTIMER2_BASE #elif TIVA_ST_TIMER_NUMBER == 3 #if !TIVA_HAS_WGPT3 #error "WGPT3 not present" #endif -#define TIVA_ST_TIM WGPT3 +#define TIVA_ST_TIM WTIMER3_BASE #elif TIVA_ST_TIMER_NUMBER == 4 #if !TIVA_HAS_WGPT4 #error "WGPT4 not present" #endif -#define TIVA_ST_TIM WGPT4 +#define TIVA_ST_TIM WTIMER4_BASE #elif TIVA_ST_TIMER_NUMBER == 5 #if !TIVA_HAS_WGPT5 #error "WGPT5 not present" #endif -#define TIVA_ST_TIM WGPT5 +#define TIVA_ST_TIM WTIMER5_BASE #else #error "TIVA_ST_USE_TIMER specifies an unsupported timer" @@ -124,37 +123,37 @@ #if !TIVA_HAS_GPT0 #error "GPT0 not present" #endif -#define TIVA_ST_TIM GPT0 +#define TIVA_ST_TIM TIMER0_BASE #elif TIVA_ST_TIMER_NUMBER == 1 #if !TIVA_HAS_GPT1 #error "GPT1 not present" #endif -#define TIVA_ST_TIM GPT1 +#define TIVA_ST_TIM TIMER1_BASE #elif TIVA_ST_TIMER_NUMBER == 2 #if !TIVA_HAS_GPT2 #error "GPT2 not present" #endif -#define TIVA_ST_TIM GPT2 +#define TIVA_ST_TIM TIMER2_BASE #elif TIVA_ST_TIMER_NUMBER == 3 #if !TIVA_HAS_GPT3 #error "GPT3 not present" #endif -#define TIVA_ST_TIM GPT3 +#define TIVA_ST_TIM TIMER3_BASE #elif TIVA_ST_TIMER_NUMBER == 4 #if !TIVA_HAS_GPT4 #error "GPT4 not present" #endif -#define TIVA_ST_TIM GPT4 +#define TIVA_ST_TIM TIMER4_BASE #elif TIVA_ST_TIMER_NUMBER == 5 #if !TIVA_HAS_GPT5 #error "GPT5 not present" #endif -#define TIVA_ST_TIM GPT5 +#define TIVA_ST_TIM TIMER5_BASE #else #error "TIVA_ST_TIMER_NUMBER specifies an unsupported timer" @@ -164,11 +163,6 @@ #error "wrong value defined for TIVA_ST_USE_WIDE_TIMER" #endif -#if OSAL_ST_MODE != OSAL_ST_MODE_NONE && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ST" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -202,7 +196,7 @@ extern "C" { */ static inline systime_t st_lld_get_counter(void) { - return (systime_t) (((systime_t) 0xffffffff) - TIVA_ST_TIM->TAR); + return (systime_t) (((systime_t) 0xffffffff) - HWREG(TIVA_ST_TIM + TIMER_O_TAV)); } /** @@ -216,9 +210,9 @@ static inline systime_t st_lld_get_counter(void) */ static inline void st_lld_start_alarm(systime_t time) { - TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); - TIVA_ST_TIM->ICR = TIVA_ST_TIM->MIS; - TIVA_ST_TIM->IMR = GPTM_IMR_TAMIM; + HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time); + HWREG(TIVA_ST_TIM + TIMER_O_ICR) = HWREG(TIVA_ST_TIM + TIMER_O_MIS); + HWREG(TIVA_ST_TIM + TIMER_O_IMR) = TIMER_IMR_TAMIM; } /** @@ -228,7 +222,7 @@ static inline void st_lld_start_alarm(systime_t time) */ static inline void st_lld_stop_alarm(void) { - TIVA_ST_TIM->IMR = 0; + HWREG(TIVA_ST_TIM + TIMER_O_IMR) = 0; } /** @@ -240,7 +234,7 @@ static inline void st_lld_stop_alarm(void) */ static inline void st_lld_set_alarm(systime_t time) { - TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); + HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time); } /** @@ -252,7 +246,7 @@ static inline void st_lld_set_alarm(systime_t time) */ static inline systime_t st_lld_get_alarm(void) { - return (systime_t) (((systime_t)0xffffffff) - TIVA_ST_TIM->TAMATCHR); + return (systime_t) (((systime_t)0xffffffff) - HWREG(TIVA_ST_TIM + TIMER_O_TAMATCHR)); } /** @@ -266,7 +260,7 @@ static inline systime_t st_lld_get_alarm(void) */ static inline bool st_lld_is_alarm_active(void) { - return (bool) ((TIVA_ST_TIM->IMR & GPTM_IMR_TAMIM) !=0); + return (bool) ((HWREG(TIVA_ST_TIM + TIMER_O_IMR) & TIMER_IMR_TAMIM) !=0); } #endif /* HAL_ST_LLD_H */ diff --git a/os/hal/ports/TIVA/LLD/I2C/driver.mk b/os/hal/ports/TIVA/LLD/I2C/driver.mk new file mode 100644 index 0000000..d327a19 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/I2C/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_I2C TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/I2C diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c index 5d80633..7ba7bad 100644 --- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/LLD/i2c_lld.c + * @file I2C/hal_i2c_lld.c * @brief TM4C123x/TM4C129x I2C subsystem low level driver source. * * @addtogroup I2C @@ -30,6 +30,33 @@ /* Driver local definitions. */ /*===========================================================================*/ +// interrupt states +#define STATE_IDLE 0 +#define STATE_WRITE_NEXT 1 +#define STATE_WRITE_FINAL 2 +#define STATE_WAIT_ACK 3 +#define STATE_SEND_ACK 4 +#define STATE_READ_ONE 5 +#define STATE_READ_FIRST 6 +#define STATE_READ_NEXT 7 +#define STATE_READ_FINAL 8 +#define STATE_READ_WAIT 9 + +#define TIVA_I2C_SIGNLE_SEND (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_START (I2C_MCS_RUN | I2C_MCS_START) +#define TIVA_I2C_BURST_SEND_CONTINUE (I2C_MCS_RUN) +#define TIVA_I2C_BURST_SEND_FINISH (I2C_MCS_RUN | I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_STOP (I2C_MCS_STOP) +#define TIVA_I2C_BURST_SEND_ERROR_STOP (I2C_MCS_STOP) + +#define TIVA_I2C_SINGLE_RECEIVE (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_STOP) +#define TIVA_I2C_BURST_RECEIVE_START (I2C_MCS_RUN | I2C_MCS_START | I2C_MCS_ACK) +#define TIVA_I2C_BURST_RECEIVE_CONTINUE (I2C_MCS_RUN | I2C_MCS_ACK) +#define TIVA_I2C_BURST_RECEIVE_FINISH (I2C_MCS_RUN | I2C_MCS_STOP) +#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (I2C_MCS_STOP) + +#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1) + /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ @@ -125,19 +152,19 @@ I2CDriver I2CD10; */ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; uint32_t status; // clear MIS bit in MICR by writing 1 - dp->MICR = 1; + HWREG(i2c + I2C_O_MICR) = 1; // read interrupt status - status = dp->MCS; + status = HWREG(i2c + I2C_O_MCS); - if (status & TIVA_MCS_ERROR) { + if (status & I2C_MCS_ERROR) { i2cp->errors |= I2C_BUS_ERROR; } - if (status & TIVA_MCS_ARBLST) { + if (status & I2C_MCS_ARBLST) { i2cp->errors |= I2C_ARBITRATION_LOST; } @@ -152,11 +179,11 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) if (i2cp->txbytes == 1) { i2cp->intstate = STATE_WRITE_FINAL; } - dp->MDR = *(i2cp->txbuf); + HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf); i2cp->txbuf++; i2cp->txbytes--; // start transmission - dp->MCS = TIVA_I2C_BURST_SEND_CONTINUE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_CONTINUE; break; } case STATE_WRITE_FINAL: { @@ -169,12 +196,12 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) else { i2cp->intstate = STATE_READ_FIRST; } - dp->MDR = *(i2cp->txbuf); + HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf); i2cp->txbuf++; // txbytes - 1 i2cp->txbytes--; // start transmission - dp->MCS = TIVA_I2C_BURST_SEND_FINISH; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_FINISH; break; } case STATE_WAIT_ACK: { @@ -189,10 +216,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) i2cp->addr |= 1; // set slave address - dp->MSA = i2cp->addr; - i2cp->rxbytes--; + HWREG(i2c + I2C_O_MSA) = i2cp->addr; + i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_SINGLE_RECEIVE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE; break; } @@ -208,10 +235,10 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) i2cp->addr |= 1; // set slave address - dp->MSA = i2cp->addr; - i2cp->rxbytes--; + HWREG(i2c + I2C_O_MSA) = i2cp->addr; + i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_START; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_START; break; } @@ -219,27 +246,27 @@ static void i2c_lld_serve_interrupt(I2CDriver *i2cp) if(i2cp->rxbytes == 2) { i2cp->intstate = STATE_READ_FINAL; } - *(i2cp->rxbuf) = dp->MDR; + *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR); i2cp->rxbuf++; i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_CONTINUE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_CONTINUE; break; } case STATE_READ_FINAL: { i2cp->intstate = STATE_READ_WAIT; - *(i2cp->rxbuf) = dp->MDR; + *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR); i2cp->rxbuf++; - i2cp->rxbytes--; + i2cp->rxbytes--; //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_FINISH; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_RECEIVE_FINISH; break; } case STATE_READ_WAIT: { i2cp->intstate = STATE_IDLE; - *(i2cp->rxbuf) = dp->MDR; + *(i2cp->rxbuf) = HWREG(i2c + I2C_O_MDR); i2cp->rxbuf++; _i2c_wakeup_isr(i2cp); break; @@ -430,61 +457,61 @@ void i2c_lld_init(void) { #if TIVA_I2C_USE_I2C0 i2cObjectInit(&I2CD1); I2CD1.thread = NULL; - I2CD1.i2c = I2C0; + I2CD1.i2c = I2C0_BASE; #endif /* TIVA_I2C_USE_I2C0 */ #if TIVA_I2C_USE_I2C1 i2cObjectInit(&I2CD2); I2CD2.thread = NULL; - I2CD2.i2c = I2C1; + I2CD2.i2c = I2C1_BASE; #endif /* TIVA_I2C_USE_I2C1 */ #if TIVA_I2C_USE_I2C2 i2cObjectInit(&I2CD3); I2CD3.thread = NULL; - I2CD3.i2c = I2C2; + I2CD3.i2c = I2C2_BASE; #endif /* TIVA_I2C_USE_I2C2 */ #if TIVA_I2C_USE_I2C3 i2cObjectInit(&I2CD4); I2CD4.thread = NULL; - I2CD4.i2c = I2C3; + I2CD4.i2c = I2C3_BASE; #endif /* TIVA_I2C_USE_I2C3 */ #if TIVA_I2C_USE_I2C4 i2cObjectInit(&I2CD5); I2CD5.thread = NULL; - I2CD5.i2c = I2C4; + I2CD5.i2c = I2C4_BASE; #endif /* TIVA_I2C_USE_I2C4 */ #if TIVA_I2C_USE_I2C5 i2cObjectInit(&I2CD6); I2CD6.thread = NULL; - I2CD6.i2c = I2C5; + I2CD6.i2c = I2C5_BASE; #endif /* TIVA_I2C_USE_I2C5 */ #if TIVA_I2C_USE_I2C6 i2cObjectInit(&I2CD7); I2CD7.thread = NULL; - I2CD7.i2c = I2C6; + I2CD7.i2c = I2C6_BASE; #endif /* TIVA_I2C_USE_I2C6 */ #if TIVA_I2C_USE_I2C7 i2cObjectInit(&I2CD8); I2CD8.thread = NULL; - I2CD8.i2c = I2C7; + I2CD8.i2c = I2C7_BASE; #endif /* TIVA_I2C_USE_I2C7 */ #if TIVA_I2C_USE_I2C8 i2cObjectInit(&I2CD9); I2CD9.thread = NULL; - I2CD9.i2c = I2C8; + I2CD9.i2c = I2C8_BASE; #endif /* TIVA_I2C_USE_I2C8 */ #if TIVA_I2C_USE_I2C9 i2cObjectInit(&I2CD10); I2CD10.thread = NULL; - I2CD10.i2c = I2C9; + I2CD10.i2c = I2C9_BASE; #endif /* TIVA_I2C_USE_I2C9 */ } @@ -497,83 +524,123 @@ void i2c_lld_init(void) { */ void i2c_lld_start(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; /* If in stopped state then enables the I2C clocks.*/ if (i2cp->state == I2C_STOP) { #if TIVA_I2C_USE_I2C0 if (&I2CD1 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 0); + HWREG(SYSCTL_RCGCI2C) |= (1 << 0); + + while (!(HWREG(SYSCTL_PRI2C) & (1 << 0))) + ; + nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C0 */ #if TIVA_I2C_USE_I2C1 if (&I2CD2 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 1); + HWREG(SYSCTL_RCGCI2C) |= (1 << 1); + + while (!(HWREG(SYSCTL_PRI2C) & (1 << 1))) + ; + nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C1 */ #if TIVA_I2C_USE_I2C2 if (&I2CD3 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 2); + HWREG(SYSCTL_RCGCI2C) |= (1 << 2); + + while (!(HWREG(SYSCTL_PRI2C) & (1 << 2))) + ; + nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C2 */ #if TIVA_I2C_USE_I2C3 if (&I2CD4 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 3); + HWREG(SYSCTL_RCGCI2C) |= (1 << 3); + + while (!(HWREG(SYSCTL_PRI2C) & (1 << 3))) + ; + nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C3 */ #if TIVA_I2C_USE_I2C4 if (&I2CD5 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 4); + HWREG(SYSCTL_RCGCI2C) |= (1 << 4); + + while (!(HWREG(SYSCTL_PRI2C) & (1 << 4))) + ; + nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C4 */ #if TIVA_I2C_USE_I2C5 if (&I2CD6 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 5); + HWREG(SYSCTL_RCGCI2C) |= (1 << 5); + + while (!(HWREG(SYSCTL_PRI2C) & (1 << 5))) + ; + nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C5 */ #if TIVA_I2C_USE_I2C6 if (&I2CD7 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 6); + HWREG(SYSCTL_RCGCI2C) |= (1 << 6); + + while (!(HWREG(SYSCTL_PRI2C) & (1 << 6))) + ; + nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C6 */ #if TIVA_I2C_USE_I2C7 if (&I2CD8 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 7); + HWREG(SYSCTL_RCGCI2C) |= (1 << 7); + + while (!(HWREG(SYSCTL_PRI2C) & (1 << 7))) + ; + nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C7 */ #if TIVA_I2C_USE_I2C8 if (&I2CD9 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 8); + HWREG(SYSCTL_RCGCI2C) |= (1 << 8); + + while (!(HWREG(SYSCTL_PRI2C) & (1 << 8))) + ; + nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C7 */ #if TIVA_I2C_USE_I2C9 if (&I2CD10 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 9); + HWREG(SYSCTL_RCGCI2C) |= (1 << 9); + + while (!(HWREG(SYSCTL_PRI2C) & (1 << 9))) + ; + nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY); } #endif /* TIVA_I2C_USE_I2C7 */ } - dp->MCR = 0x10; - dp->MTPR = MTPR_VALUE; + HWREG(i2c + I2C_O_MCR) = 0x10; + HWREG(i2c + I2C_O_MTPR) = MTPR_VALUE; } /** @@ -585,7 +652,8 @@ void i2c_lld_start(I2CDriver *i2cp) */ void i2c_lld_stop(I2CDriver *i2cp) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; + /* If not in stopped state then disables the I2C clock.*/ if (i2cp->state != I2C_STOP) { @@ -595,76 +663,76 @@ void i2c_lld_stop(I2CDriver *i2cp) #if TIVA_I2C_USE_I2C0 if (&I2CD1 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 0); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 0); nvicDisableVector(TIVA_I2C0_NUMBER); } #endif /* TIVA_I2C_USE_I2C0 */ #if TIVA_I2C_USE_I2C1 if (&I2CD2 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 1); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 1); nvicDisableVector(TIVA_I2C1_NUMBER); } #endif /* TIVA_I2C_USE_I2C1 */ #if TIVA_I2C_USE_I2C2 if (&I2CD3 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 2); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 2); nvicDisableVector(TIVA_I2C2_NUMBER); } #endif /* TIVA_I2C_USE_I2C2 */ #if TIVA_I2C_USE_I2C3 if (&I2CD4 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 3); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 3); nvicDisableVector(TIVA_I2C3_NUMBER); } #endif /* TIVA_I2C_USE_I2C3 */ #if TIVA_I2C_USE_I2C4 if (&I2CD5 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 4); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 4); nvicDisableVector(TIVA_I2C4_NUMBER); } #endif /* TIVA_I2C_USE_I2C4 */ #if TIVA_I2C_USE_I2C5 if (&I2CD6 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 5); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 5); nvicDisableVector(TIVA_I2C5_NUMBER); } #endif /* TIVA_I2C_USE_I2C5 */ #if TIVA_I2C_USE_I2C6 if (&I2CD7 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 6); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 6); nvicDisableVector(TIVA_I2C6_NUMBER); } #endif /* TIVA_I2C_USE_I2C6 */ #if TIVA_I2C_USE_I2C7 if (&I2CD8 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 7); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 7); nvicDisableVector(TIVA_I2C7_NUMBER); } #endif /* TIVA_I2C_USE_I2C7 */ #if TIVA_I2C_USE_I2C8 if (&I2CD9 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 8); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 8); nvicDisableVector(TIVA_I2C8_NUMBER); } #endif /* TIVA_I2C_USE_I2C8 */ #if TIVA_I2C_USE_I2C9 if (&I2CD10 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 9); + HWREG(SYSCTL_RCGCI2C) &= ~(1 << 9); nvicDisableVector(TIVA_I2C9_NUMBER); } #endif /* TIVA_I2C_USE_I2C9 */ - dp->MCR = 0; - dp->MTPR = 0; + HWREG(i2c + I2C_O_MCR) = 0; + HWREG(i2c + I2C_O_MTPR) = 0; } } @@ -693,7 +761,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; systime_t start, end; i2cp->rxbuf = rxbuf; @@ -710,7 +778,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, /* Calculating the time window for the timeout on the busy bus condition.*/ start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); + end = start + OSAL_MS2I(TIVA_I2C_BUSY_TIMEOUT); /* Waits until BUSY flag is reset or, alternatively, for a timeout condition.*/ @@ -719,22 +787,22 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if ((dp->MCS & TIVA_MCS_BUSY) == 0) + if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0) break; /* If the system time went outside the allowed window then a timeout condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) + if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) return MSG_TIMEOUT; osalSysUnlock(); } /* set slave address */ - dp->MSA = addr; + HWREG(i2c + I2C_O_MSA) = addr; /* Starts the operation.*/ - dp->MCS = TIVA_I2C_SINGLE_RECEIVE; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SINGLE_RECEIVE; /* Waits for the operation completion or a timeout.*/ return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); @@ -768,7 +836,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { - I2C_TypeDef *dp = i2cp->i2c; + uint32_t i2c = i2cp->i2c; systime_t start, end; i2cp->rxbuf = rxbuf; @@ -784,7 +852,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, /* Calculating the time window for the timeout on the busy bus condition.*/ start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); + end = start + OSAL_MS2I(TIVA_I2C_BUSY_TIMEOUT); /* Waits until BUSY flag is reset or, alternatively, for a timeout condition.*/ @@ -793,12 +861,13 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if ((dp->MCS & TIVA_MCS_BUSY) == 0) + if ((HWREG(i2c + I2C_O_MCS) & I2C_MCS_BUSY) == 0) break; /* If the system time went outside the allowed window then a timeout condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) + if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) + return MSG_TIMEOUT; osalSysUnlock(); @@ -808,13 +877,13 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->addr = addr << 1 | 0; /* set slave address */ - dp->MSA = i2cp->addr; + HWREG(i2c + I2C_O_MSA) = i2cp->addr; /* enable interrupts */ - dp->MIMR = TIVA_MIMR_IM; + HWREG(i2c + I2C_O_MIMR) = I2C_MIMR_IM; /* put data in register */ - dp->MDR = *(i2cp->txbuf); + HWREG(i2c + I2C_O_MDR) = *(i2cp->txbuf); /* check if 1 or more bytes */ if (i2cp->txbytes == 1) { @@ -827,7 +896,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->intstate = STATE_READ_FIRST; } // single byte send - dp->MCS = TIVA_I2C_SIGNLE_SEND; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_SIGNLE_SEND; } else { if (i2cp->txbytes == 2) { @@ -839,7 +908,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, i2cp->intstate = STATE_WRITE_NEXT; } // multiple bytes start send - dp->MCS = TIVA_I2C_BURST_SEND_START; + HWREG(i2c + I2C_O_MCS) = TIVA_I2C_BURST_SEND_START; } i2cp->txbuf++; diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h index 460d231..66669f1 100644 --- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/LLD/i2c_lld.h + * @file I2C/hal_i2c_lld.h * @brief TM4C123x/TM4C129x I2C subsystem low level driver header. * * @addtogroup I2C @@ -31,80 +31,6 @@ /* Driver constants. */ /*===========================================================================*/ -#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1) - -#define TIVA_MSA_RS (1 << 0) -#define TIVA_MSA_SA (127 << 1) - -#define TIVA_MCS_BUSY (1 << 0) -#define TIVA_MCS_ERROR (1 << 1) -#define TIVA_MCS_ADRACK (1 << 2) -#define TIVA_MCS_DATACK (1 << 3) -#define TIVA_MCS_ARBLST (1 << 4) -#define TIVA_MCS_IDLE (1 << 5) -#define TIVA_MCS_BUSBSY (1 << 6) -#define TIVA_MCS_CLKTO (1 << 7) - -#define TIVA_MCS_RUN (1 << 0) -#define TIVA_MCS_START (1 << 1) -#define TIVA_MCS_STOP (1 << 2) -#define TIVA_MCS_ACK (1 << 3) -#define TIVA_MCS_HS (1 << 4) - -#define TIVA_I2C_SIGNLE_SEND (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_START (TIVA_MCS_RUN | TIVA_MCS_START) -#define TIVA_I2C_BURST_SEND_CONTINUE (TIVA_MCS_RUN) -#define TIVA_I2C_BURST_SEND_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_STOP (TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_I2C_SINGLE_RECEIVE (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_START (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_CONTINUE (TIVA_MCS_RUN | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_MDR_DATA (255 << 0) - -#define TIVA_MTPR_TPR (127 << 0) -#define TIVA_MTPR_HS (1 << 7) - -#define TIVA_MIMR_IM (1 << 0) -#define TIVA_MIMR_CLKIM (1 << 1) - -#define TIVA_MRIS_RIS (1 << 0) -#define TIVA_MRIS_CLKRIS (1 << 1) - -#define TIVA_MMIS_MIS (1 << 0) -#define TIVA_MMIS_CLKMIS (1 << 1) - -#define TIVA_MICR_IC (1 << 0) -#define TIVA_MICR_CLKIC (1 << 1) - -#define TIVA_MCR_LPBK (1 << 0) -#define TIVA_MCR_MFE (1 << 4) -#define TIVA_MCR_SFE (1 << 5) -#define TIVA_MCR_GFE (1 << 6) - -#define TIVA_MCLKOCNT_CNTL (255 << 0) - -#define TIVA_MBMON_SCL (1 << 0) -#define TIVA_MBMON_SDA (1 << 1) - -#define TIVA_MCR2_GFPW (7 << 4) - -// interrupt states -#define STATE_IDLE 0 -#define STATE_WRITE_NEXT 1 -#define STATE_WRITE_FINAL 2 -#define STATE_WAIT_ACK 3 -#define STATE_SEND_ACK 4 -#define STATE_READ_ONE 5 -#define STATE_READ_FIRST 6 -#define STATE_READ_NEXT 7 -#define STATE_READ_FINAL 8 -#define STATE_READ_WAIT 9 - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -440,7 +366,7 @@ struct I2CDriver { /** * @brief Pointer to the I2Cx registers block. */ - I2C_TypeDef *i2c; + uint32_t i2c; }; /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/MAC/driver.mk b/os/hal/ports/TIVA/LLD/MAC/driver.mk new file mode 100644 index 0000000..3847ce8 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/MAC/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_MAC TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/MAC diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.c b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c index 04177b6..1f1f220 100644 --- a/os/hal/ports/TIVA/LLD/hal_mac_lld.c +++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/mac_lld.c + * @file MAC/hal_mac_lld.c * @brief MAC Driver subsystem low level driver source. * * @addtogroup MAC @@ -89,10 +89,10 @@ static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]; */ static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) { - ETH->MIIDATA = value; - ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB; + HWREG(EMAC0_BASE + EMAC_O_MIIDATA) = value; + HWREG(EMAC0_BASE + EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB; - while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) + while ((HWREG(EMAC0_BASE + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0) ; } @@ -126,12 +126,12 @@ static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value) */ static uint32_t mii_read(MACDriver *macp, uint32_t reg) { - ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB; + HWREG(EMAC0_BASE + EMAC_O_MIIADDR) = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB; - while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) + while ((HWREG(EMAC0_BASE + EMAC_O_MIIADDR) & EMAC_MIIADDR_MIIB) != 0) ; - return ETH->MIIDATA; + return HWREG(EMAC0_BASE + EMAC_O_MIIDATA); } /** @@ -171,7 +171,7 @@ static void mii_find_phy(MACDriver *macp) #endif for (i = 0; i < 31; i++) { macp->phyaddr = i << 11; - ETH->MIIDATA = (i << 6) | MACMIIADDR_CR; + HWREG(EMAC0_BASE + EMAC_O_MIIDATA) = (i << 6) | MACMIIADDR_CR; if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) && ((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { return; @@ -196,20 +196,20 @@ static void mac_lld_set_address(const uint8_t *p) { /* MAC address configuration, only a single address comparator is used, hash table not used.*/ - ETH->ADDR0H = ((uint32_t)p[5] << 8) | + HWREG(EMAC0_BASE + EMAC_O_ADDR0H) = ((uint32_t)p[5] << 8) | ((uint32_t)p[4] << 0); - ETH->ADDR0L = ((uint32_t)p[3] << 24) | + HWREG(EMAC0_BASE + EMAC_O_ADDR0L) = ((uint32_t)p[3] << 24) | ((uint32_t)p[2] << 16) | ((uint32_t)p[1] << 8) | ((uint32_t)p[0] << 0); - ETH->ADDR1H = 0x0000FFFF; - ETH->ADDR1L = 0xFFFFFFFF; - ETH->ADDR2H = 0x0000FFFF; - ETH->ADDR2L = 0xFFFFFFFF; - ETH->ADDR3H = 0x0000FFFF; - ETH->ADDR3L = 0xFFFFFFFF; - ETH->HASHTBLH = 0; - ETH->HASHTBLL = 0; + HWREG(EMAC0_BASE + EMAC_O_ADDR1H) = 0x0000FFFF; + HWREG(EMAC0_BASE + EMAC_O_ADDR1L) = 0xFFFFFFFF; + HWREG(EMAC0_BASE + EMAC_O_ADDR2H) = 0x0000FFFF; + HWREG(EMAC0_BASE + EMAC_O_ADDR2L) = 0xFFFFFFFF; + HWREG(EMAC0_BASE + EMAC_O_ADDR3H) = 0x0000FFFF; + HWREG(EMAC0_BASE + EMAC_O_ADDR3L) = 0xFFFFFFFF; + HWREG(EMAC0_BASE + EMAC_O_HASHTBLH) = 0; + HWREG(EMAC0_BASE + EMAC_O_HASHTBLL) = 0; } /*===========================================================================*/ @@ -222,8 +222,8 @@ CH_IRQ_HANDLER(TIVA_MAC_HANDLER) CH_IRQ_PROLOGUE(); - dmaris = ETH->DMARIS; - ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/ + dmaris = HWREG(EMAC0_BASE + EMAC_O_DMARIS); + HWREG(EMAC0_BASE + EMAC_O_DMARIS) = dmaris & 0x0001FFFF; /* Clear status bits.*/ if (dmaris & (1 << 6)) { /* Data Received.*/ @@ -275,26 +275,26 @@ void mac_lld_init(void) } /* Enable MAC clock */ - SYSCTL->RCGCEMAC = 1; - while (SYSCTL->PREMAC != 0x01) + HWREG(SYSCTL_RCGCEMAC) = 1; + while (HWREG(SYSCTL_PREMAC) != 0x01) ; /* Set PHYHOLD bit */ - ETH->PC |= 1; + HWREG(EMAC0_BASE + EMAC_O_PC) |= 1; /* Enable PHY clock */ - SYSCTL->RCGCEPHY = 1; - while (SYSCTL->PREPHY != 0x01) + HWREG(SYSCTL_RCGCEPHY) = 1; + while (HWREG(SYSCTL_PREPHY) != 0x01) ; /* Enable power to PHY */ - SYSCTL->PCEPHY |= 1; - while (SYSCTL->PREPHY != 0x01) + HWREG(SYSCTL_PCEPHY) |= 1; + while (HWREG(SYSCTL_PREPHY) != 0x01) ; #if BOARD_PHY_RMII - ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28); + HWREG(EMAC0_BASE + EMAC_O_PC) = EMAC_PHY_CONFIG | (0x04 << 28); #else - ETH->PC = EMAC_PHY_CONFIG; + HWREG(EMAC0_BASE + EMAC_O_PC) = EMAC_PHY_CONFIG; #endif /* @@ -310,12 +310,12 @@ void mac_lld_init(void) /* Set done bit after writing EMACPC register */ mii_write(ÐD1, TIVA_CFG1, (1 << 15) | mii_read(ÐD1, TIVA_CFG1)); - while(ETH->DMABUSMOD & 1) + while(HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & 1) ; /* Reset MAC */ - ETH->DMABUSMOD |= 1; - while (ETH->DMABUSMOD & 1) + HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) |= 1; + while (HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) & 1) ; /* PHY address setup.*/ @@ -344,10 +344,10 @@ void mac_lld_init(void) #endif /* Disable MAC clock */ - SYSCTL->RCGCEMAC = 0; + HWREG(SYSCTL_RCGCEMAC) = 0; /* Disable PHY clock */ - SYSCTL->RCGCEPHY = 0; + HWREG(SYSCTL_RCGCEPHY) = 0; } /** @@ -374,13 +374,13 @@ void mac_lld_start(MACDriver *macp) macp->txptr = (tiva_eth_tx_descriptor_t *)td; /* Enable MAC clock */ - SYSCTL->RCGCEMAC = 1; - while (SYSCTL->PREMAC != 0x01) + HWREG(SYSCTL_RCGCEMAC) = 1; + while (HWREG(SYSCTL_PREMAC) != 0x01) ; /* Enable PHY clock */ - SYSCTL->RCGCEPHY = 1; - while (!SYSCTL->PREPHY) + HWREG(SYSCTL_RCGCEPHY) = 1; + while (!HWREG(SYSCTL_PREPHY)) ; /* ISR vector enabled.*/ @@ -392,9 +392,9 @@ void mac_lld_start(MACDriver *macp) #endif /* MAC configuration.*/ - ETH->FRAMEFLTR = 0; - ETH->FLOWCTL = 0; - ETH->VLANTG = 0; + HWREG(EMAC0_BASE + EMAC_O_FRAMEFLTR) = 0; + HWREG(EMAC0_BASE + EMAC_O_FLOWCTL) = 0; + HWREG(EMAC0_BASE + EMAC_O_VLANTG) = 0; /* MAC address setup.*/ if (macp->config->mac_address == NULL) @@ -406,30 +406,30 @@ void mac_lld_start(MACDriver *macp) Note that the complete setup of the MAC is performed when the link status is detected.*/ #if TIVA_MAC_IP_CHECKSUM_OFFLOAD - ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2); + HWREG(EMAC0_BASE + EMAC_O_CFG) = (1 << 10) | (1 << 3) | (1 << 2); #else - ETH->CFG = (1 << 3) | (1 << 2); + HWREG(EMAC0_BASE + EMAC_O_CFG) = (1 << 3) | (1 << 2); #endif /* DMA configuration: Descriptor chains pointers.*/ - ETH->RXDLADDR = (uint32_t)rd; - ETH->TXDLADDR = (uint32_t)td; + HWREG(EMAC0_BASE + EMAC_O_RXDLADDR) = (uint32_t)rd; + HWREG(EMAC0_BASE + EMAC_O_TXDLADDR) = (uint32_t)td; /* Enabling required interrupt sources.*/ - ETH->DMARIS &= 0xFFFF; - ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0); + HWREG(EMAC0_BASE + EMAC_O_DMARIS) &= 0xFFFF; + HWREG(EMAC0_BASE + EMAC_O_DMAIM) = (1 << 16) | (1 << 6) | (1 << 0); /* DMA general settings.*/ - ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8); + HWREG(EMAC0_BASE + EMAC_O_DMABUSMOD) = (1 << 25) | (1 << 17) | (1 << 8); /* Transmit FIFO flush.*/ - ETH->DMAOPMODE = (1 << 20); - while (ETH->DMAOPMODE & (1 << 20)) + HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = (1 << 20); + while (HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) & (1 << 20)) ; /* DMA final configuration and start.*/ - ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) | + HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = (1 << 26) | (1 << 25) | (1 << 21) | (1 << 13) | (1 << 1); } @@ -449,16 +449,16 @@ void mac_lld_stop(MACDriver *macp) #endif /* MAC and DMA stopped.*/ - ETH->CFG = 0; - ETH->DMAOPMODE = 0; - ETH->DMAIM = 0; - ETH->DMARIS &= 0xFFFF; + HWREG(EMAC0_BASE + EMAC_O_CFG) = 0; + HWREG(EMAC0_BASE + EMAC_O_DMAOPMODE) = 0; + HWREG(EMAC0_BASE + EMAC_O_DMAIM) = 0; + HWREG(EMAC0_BASE + EMAC_O_DMARIS) &= 0xFFFF; /* MAC clocks stopped.*/ - SYSCTL->RCGCEMAC = 0; + HWREG(SYSCTL_RCGCEMAC) = 0; /* PHY clock stopped.*/ - SYSCTL->RCGCEPHY = 0; + HWREG(SYSCTL_RCGCEPHY) = 0; /* ISR vector disabled.*/ nvicDisableVector(TIVA_MAC_NUMBER); @@ -537,9 +537,9 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) tdp->physdesc->locked = 0; /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) { - ETH->DMARIS = (1 << 2); - ETH->TXPOLLD = 1; /* Any value is OK.*/ + if ((HWREG(EMAC0_BASE + EMAC_O_DMARIS) & (0x7 << 20)) == (6 << 20)) { + HWREG(EMAC0_BASE + EMAC_O_DMARIS) = (1 << 2); + HWREG(EMAC0_BASE + EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/ } osalSysUnlock(); @@ -616,9 +616,9 @@ void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) rdp->physdesc->rdes0 = TIVA_RDES0_OWN; /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) { - ETH->DMARIS = (1 << 7); - ETH->TXPOLLD = 1; /* Any value is OK.*/ + if ((HWREG(EMAC0_BASE + EMAC_O_STATUS) & (0xf << 17)) == (4 << 17)) { + HWREG(EMAC0_BASE + EMAC_O_DMARIS) = (1 << 7); + HWREG(EMAC0_BASE + EMAC_O_TXPOLLD) = 1; /* Any value is OK.*/ } osalSysUnlock(); @@ -638,7 +638,7 @@ bool mac_lld_poll_link_status(MACDriver *macp) { uint32_t maccfg, bmsr, bmcr; - maccfg = ETH->CFG; + maccfg = HWREG(EMAC0_BASE + EMAC_O_CFG); /* PHY CR and SR registers read.*/ (void)mii_read(macp, MII_BMSR); @@ -688,7 +688,7 @@ bool mac_lld_poll_link_status(MACDriver *macp) } /* Changes the mode in the MAC.*/ - ETH->CFG = maccfg; + HWREG(EMAC0_BASE + EMAC_O_CFG) = maccfg; /* Returns the link status.*/ return macp->link_up = true; diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.h b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h index 98036bb..407bf6c 100644 --- a/os/hal/ports/TIVA/LLD/hal_mac_lld.h +++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/mac_lld.h + * @file MAC/hal_mac_lld.h * @brief MAC Driver subsystem low level driver header. * * @addtogroup MAC diff --git a/os/hal/ports/TIVA/LLD/PWM/driver.mk b/os/hal/ports/TIVA/LLD/PWM/driver.mk new file mode 100644 index 0000000..0c82d6f --- /dev/null +++ b/os/hal/ports/TIVA/LLD/PWM/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PWM TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/PWM diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c index b223a9c..6f4535c 100644 --- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c +++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/LLD/pwm_lld.c + * @file PWM/hal_pwm_lld.c * @brief TM4C123x/TM4C129x PWM subsystem low level driver. * * @addtogroup PWM @@ -30,13 +30,6 @@ /* Driver local definitions. */ /*===========================================================================*/ -#define PWM_INT_CMPBD (1 << 5) -#define PWM_INT_CMPBU (1 << 4) -#define PWM_INT_CMPAD (1 << 3) -#define PWM_INT_CMPAU (1 << 2) -#define PWM_INT_CNTLOAD (1 << 1) -#define PWM_INT_CNTZERO (1 << 0) - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -59,6 +52,8 @@ PWMDriver PWMD2; /* Driver local variables and types. */ /*===========================================================================*/ +static uint32_t pwm_generator_offsets[] = { PWM_GEN_0_OFFSET, PWM_GEN_1_OFFSET, PWM_GEN_2_OFFSET, PWM_GEN_3_OFFSET}; + /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ @@ -75,35 +70,36 @@ PWMDriver PWMD2; static void pwm_lld_serve_generator_interrupt (PWMDriver *pwmp, uint8_t i) { uint32_t isc; + uint32_t pwm = pwmp->pwm; - isc = pwmp->pwm->PWM[i].ISC; - pwmp->pwm->PWM[i].ISC = isc; + isc = HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC) = isc; - if (((isc & PWM_INT_CMPAD) != 0) && + if (((isc & PWM_X_ISC_INTCMPAD) != 0) && (pwmp->config->channels[i * 2 + 0].callback != NULL)) { pwmp->config->channels[i * 2 + 0].callback(pwmp); } - if (((isc & PWM_INT_CMPAU) != 0) && + if (((isc & PWM_X_ISC_INTCMPAU) != 0) && (pwmp->config->channels[i * 2 + 0].callback != NULL)) { pwmp->config->channels[i * 2 + 0].callback(pwmp); } - if (((isc & PWM_INT_CMPBD) != 0) && + if (((isc & PWM_X_ISC_INTCMPBD) != 0) && (pwmp->config->channels[i * 2 + 1].callback != NULL)) { pwmp->config->channels[i * 2 + 1].callback(pwmp); } - if (((isc & PWM_INT_CMPBU) != 0) && + if (((isc & PWM_X_ISC_INTCMPBU) != 0) && (pwmp->config->channels[i * 2 + 1].callback != NULL)) { pwmp->config->channels[i * 2 + 1].callback(pwmp); } - if (((isc & PWM_INT_CNTLOAD) != 0) && (pwmp->config->callback != NULL)) { + if (((isc & PWM_X_ISC_INTCNTLOAD) != 0) && (pwmp->config->callback != NULL)) { pwmp->config->callback(pwmp); } - if (((isc & PWM_INT_CNTZERO) != 0) && (pwmp->config->callback != NULL)) { + if (((isc & PWM_X_ISC_INTCNTZERO) != 0) && (pwmp->config->callback != NULL)) { pwmp->config->callback(pwmp); } } @@ -311,13 +307,13 @@ void pwm_lld_init(void) #if TIVA_PWM_USE_PWM0 pwmObjectInit(&PWMD1); PWMD1.channels = PWM_CHANNELS; - PWMD1.pwm = PWM0; + PWMD1.pwm = PWM0_BASE; #endif #if TIVA_PWM_USE_PWM1 pwmObjectInit(&PWMD2); PWMD2.channels = PWM_CHANNELS; - PWMD2.pwm = PWM1; + PWMD2.pwm = PWM1_BASE; #endif } @@ -335,12 +331,17 @@ void pwm_lld_start(PWMDriver *pwmp) uint8_t i; uint32_t invert = 0; uint32_t enable = 0; + uint32_t pwm = pwmp->pwm; if (pwmp->state == PWM_STOP) { /* Clock activation.*/ #if TIVA_PWM_USE_PWM0 if (&PWMD1 == pwmp) { - SYSCTL->RCGCPWM |= (1 << 0); + HWREG(SYSCTL_RCGCPWM) |= (1 << 0); + + while (!(HWREG(SYSCTL_PRPWM) & (1 << 0))) + ; + nvicEnableVector(TIVA_PWM0FAULT_NUMBER, TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY); nvicEnableVector(TIVA_PWM0GEN0_NUMBER, TIVA_PWM_PWM0_0_IRQ_PRIORITY); @@ -352,7 +353,11 @@ void pwm_lld_start(PWMDriver *pwmp) #if TIVA_PWM_USE_PWM1 if (&PWMD2 == pwmp) { - SYSCTL->RCGCPWM |= (1 << 1); + HWREG(SYSCTL_RCGCPWM) |= (1 << 1); + + while (!(HWREG(SYSCTL_PRPWM) & (1 << 1))) + ; + nvicEnableVector(TIVA_PWM1FAULT_NUMBER, TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY); nvicEnableVector(TIVA_PWM1GEN0_NUMBER, TIVA_PWM_PWM1_0_IRQ_PRIORITY); @@ -364,20 +369,20 @@ void pwm_lld_start(PWMDriver *pwmp) } else { /* Driver re-configuration scenario, it must be stopped first.*/ - pwmp->pwm->PWM[0].CTL = 0; - pwmp->pwm->PWM[1].CTL = 0; - pwmp->pwm->PWM[2].CTL = 0; - pwmp->pwm->PWM[3].CTL = 0; + HWREG(pwm + PWM_O_0_CTL) = 0; + HWREG(pwm + PWM_O_1_CTL) = 0; + HWREG(pwm + PWM_O_2_CTL) = 0; + HWREG(pwm + PWM_O_3_CTL) = 0; } /* Timer configuration.*/ for (i = 0; i < (PWM_CHANNELS >> 1); i++) { - pwmp->pwm->PWM[i].CTL = 0; - pwmp->pwm->PWM[i].GEN[0] = 0x08C; - pwmp->pwm->PWM[i].GEN[1] = 0x80C; - pwmp->pwm->PWM[i].LOAD = (uint16_t)(pwmp->config->frequency - 1); - pwmp->pwm->PWM[i].CMP[0] = (uint16_t)(pwmp->period - 1); - pwmp->pwm->PWM[i].CMP[1] = (uint16_t)(pwmp->period - 1); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CTL) = 0; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_GENA) = 0x08C; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_GENB) = 0x80C; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_LOAD) = (uint16_t)(pwmp->config->frequency - 1); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CMPA) = (uint16_t)(pwmp->period - 1); + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_CMPB) = (uint16_t)(pwmp->period - 1); } /* Output enables and polarities setup.*/ @@ -399,9 +404,9 @@ void pwm_lld_start(PWMDriver *pwmp) } } - pwmp->pwm->INVERT = invert; - pwmp->pwm->ENABLE = enable; - pwmp->pwm->ISC = 0xFFFFFFFF; + HWREG(pwm + PWM_O_INVERT) = invert; + HWREG(pwm + PWM_O_ENABLE) = enable; + HWREG(pwm + PWM_O_ISC) = 0xFFFFFFFF; } /** @@ -413,12 +418,14 @@ void pwm_lld_start(PWMDriver *pwmp) */ void pwm_lld_stop(PWMDriver *pwmp) { + uint32_t pwm = pwmp->pwm; + /* If in ready state then disables the PWM clock.*/ if (pwmp->state == PWM_READY) { - pwmp->pwm->PWM[0].CTL = 0; - pwmp->pwm->PWM[1].CTL = 0; - pwmp->pwm->PWM[2].CTL = 0; - pwmp->pwm->PWM[3].CTL = 0; + HWREG(pwm + PWM_O_0_CTL) = 0; + HWREG(pwm + PWM_O_1_CTL) = 0; + HWREG(pwm + PWM_O_2_CTL) = 0; + HWREG(pwm + PWM_O_3_CTL) = 0; #if TIVA_PWM_USE_PWM0 if (&PWMD1 == pwmp) { @@ -427,7 +434,7 @@ void pwm_lld_stop(PWMDriver *pwmp) nvicDisableVector(TIVA_PWM0GEN1_NUMBER); nvicDisableVector(TIVA_PWM0GEN2_NUMBER); nvicDisableVector(TIVA_PWM0GEN3_NUMBER); - SYSCTL->RCGCPWM &= ~(1 << 0); + HWREG(SYSCTL_RCGCPWM) &= ~(1 << 0); } #endif @@ -438,7 +445,7 @@ void pwm_lld_stop(PWMDriver *pwmp) nvicDisableVector(TIVA_PWM1GEN1_NUMBER); nvicDisableVector(TIVA_PWM1GEN2_NUMBER); nvicDisableVector(TIVA_PWM1GEN3_NUMBER); - SYSCTL->RCGCPWM &= ~(1 << 1); + HWREG(SYSCTL_RCGCPWM) &= ~(1 << 1); } #endif } @@ -461,9 +468,16 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, pwmchannel_t channel, pwmcnt_t width) { + uint32_t pwm = pwmp->pwm; + /* Changing channel duty cycle on the fly.*/ - pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = width; - pwmp->pwm->PWM[channel >> 1].CTL |= (1 << 0); + if (channel & 1) + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPB) = width; + else + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPA) = width; + + + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CTL) = (1 << 0); } /** @@ -480,8 +494,14 @@ void pwm_lld_enable_channel(PWMDriver *pwmp, */ void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) { - pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = 0; - pwmp->pwm->PWM[channel >> 1].CTL &= ~(1 << 0); + uint32_t pwm = pwmp->pwm; + + if (channel & 1) + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPB) = 0; + else + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CMPA) = 0; + + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_CTL) = (1 << 0); } /** @@ -497,18 +517,19 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) { uint32_t inten; uint8_t i; + uint32_t pwm = pwmp->pwm; /* If the IRQ is not already enabled care must be taken to clear it, it is probably already pending because the timer is running.*/ for(i = 0; i < (PWM_CHANNELS >> 1); i++) { - inten = pwmp->pwm->PWM[i].INTEN; + inten = HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_INTEN); if ((inten & 0x03) == 0) { - pwmp->pwm->PWM[i].INTEN |= 0x03; - pwmp->pwm->PWM[i].ISC = 0x03; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_INTEN) |= 0x03; + HWREG(pwm + pwm_generator_offsets[i] + PWM_O_X_ISC) = 0x03; } } - pwmp->pwm->INTEN = 0x3f; + HWREG(pwm + PWM_O_INTEN) = 0x3f; } /** @@ -522,11 +543,14 @@ void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) */ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) { - pwmp->pwm->PWM[0].INTEN &= ~(0x03); - pwmp->pwm->PWM[1].INTEN &= ~(0x03); - pwmp->pwm->PWM[2].INTEN &= ~(0x03); - pwmp->pwm->PWM[3].INTEN &= ~(0x03); - pwmp->pwm->INTEN &= ~(0x3F); + uint32_t pwm = pwmp->pwm; + + HWREG(pwm + PWM_O_0_INTEN) = ~(0x03); + HWREG(pwm + PWM_O_1_INTEN) = ~(0x03); + HWREG(pwm + PWM_O_2_INTEN) = ~(0x03); + HWREG(pwm + PWM_O_3_INTEN) = ~(0x03); + + HWREG(pwm + PWM_O_INTEN) &= ~(0x3F); } /** @@ -543,13 +567,14 @@ void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) void pwm_lld_enable_channel_notification(PWMDriver *pwmp, pwmchannel_t channel) { - uint32_t inten = pwmp->pwm->PWM[channel >> 1].INTEN; + uint32_t pwm = pwmp->pwm; + uint32_t inten = HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_ISC); /* If the IRQ is not already enabled care must be taken to clear it, it is probably already pending because the timer is running.*/ if ((inten & (0x03 << (((channel & 1) * 2) + 2))) == 0) { - pwmp->pwm->PWM[channel >> 1].INTEN |= (0x03 << (((channel & 1) * 2) + 2)); - pwmp->pwm->PWM[channel >> 1].ISC = (0x03 << (((channel & 1) * 2) + 2)); + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_INTEN) |= (0x03 << (((channel & 1) * 2) + 2)); + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_ISC) = (0x03 << (((channel & 1) * 2) + 2)); } } @@ -567,7 +592,9 @@ void pwm_lld_enable_channel_notification(PWMDriver *pwmp, void pwm_lld_disable_channel_notification(PWMDriver *pwmp, pwmchannel_t channel) { - pwmp->pwm->PWM[channel >> 1].INTEN &= ~(0x03 << (((channel & 1) * 2) + 2)); + uint32_t pwm = pwmp->pwm; + + HWREG(pwm + pwm_generator_offsets[channel >> 1] + PWM_O_X_INTEN) = ~(0x03 << (((channel & 1) * 2) + 2)); } #endif /* HAL_USE_PWM */ diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h index ac64fe1..3fca631 100644 --- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h +++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/LLD/pwm_lld.c + * @file PWM/hal_pwm_lld.c * @brief TM4C123x/TM4C129x PWM subsystem low level driver header. * * @addtogroup PWM @@ -304,7 +304,7 @@ struct PWMDriver { /** * @brief Pointer to the PWMx registers block. */ - PWM_TypeDef *pwm; + uint32_t pwm; }; /*===========================================================================*/ @@ -328,10 +328,10 @@ struct PWMDriver { * @notapi */ #define pwm_lld_change_period(pwmp, period) \ - ((pwmp)->pwm->PWM[0].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[1].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[2].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[3].LOAD = (uint16_t)((period) - 1)) + HWREG((pwmp)->pwm + PWM_O_0_LOAD) = (uint16_t)((period) - 1); \ + HWREG((pwmp)->pwm + PWM_O_1_LOAD) = (uint16_t)((period) - 1); \ + HWREG((pwmp)->pwm + PWM_O_2_LOAD) = (uint16_t)((period) - 1); \ + HWREG((pwmp)->pwm + PWM_O_3_LOAD) = (uint16_t)((period) - 1) /*===========================================================================*/ /* External declarations. */ diff --git a/os/hal/ports/TIVA/LLD/SSI/driver.mk b/os/hal/ports/TIVA/LLD/SSI/driver.mk new file mode 100644 index 0000000..6f71487 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/SSI/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c index ded2b99..2255110 100644 --- a/os/hal/ports/TIVA/LLD/hal_spi_lld.c +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/LLD/spi_lld.c + * @file SSI/hal_spi_lld.c * @brief TM4C123x/TM4C129x SPI subsystem low level driver. * * @addtogroup SPI @@ -77,19 +77,19 @@ static uint16_t dummyrx; */ static void spi_serve_interrupt(SPIDriver *spip) { - SSI_TypeDef *ssi = spip->ssi; - uint32_t mis = ssi->MIS; - uint32_t dmachis = UDMA->CHIS; + uint32_t ssi = spip->ssi; + uint32_t mis = HWREG(ssi + SSI_O_MIS); + uint32_t dmachis = HWREG(UDMA_CHIS); /* SPI error handling.*/ - if ((mis & (TIVA_MIS_RORMIS | TIVA_MIS_RTMIS)) != 0) { + if ((mis & (SSI_MIS_RORMIS | SSI_MIS_RTMIS)) != 0) { TIVA_SPI_SSI_ERROR_HOOK(spip); } - if ( (dmachis & ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) == - ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) { + if ((dmachis & ((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) == + (uint32_t)((1 << spip->dmarxnr) | (1 << spip->dmatxnr))) { /* Clear DMA Channel interrupts.*/ - UDMA->CHIS = (1 << spip->dmarxnr) | (1 << spip->dmatxnr); + HWREG(UDMA_CHIS) = (1 << spip->dmarxnr) | (1 << spip->dmatxnr); /* Portable SPI ISR code defined in the high level driver, note, it is a macro.*/ @@ -180,7 +180,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI0 spiObjectInit(&SPID1); - SPID1.ssi = SSI0; + SPID1.ssi = SSI0_BASE; SPID1.dmarxnr = TIVA_SPI_SSI0_RX_UDMA_CHANNEL; SPID1.dmatxnr = TIVA_SPI_SSI0_TX_UDMA_CHANNEL; SPID1.rxchnmap = TIVA_SPI_SSI0_RX_UDMA_MAPPING; @@ -189,7 +189,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI1 spiObjectInit(&SPID2); - SPID2.ssi = SSI1; + SPID2.ssi = SSI1_BASE; SPID2.dmarxnr = TIVA_SPI_SSI1_RX_UDMA_CHANNEL; SPID2.dmatxnr = TIVA_SPI_SSI1_TX_UDMA_CHANNEL; SPID2.rxchnmap = TIVA_SPI_SSI1_RX_UDMA_MAPPING; @@ -198,7 +198,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI2 spiObjectInit(&SPID3); - SPID3.ssi = SSI2; + SPID3.ssi = SSI2_BASE; SPID3.dmarxnr = TIVA_SPI_SSI2_RX_UDMA_CHANNEL; SPID3.dmatxnr = TIVA_SPI_SSI2_TX_UDMA_CHANNEL; SPID3.rxchnmap = TIVA_SPI_SSI2_RX_UDMA_MAPPING; @@ -207,7 +207,7 @@ void spi_lld_init(void) #if TIVA_SPI_USE_SSI3 spiObjectInit(&SPID4); - SPID4.ssi = SSI3; + SPID4.ssi = SSI3_BASE; SPID4.dmarxnr = TIVA_SPI_SSI3_RX_UDMA_CHANNEL; SPID4.dmatxnr = TIVA_SPI_SSI3_TX_UDMA_CHANNEL; SPID4.rxchnmap = TIVA_SPI_SSI3_RX_UDMA_MAPPING; @@ -235,8 +235,8 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 0); - while (!(SYSCTL->PRSSI & (1 << 0))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 0); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 0))) ; nvicEnableVector(TIVA_SSI0_NUMBER, TIVA_SPI_SSI0_IRQ_PRIORITY); @@ -251,14 +251,14 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 1); - while (!(SYSCTL->PRSSI & (1 << 1))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 1); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 1))) ; nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY); } #endif -#if TIVASPI_USE_SSI2 +#if TIVA_SPI_USE_SSI2 if (&SPID2 == spip) { bool b; b = udmaChannelAllocate(spip->dmarxnr); @@ -267,8 +267,8 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 2); - while (!(SYSCTL->PRSSI & (1 << 2))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 2); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 2))) ; nvicEnableVector(TIVA_SSI2_NUMBER, TIVA_SPI_SSI2_IRQ_PRIORITY); @@ -283,40 +283,40 @@ void spi_lld_start(SPIDriver *spip) osalDbgAssert(!b, "channel already allocated"); /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 3); - while (!(SYSCTL->PRSSI & (1 << 3))) + HWREG(SYSCTL_RCGCSSI) |= (1 << 3); + while (!(HWREG(SYSCTL_PRSSI) & (1 << 3))) ; nvicEnableVector(TIVA_SSI3_NUMBER, TIVA_SPI_SSI3_IRQ_PRIORITY); } #endif - UDMA->CHMAP[spip->dmarxnr / 8] |= (spip->rxchnmap << (spip->dmarxnr % 8)); - UDMA->CHMAP[spip->dmatxnr / 8] |= (spip->txchnmap << (spip->dmatxnr % 8)); + HWREG(UDMA_CHMAP0 + (spip->dmarxnr / 8) * 4) |= (spip->rxchnmap << (spip->dmarxnr % 8)); + HWREG(UDMA_CHMAP0 + (spip->dmatxnr / 8) * 4) |= (spip->txchnmap << (spip->dmatxnr % 8)); } /* Set master operation mode.*/ - spip->ssi->CR1 = 0; + HWREG(spip->ssi + SSI_O_CR1) = 0; /* Clock configuration - System Clock.*/ - spip->ssi->CC = 0; + HWREG(spip->ssi + SSI_O_CC) = 0; /* Clear pending interrupts.*/ - spip->ssi->ICR = TIVA_ICR_RTIC | TIVA_ICR_RORIC; + HWREG(spip->ssi + SSI_O_ICR) = SSI_ICR_RTIC | SSI_ICR_RORIC; /* Enable Receive Time-Out and Receive Overrun Interrupts.*/ - spip->ssi->IM = TIVA_IM_RTIM | TIVA_IM_RORIM; + HWREG(spip->ssi + SSI_O_IM) = SSI_IM_RTIM | SSI_IM_RORIM; /* Configure the clock prescale divisor.*/ - spip->ssi->CPSR = spip->config->cpsr; + HWREG(spip->ssi + SSI_O_CPSR) = spip->config->cpsr; /* Serial clock rate, phase/polarity, data size, fixed SPI frame format.*/ - spip->ssi->CR0 = (spip->config->cr0 & ~TIVA_CR0_FRF_MASK) | TIVA_CR0_FRF(0); + HWREG(spip->ssi + SSI_O_CR0) = (spip->config->cr0 & ~SSI_CR0_FRF_M) | SSI_CR0_FRF_MOTO; /* Enable SSI.*/ - spip->ssi->CR1 |= TIVA_CR1_SSE; + HWREG(spip->ssi + SSI_O_CR1) |= SSI_CR1_SSE; /* Enable RX and TX DMA channels.*/ - spip->ssi->DMACTL = (TIVA_DMACTL_TXDMAE | TIVA_DMACTL_RXDMAE); + HWREG(spip->ssi + SSI_O_DMACTL) = (SSI_DMACTL_TXDMAE | SSI_DMACTL_RXDMAE); } /** @@ -329,9 +329,9 @@ void spi_lld_start(SPIDriver *spip) void spi_lld_stop(SPIDriver *spip) { if (spip->state != SPI_STOP) { - spip->ssi->CR1 = 0; - spip->ssi->CR0 = 0; - spip->ssi->CPSR = 0; + HWREG(spip->ssi + SSI_O_CR1) = 0; + HWREG(spip->ssi + SSI_O_CR0) = 0; + HWREG(spip->ssi + SSI_O_CPSR) = 0; udmaChannelRelease(spip->dmarxnr); udmaChannelRelease(spip->dmatxnr); @@ -359,6 +359,7 @@ void spi_lld_stop(SPIDriver *spip) } } +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) /** * @brief Asserts the slave select signal and prepares for transfers. * @@ -368,7 +369,7 @@ void spi_lld_stop(SPIDriver *spip) */ void spi_lld_select(SPIDriver *spip) { - palClearPad(spip->config->ssport, spip->config->sspad); + /* No implementation on Tiva.*/ } /** @@ -381,8 +382,9 @@ void spi_lld_select(SPIDriver *spip) */ void spi_lld_unselect(SPIDriver *spip) { - palSetPad(spip->config->ssport, spip->config->sspad); + /* No implementation on Tiva.*/ } +#endif /** * @brief Ignores data on the SPI bus. @@ -399,20 +401,20 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -420,17 +422,17 @@ void spi_lld_ignore(SPIDriver *spip, size_t n) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -470,20 +472,20 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+n-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -491,17 +493,17 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -539,20 +541,20 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].dstendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -560,17 +562,17 @@ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].dstendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -608,20 +610,20 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { tiva_udma_table_entry_t *primary = udmaControlTable.primary; - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + if ((spip->config->cr0 & SSI_CR0_DSS_M) < 8) { /* Configure for 8-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+n-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -629,17 +631,17 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) else { /* Configure for 16-bit transfers.*/ primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + primary[spip->dmatxnr].dstendp = (void *)(spip->ssi + SSI_O_DR); + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = (void *)(spip->ssi + SSI_O_DR); primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_NONE | UDMA_CHCTL_ARBSIZE_4 | UDMA_CHCTL_XFERSIZE(n) | UDMA_CHCTL_XFERMODE_BASIC; @@ -674,10 +676,10 @@ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) */ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - spip->ssi->DR = (uint32_t)frame; - while ((spip->ssi->SR & TIVA_SR_RNE) == 0) + HWREG(spip->ssi + SSI_O_DR) = (uint32_t)frame; + while ((HWREG(spip->ssi + SSI_O_SR) & SSI_SR_RNE) == 0) ; - return (uint16_t)spip->ssi->DR; + return (uint16_t)HWREG(spip->ssi + SSI_O_DR); } #endif /* HAL_USE_SPI */ diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h index 2adc9ed..c93c189 100644 --- a/os/hal/ports/TIVA/LLD/hal_spi_lld.h +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/LLD/spi_lld.h + * @file SSI/hal_spi_lld.h * @brief TM4C123x/TM4C129x SPI subsystem low level driver. * * @addtogroup SPI @@ -32,89 +32,9 @@ /*===========================================================================*/ /** - * @name Control 0 - * @{ - */ -#define TIVA_CR0_DSS_MASK 0x0F -#define TIVA_CR0_DSS(n) ((n-1) << 0) - -#define TIVA_CR0_FRF_MASK (3 << 4) -#define TIVA_CR0_FRF(n) ((n) << 4) - -#define TIVA_CR0_SPO (1 << 6) -#define TIVA_CR0_SPH (1 << 7) - -#define TIVA_CR0_SRC_MASK (0xFF << 8) -#define TIVA_CR0_SRC(n) ((n) << 8) -/** @} */ - -/** - * @name Control 1 - * @{ - */ -#define TIVA_CR1_LBM (1 << 0) -#define TIVA_CR1_SSE (1 << 1) -#define TIVA_CR1_MS (1 << 2) -#define TIVA_CR1_SOD (1 << 3) -#define TIVA_CR1_EOT (1 << 4) -/** @} */ - -/** - * @name Status - * @{ - */ -#define TIVA_SR_TFE (1 << 0) -#define TIVA_SR_TNF (1 << 1) -#define TIVA_SR_RNE (1 << 2) -#define TIVA_SR_RFF (1 << 3) -#define TIVA_SR_BSY (1 << 4) -/** @} */ - -/** - * @name Interrupt Mask - * @{ - */ -#define TIVA_IM_RORIM (1 << 0) -#define TIVA_IM_RTIM (1 << 1) -#define TIVA_IM_RXIM (1 << 2) -#define TIVA_IM_TXIM (1 << 3) -/** @} */ - -/** - * @name Interrupt Status - * @{ - */ -#define TIVA_IS_RORIS (1 << 0) -#define TIVA_IS_RTIS (1 << 1) -#define TIVA_IS_RXIS (1 << 2) -#define TIVA_IS_TXIS (1 << 3) -/** @} */ - -/** - * @name Masked Interrupt Status - * @{ - */ -#define TIVA_MIS_RORMIS (1 << 0) -#define TIVA_MIS_RTMIS (1 << 1) -#define TIVA_MIS_RXMIS (1 << 2) -#define TIVA_MIS_TXMIS (1 << 3) -/** @} */ - -/** - * @name Interrupt Clear - * @{ + * @brief CR0 Serial Clock Rate helper. */ -#define TIVA_ICR_RORIC (1 << 0) -#define TIVA_ICR_RTIC (1 << 1) -/** @} */ - -/** - * @name DMA Control - * @{ - */ -#define TIVA_DMACTL_RXDMAE (1 << 0) -#define TIVA_DMACTL_TXDMAE (1 << 1) -/** @} */ +#define SSI_CR0_SCR(n) ((n) << 8) /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -236,7 +156,7 @@ #error "Invalid IRQ priority assigned to SSI2" #endif -#if TM4C123x_SPI_USE_SSI3 && \ +#if TIVA_SPI_USE_SSI3 && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI3" #endif @@ -245,6 +165,10 @@ #define TIVA_UDMA_REQUIRED #endif +#if SPI_SELECT_MODE == SPI_SELECT_MODE_LLD +#error "SPI_SELECT_MODE_LLD not supported by this driver" +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ @@ -269,16 +193,34 @@ typedef struct { /** * @brief Operation complete callback or @p NULL. */ - spicallback_t end_cb; - /* End of the mandatory fields.*/ + spicallback_t end_cb; +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LINE) || defined(__DOXYGEN__) /** - * @brief The chip select line port. + * @brief The chip select line. */ - ioportid_t ssport; + ioline_t ssline; +#endif +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_PORT) || defined(__DOXYGEN__) /** - * @brief The chip select line pad number. + * @brief The chip select port. */ - uint16_t sspad; + ioportid_t ssport; + /** + * @brief The chip select port mask. + */ + uint8fast_t ssmask; +#endif +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_PAD) || defined(__DOXYGEN__) + /** + * @brief The chip select port. + */ + ioportid_t ssport; + /** + * @brief The chip select pad number. + */ + uint_fast8_t sspad; +#endif + /* End of the mandatory fields.*/ /** * @brief SSI CR0 initialization data. */ @@ -320,7 +262,7 @@ struct SPIDriver { /** * @brief Pointer to the SSI registers block. */ - SSI_TypeDef *ssi; + uint32_t ssi; /** * @brief Receive DMA channel number. */ @@ -369,8 +311,10 @@ extern "C" { void spi_lld_init(void); void spi_lld_start(SPIDriver *spip); void spi_lld_stop(SPIDriver *spip); +#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__) void spi_lld_select(SPIDriver *spip); void spi_lld_unselect(SPIDriver *spip); +#endif void spi_lld_ignore(SPIDriver *spip, size_t n); void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf); diff --git a/os/hal/ports/TIVA/LLD/UART/driver.mk b/os/hal/ports/TIVA/LLD/UART/driver.mk new file mode 100644 index 0000000..e42f34a --- /dev/null +++ b/os/hal/ports/TIVA/LLD/UART/driver.mk @@ -0,0 +1,13 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c +endif +ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c index bd1b81e..f1bda8d 100644 --- a/os/hal/ports/TIVA/LLD/hal_serial_lld.c +++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/LLD/serial_lld.c + * @file UART/hal_serial_lld.c * @brief Tiva low level serial driver code. * * @addtogroup SERIAL @@ -34,58 +34,42 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** - * @brief UART0 serial driver identifier. - */ +/** @brief UART0 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) SerialDriver SD1; #endif -/** - * @brief UART1 serial driver identifier. - */ +/** @brief UART1 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) SerialDriver SD2; #endif -/** - * @brief UART2 serial driver identifier. - */ +/** @brief UART2 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) SerialDriver SD3; #endif -/** - * @brief UART3 serial driver identifier. - */ +/** @brief UART3 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) SerialDriver SD4; #endif -/** - * @brief UART4 serial driver identifier. - */ +/** @brief UART4 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) SerialDriver SD5; #endif -/** - * @brief UART5 serial driver identifier. - */ +/** @brief UART5 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) SerialDriver SD6; #endif -/** - * @brief UART6 serial driver identifier. - */ +/** @brief UART6 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) SerialDriver SD7; #endif -/** - * @brief UART7 serial driver identifier. - */ +/** @brief UART7 serial driver identifier.*/ #if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) SerialDriver SD8; #endif @@ -94,16 +78,80 @@ SerialDriver SD8; /* Driver local variables. */ /*===========================================================================*/ -/** - * @brief Driver default configuration. - */ +/** @brief Driver default configuration.*/ static const SerialConfig sd_default_config = { SERIAL_DEFAULT_BITRATE, - TIVA_LCRH_FEN | TIVA_LCRH_WLEN_8, - TIVA_IFLS_TXIFLSEL_1_8_F | TIVA_IFLS_RXIFLSEL_1_8_E + 0, + UART_LCRH_FEN | UART_LCRH_WLEN_8, + UART_IFLS_TX4_8 | UART_IFLS_RX7_8, + UART_CC_CS_SYSCLK }; +#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) +/** @brief Input buffer for SD1.*/ +static uint8_t sd_in_buf1[TIVA_SERIAL_UART0_IN_BUF_SIZE]; + +/** @brief Output buffer for SD1.*/ +static uint8_t sd_out_buf1[TIVA_SERIAL_UART0_OUT_BUF_SIZE]; +#endif + +#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) +/** @brief Input buffer for SD2.*/ +static uint8_t sd_in_buf2[TIVA_SERIAL_UART1_IN_BUF_SIZE]; + +/** @brief Output buffer for SD2.*/ +static uint8_t sd_out_buf2[TIVA_SERIAL_UART1_OUT_BUF_SIZE]; +#endif + +#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) +/** @brief Input buffer for SD3.*/ +static uint8_t sd_in_buf3[TIVA_SERIAL_UART2_IN_BUF_SIZE]; + +/** @brief Output buffer for SD3.*/ +static uint8_t sd_out_buf3[TIVA_SERIAL_UART2_OUT_BUF_SIZE]; +#endif + +#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) +/** @brief Input buffer for SD4.*/ +static uint8_t sd_in_buf4[TIVA_SERIAL_UART3_IN_BUF_SIZE]; + +/** @brief Output buffer for SD4.*/ +static uint8_t sd_out_buf4[TIVA_SERIAL_UART3_OUT_BUF_SIZE]; +#endif + +#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) +/** @brief Input buffer for SD5.*/ +static uint8_t sd_in_buf5[TIVA_SERIAL_UART4_IN_BUF_SIZE]; + +/** @brief Output buffer for SD5.*/ +static uint8_t sd_out_buf5[TIVA_SERIAL_UART4_OUT_BUF_SIZE]; +#endif + +#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) +/** @brief Input buffer for SD6.*/ +static uint8_t sd_in_buf6[TIVA_SERIAL_UART5_IN_BUF_SIZE]; + +/** @brief Output buffer for SD6.*/ +static uint8_t sd_out_buf6[TIVA_SERIAL_UART5_OUT_BUF_SIZE]; +#endif + +#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) +/** @brief Input buffer for SD7.*/ +static uint8_t sd_in_buf7[TIVA_SERIAL_UART6_IN_BUF_SIZE]; + +/** @brief Output buffer for SD7.*/ +static uint8_t sd_out_buf7[TIVA_SERIAL_UART6_OUT_BUF_SIZE]; +#endif + +#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) +/** @brief Input buffer for SD8.*/ +static uint8_t sd_in_buf8[TIVA_SERIAL_UART7_IN_BUF_SIZE]; + +/** @brief Output buffer for SD8.*/ +static uint8_t sd_out_buf8[TIVA_SERIAL_UART7_OUT_BUF_SIZE]; +#endif + /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ @@ -111,23 +159,55 @@ static const SerialConfig sd_default_config = /** * @brief UART initialization. * - * @param[in] sdp communication channel associated to the UART + * @param[in] sdp pointer to a @p SerialDriver object * @param[in] config the architecture-dependent serial driver configuration */ static void uart_init(SerialDriver *sdp, const SerialConfig *config) { - UART_TypeDef *u = sdp->uart; - uint32_t div; /* baud rate divisor */ - - /* disable the UART before any of the control registers are reprogrammed */ - u->CTL &= ~TIVA_CTL_UARTEN; - div = (((TIVA_SYSCLK * 8) / config->sc_speed) + 1) / 2; - u->IBRD = div / 64; /* integer portion of the baud rate divisor */ - u->FBRD = div % 64; /* fractional portion of the baud rate divisor */ - u->LCRH = config->sc_lcrh; /* set data format */ - u->IFLS = config->sc_ifls; - u->CTL |= TIVA_CTL_TXE | TIVA_CTL_RXE | TIVA_CTL_UARTEN; - u->IM |= TIVA_IM_RXIM | TIVA_IM_TXIM | TIVA_IM_RTIM; /* interrupts enable */ + uint32_t u = sdp->uart; + uint32_t brd; + uint32_t speed = config->speed; + uint32_t clock_source; + + if (config->ctl & UART_CTL_HSE) { + /* High speed mode is enabled, half the baud rate to compensate + * for high speed mode.*/ + speed = (speed + 1) / 2; + } + + if ((config->cc & UART_CC_CS_SYSCLK) == UART_CC_CS_SYSCLK) { + /* UART is clocked using the SYSCLK.*/ + clock_source = TIVA_SYSCLK * 8; + } + else { + /* UART is clocked using the PIOSC.*/ + clock_source = 16000000 * 8; + } + + /* Calculate the baud rate divisor */ + brd = ((clock_source / speed) + 1) / 2; + + /* Disable UART.*/ + HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN; + + /* Set baud rate.*/ + HWREG(u + UART_O_IBRD) = brd / 64; + HWREG(u + UART_O_FBRD) = brd % 64; + + /* Line control/*/ + HWREG(u + UART_O_LCRH) = config->lcrh; + + /* Select clock source.*/ + HWREG(u + UART_O_CC) = config->cc & UART_CC_CS_M; + + /* FIFO configuration.*/ + HWREG(u + UART_O_IFLS) = config->ifls & (UART_IFLS_RX_M | UART_IFLS_TX_M); + + /* Note that some bits are enforced.*/ + HWREG(u + UART_O_CTL) = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN; + + /* Enable interrupts.*/ + HWREG(u + UART_O_IM) = UART_IM_RXIM | UART_IM_TXIM | UART_IM_RTIM; } /** @@ -135,9 +215,9 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config) * * @param[in] u pointer to an UART I/O block */ -static void uart_deinit(UART_TypeDef *u) +static void uart_deinit(uint32_t u) { - u->CTL &= ~TIVA_CTL_UARTEN; + HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN; } /** @@ -150,13 +230,13 @@ static void set_error(SerialDriver *sdp, uint16_t err) { eventflags_t sts = 0; - if (err & TIVA_MIS_FEMIS) + if (err & UART_MIS_FEMIS) sts |= SD_FRAMING_ERROR; - if (err & TIVA_MIS_PEMIS) + if (err & UART_MIS_PEMIS) sts |= SD_PARITY_ERROR; - if (err & TIVA_MIS_BEMIS) + if (err & UART_MIS_BEMIS) sts |= SD_BREAK_DETECTED; - if (err & TIVA_MIS_OEMIS) + if (err & UART_MIS_OEMIS) sts |= SD_OVERRUN_ERROR; osalSysLockFromISR(); chnAddFlagsI(sdp, sts); @@ -174,64 +254,67 @@ static void set_error(SerialDriver *sdp, uint16_t err) */ static void serial_serve_interrupt(SerialDriver *sdp) { - UART_TypeDef *u = sdp->uart; - uint16_t mis = u->MIS; + uint32_t u = sdp->uart; + uint16_t mis = HWREG(u + UART_O_MIS); - u->ICR = mis; /* clear interrupts */ + HWREG(u + UART_O_ICR) = mis; /* clear interrupts */ - if (mis & (TIVA_MIS_FEMIS | TIVA_MIS_PEMIS | TIVA_MIS_BEMIS | TIVA_MIS_OEMIS)) { + if (mis & (UART_MIS_FEMIS | UART_MIS_PEMIS | UART_MIS_BEMIS | UART_MIS_OEMIS)) { set_error(sdp, mis); } - if ((mis & TIVA_MIS_RXMIS) || (mis & TIVA_MIS_RTMIS)) { + if ((mis & UART_MIS_RXMIS) || (mis & UART_MIS_RTMIS)) { osalSysLockFromISR(); if (iqIsEmptyI(&sdp->iqueue)) { chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); } osalSysUnlockFromISR(); - while ((u->FR & TIVA_FR_RXFE) == 0) { + while ((HWREG(u + UART_O_FR) & UART_FR_RXFE) == 0) { osalSysLockFromISR(); - if (iqPutI(&sdp->iqueue, u->DR) < Q_OK) { - chnAddFlagsI(sdp, SD_OVERRUN_ERROR); + if (iqPutI(&sdp->iqueue, HWREG(u + UART_O_DR)) < Q_OK) { + chnAddFlagsI(sdp, SD_QUEUE_FULL_ERROR); } osalSysUnlockFromISR(); } } - if (mis & TIVA_MIS_TXMIS) { - while ((u->FR & TIVA_FR_TXFF) == 0) { + if (mis & UART_MIS_TXMIS) { + while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) { msg_t b; osalSysLockFromISR(); b = oqGetI(&sdp->oqueue); osalSysUnlockFromISR(); if (b < Q_OK) { - u->IM &= ~TIVA_IM_TXIM; + HWREG(u + UART_O_IM) &= ~UART_IM_TXIM; osalSysLockFromISR(); chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); osalSysUnlockFromISR(); break; } - u->DR = b; + HWREG(u + UART_O_DR) = b; } } + + /* TODO: Physical transmission end. */ } /** - * @brief + * @brief Fill the hardware FIFO of a UART. */ static void fifo_load(SerialDriver *sdp) { - UART_TypeDef *u = sdp->uart; + uint32_t u = sdp->uart; - while ((u->FR & TIVA_FR_TXFF) == 0) { + while ((HWREG(u + UART_O_FR) & UART_FR_TXFF) == 0) { msg_t b = oqGetI(&sdp->oqueue); if (b < Q_OK) { chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); return; } - u->DR = b; + HWREG(u + UART_O_DR) = b; } - u->IM |= TIVA_IM_TXIM; /* transmit interrupt enable */ + + HWREG(u + UART_O_IM) |= UART_IM_TXIM; /* transmit interrupt enable */ } /** @@ -326,13 +409,15 @@ static void notify8(io_queue_t *qp) /* Driver interrupt handlers. */ /*===========================================================================*/ -/** - * @brief UART0 IRQ handler. - */ #if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) #if !defined(TIVA_UART0_HANDLER) #error "TIVA_UART0_HANDLER not defined" #endif +/** + * @brief UART0 interrupt handler. + * + * @isr + */ CH_IRQ_HANDLER(TIVA_UART0_HANDLER) { CH_IRQ_PROLOGUE(); @@ -343,10 +428,16 @@ CH_IRQ_HANDLER(TIVA_UART0_HANDLER) } #endif + +#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) +#if !defined(TIVA_UART1_HANDLER) +#error "TIVA_UART1_HANDLER not defined" +#endif /** - * @brief UART1 IRQ handler. + * @brief UART1 interrupt handler. + * + * @isr */ -#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) CH_IRQ_HANDLER(TIVA_UART1_HANDLER) { CH_IRQ_PROLOGUE(); @@ -357,10 +448,15 @@ CH_IRQ_HANDLER(TIVA_UART1_HANDLER) } #endif +#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) +#if !defined(TIVA_UART2_HANDLER) +#error "TIVA_UART2_HANDLER not defined" +#endif /** - * @brief UART2 IRQ handler. + * @brief UART2 interrupt handler. + * + * @isr */ -#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) CH_IRQ_HANDLER(TIVA_UART2_HANDLER) { CH_IRQ_PROLOGUE(); @@ -371,10 +467,15 @@ CH_IRQ_HANDLER(TIVA_UART2_HANDLER) } #endif +#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) +#if !defined(TIVA_UART3_HANDLER) +#error "TIVA_UART3_HANDLER not defined" +#endif /** - * @brief UART3 IRQ handler. + * @brief UART3 interrupt handler. + * + * @isr */ -#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) CH_IRQ_HANDLER(TIVA_UART3_HANDLER) { CH_IRQ_PROLOGUE(); @@ -385,10 +486,15 @@ CH_IRQ_HANDLER(TIVA_UART3_HANDLER) } #endif +#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) +#if !defined(TIVA_UART4_HANDLER) +#error "TIVA_UART4_HANDLER not defined" +#endif /** - * @brief UART4 IRQ handler. + * @brief UART4 interrupt handler. + * + * @isr */ -#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) CH_IRQ_HANDLER(TIVA_UART4_HANDLER) { CH_IRQ_PROLOGUE(); @@ -399,10 +505,15 @@ CH_IRQ_HANDLER(TIVA_UART4_HANDLER) } #endif +#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) +#if !defined(TIVA_UART5_HANDLER) +#error "TIVA_UART5_HANDLER not defined" +#endif /** - * @brief UART5 IRQ handler. + * @brief UART5 interrupt handler. + * + * @isr */ -#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) CH_IRQ_HANDLER(TIVA_UART5_HANDLER) { CH_IRQ_PROLOGUE(); @@ -413,10 +524,15 @@ CH_IRQ_HANDLER(TIVA_UART5_HANDLER) } #endif +#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) +#if !defined(TIVA_UART6_HANDLER) +#error "TIVA_UART6_HANDLER not defined" +#endif /** - * @brief UART6 IRQ handler. + * @brief UART6 interrupt handler. + * + * @isr */ -#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) CH_IRQ_HANDLER(TIVA_UART6_HANDLER) { CH_IRQ_PROLOGUE(); @@ -427,10 +543,15 @@ CH_IRQ_HANDLER(TIVA_UART6_HANDLER) } #endif +#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) +#if !defined(TIVA_UART7_HANDLER) +#error "TIVA_UART7_HANDLER not defined" +#endif /** - * @brief UART7 IRQ handler. + * @brief UART7 interrupt handler. + * + * @isr */ -#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) CH_IRQ_HANDLER(TIVA_UART7_HANDLER) { CH_IRQ_PROLOGUE(); @@ -447,47 +568,65 @@ CH_IRQ_HANDLER(TIVA_UART7_HANDLER) /** * @brief Low level serial driver initialization. + * + * @notapi */ void sd_lld_init(void) { #if TIVA_SERIAL_USE_UART0 - sdObjectInit(&SD1, NULL, notify1); - SD1.uart = UART0; + sdObjectInit(&SD1); + iqObjectInit(&SD1.iqueue, sd_in_buf1, sizeof sd_in_buf1, NULL, &SD1); + oqObjectInit(&SD1.oqueue, sd_out_buf1, sizeof sd_out_buf1, notify1, &SD1); + SD1.uart = UART0_BASE; #endif #if TIVA_SERIAL_USE_UART1 - sdObjectInit(&SD2, NULL, notify2); - SD2.uart = UART1; + sdObjectInit(&SD2); + iqObjectInit(&SD2.iqueue, sd_in_buf2, sizeof sd_in_buf2, NULL, &SD2); + oqObjectInit(&SD2.oqueue, sd_out_buf2, sizeof sd_out_buf2, notify2, &SD2); + SD2.uart = UART1_BASE; #endif #if TIVA_SERIAL_USE_UART2 - sdObjectInit(&SD3, NULL, notify3); - SD3.uart = UART2; + sdObjectInit(&SD3); + iqObjectInit(&SD3.iqueue, sd_in_buf3, sizeof sd_in_buf3, NULL, &SD3); + oqObjectInit(&SD3.oqueue, sd_out_buf3, sizeof sd_out_buf3, notify3, &SD3); + SD3.uart = UART2_BASE; #endif #if TIVA_SERIAL_USE_UART3 - sdObjectInit(&SD4, NULL, notify4); - SD4.uart = UART3; + sdObjectInit(&SD4); + iqObjectInit(&SD4.iqueue, sd_in_buf4, sizeof sd_in_buf4, NULL, &SD4); + oqObjectInit(&SD4.oqueue, sd_out_buf4, sizeof sd_out_buf4, notify4, &SD4); + SD4.uart = UART3_BASE; #endif #if TIVA_SERIAL_USE_UART4 - sdObjectInit(&SD5, NULL, notify5); - SD5.uart = UART4; + sdObjectInit(&SD5); + iqObjectInit(&SD5.iqueue, sd_in_buf5, sizeof sd_in_buf5, NULL, &SD5); + oqObjectInit(&SD5.oqueue, sd_out_buf5, sizeof sd_out_buf5, notify5, &SD5); + SD5.uart = UART4_BASE; #endif #if TIVA_SERIAL_USE_UART5 - sdObjectInit(&SD6, NULL, notify6); - SD6.uart = UART5; + sdObjectInit(&SD6); + iqObjectInit(&SD6.iqueue, sd_in_buf6, sizeof sd_in_buf6, NULL, &SD6); + oqObjectInit(&SD6.oqueue, sd_out_buf6, sizeof sd_out_buf6, notify6, &SD6); + SD6.uart = UART5_BASE; #endif #if TIVA_SERIAL_USE_UART6 - sdObjectInit(&SD7, NULL, notify7); - SD7.uart = UART6; + sdObjectInit(&SD7); + iqObjectInit(&SD7.iqueue, sd_in_buf7, sizeof sd_in_buf7, NULL, &SD7); + oqObjectInit(&SD7.oqueue, sd_out_buf7, sizeof sd_out_buf7, notify7, &SD7); + SD7.uart = UART6_BASE; #endif #if TIVA_SERIAL_USE_UART7 - sdObjectInit(&SD8, NULL, notify8); - SD8.uart = UART7; + sdObjectInit(&SD8); + iqObjectInit(&SD8.iqueue, sd_in_buf8, sizeof sd_in_buf8, NULL, &SD8); + oqObjectInit(&SD8.oqueue, sd_out_buf8, sizeof sd_out_buf8, notify8, &SD8); + SD8.uart = UART7_BASE; #endif } @@ -498,6 +637,8 @@ void sd_lld_init(void) * @param[in] config the architecture-dependent serial driver configuration. * If this parameter is set to @p NULL then a default * configuration is used. + * + * @notapi */ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { @@ -507,49 +648,81 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) if (sdp->state == SD_STOP) { #if TIVA_SERIAL_USE_UART0 if (&SD1 == sdp) { - SYSCTL->RCGCUART |= (1 << 0); + HWREG(SYSCTL_RCGCUART) |= (1 << 0); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 0))) + ; + nvicEnableVector(TIVA_UART0_NUMBER, TIVA_SERIAL_UART0_PRIORITY); } #endif #if TIVA_SERIAL_USE_UART1 if (&SD2 == sdp) { - SYSCTL->RCGC.UART |= (1 << 1); + HWREG(SYSCTL_RCGCUART) |= (1 << 1); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 1))) + ; + nvicEnableVector(TIVA_UART1_NUMBER, TIVA_SERIAL_UART1_PRIORITY); } #endif #if TIVA_SERIAL_USE_UART2 if (&SD3 == sdp) { - SYSCTL->RCGC.UART |= (1 << 2); /* enable UART2 module */ + HWREG(SYSCTL_RCGCUART) |= (1 << 2); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 2))) + ; + nvicEnableVector(TIVA_UART2_NUMBER, TIVA_SERIAL_UART2_PRIORITY); } #endif #if TIVA_SERIAL_USE_UART3 if (&SD4 == sdp) { - SYSCTL->RCGC.UART |= (1 << 3); /* enable UART3 module */ + HWREG(SYSCTL_RCGCUART) |= (1 << 3); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 3))) + ; + nvicEnableVector(TIVA_UART3_NUMBER, TIVA_SERIAL_UART3_PRIORITY); } #endif #if TIVA_SERIAL_USE_UART4 if (&SD5 == sdp) { - SYSCTL->RCGC.UART |= (1 << 4); /* enable UART4 module */ + HWREG(SYSCTL_RCGCUART) |= (1 << 4); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 4))) + ; + nvicEnableVector(TIVA_UART4_NUMBER, TIVA_SERIAL_UART4_PRIORITY); } #endif #if TIVA_SERIAL_USE_UART5 if (&SD6 == sdp) { - SYSCTL->RCGC.UART |= (1 << 5); /* enable UART5 module */ + HWREG(SYSCTL_RCGCUART) |= (1 << 5); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 5))) + ; + nvicEnableVector(TIVA_UART5_NUMBER, TIVA_SERIAL_UART5_PRIORITY); } #endif #if TIVA_SERIAL_USE_UART6 if (&SD7 == sdp) { - SYSCTL->RCGC.UART |= (1 << 6); /* enable UART6 module */ + HWREG(SYSCTL_RCGCUART) |= (1 << 6); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 6))) + ; + nvicEnableVector(TIVA_UART6_NUMBER, TIVA_SERIAL_UART6_PRIORITY); } #endif #if TIVA_SERIAL_USE_UART7 if (&SD8 == sdp) { - SYSCTL->RCGC.UART |= (1 << 7); /* enable UART7 module */ + HWREG(SYSCTL_RCGCUART) |= (1 << 7); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 7))) + ; + nvicEnableVector(TIVA_UART7_NUMBER, TIVA_SERIAL_UART7_PRIORITY); } #endif @@ -563,6 +736,8 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) * interrupt vector. * * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi */ void sd_lld_stop(SerialDriver *sdp) { @@ -570,56 +745,56 @@ void sd_lld_stop(SerialDriver *sdp) uart_deinit(sdp->uart); #if TIVA_SERIAL_USE_UART0 if (&SD1 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 0); /* disable UART0 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 0); /* disable UART0 module */ nvicDisableVector(TIVA_UART0_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART1 if (&SD2 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 1); /* disable UART1 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 1); /* disable UART1 module */ nvicDisableVector(TIVA_UART1_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART2 if (&SD3 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 2); /* disable UART2 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 2); /* disable UART2 module */ nvicDisableVector(TIVA_UART2_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART3 if (&SD4 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 3); /* disable UART3 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 3); /* disable UART3 module */ nvicDisableVector(TIVA_UART3_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART4 if (&SD5 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 4); /* disable UART4 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 4); /* disable UART4 module */ nvicDisableVector(TIVA_UART4_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART5 if (&SD6 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 5); /* disable UART5 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 5); /* disable UART5 module */ nvicDisableVector(TIVA_UART5_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART6 if (&SD7 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 6); /* disable UART6 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 6); /* disable UART6 module */ nvicDisableVector(TIVA_UART6_NUMBER); return; } #endif #if TIVA_SERIAL_USE_UART7 if (&SD8 == sdp) { - SYSCTL->RCGC.UART &= ~(1 << 7); /* disable UART7 module */ + HWREG(SYSCTL_RCGCUART) &= ~(1 << 7); /* disable UART7 module */ nvicDisableVector(TIVA_UART7_NUMBER); return; } diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h index 203ef6a..bde999e 100644 --- a/os/hal/ports/TIVA/LLD/hal_serial_lld.h +++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -15,7 +15,7 @@ */ /** - * @file TIVA/LLD/serial_lld.h + * @file UART/hal_serial_lld.h * @brief Tiva low level serial driver header. * * @addtogroup SERIAL @@ -32,162 +32,14 @@ /*===========================================================================*/ /** - * @name FR register bits definitions - * @{ - */ - -#define TIVA_FR_CTS (1 << 0) - -#define TIVA_FR_BUSY (1 << 3) - -#define TIVA_FR_RXFE (1 << 4) - -#define TIVA_FR_TXFF (1 << 5) - -#define TIVA_FR_RXFF (1 << 6) - -#define TIVA_FR_TXFE (1 << 7) - -/** - * @} - */ - -/** - * @name LCRH register bits definitions - * @{ - */ - -#define TIVA_LCRH_BRK (1 << 0) - -#define TIVA_LCRH_PEN (1 << 1) - -#define TIVA_LCRH_EPS (1 << 2) - -#define TIVA_LCRH_STP2 (1 << 3) - -#define TIVA_LCRH_FEN (1 << 4) - -#define TIVA_LCRH_WLEN_MASK (3 << 5) -#define TIVA_LCRH_WLEN_5 (0 << 5) -#define TIVA_LCRH_WLEN_6 (1 << 5) -#define TIVA_LCRH_WLEN_7 (2 << 5) -#define TIVA_LCRH_WLEN_8 (3 << 5) - -#define TIVA_LCRH_SPS (1 << 7) - -/** - * @} + * @brief Advanced buffering support switch. + * @details This constants enables the advanced buffering support in the + * low level driver, the queue buffer is no more part of the + * @p SerialDriver structure, each driver can have a different + * queue size. */ - -/** - * @name CTL register bits definitions - * @{ - */ - -#define TIVA_CTL_UARTEN (1 << 0) - -#define TIVA_CTL_SIREN (1 << 1) - -#define TIVA_CTL_SIRLP (1 << 2) - -#define TIVA_CTL_SMART (1 << 3) - -#define TIVA_CTL_EOT (1 << 4) - -#define TIVA_CTL_HSE (1 << 5) - -#define TIVA_CTL_LBE (1 << 7) - -#define TIVA_CTL_TXE (1 << 8) - -#define TIVA_CTL_RXE (1 << 9) - -#define TIVA_CTL_RTS (1 << 11) - -#define TIVA_CTL_RTSEN (1 << 14) - -#define TIVA_CTL_CTSEN (1 << 15) - -/** - * @} - */ - -/** - * @name IFLS register bits definitions - * @{ - */ - -#define TIVA_IFLS_TXIFLSEL_MASK (7 << 0) -#define TIVA_IFLS_TXIFLSEL_1_8_F (0 << 0) -#define TIVA_IFLS_TXIFLSEL_1_4_F (1 << 0) -#define TIVA_IFLS_TXIFLSEL_1_2_F (2 << 0) -#define TIVA_IFLS_TXIFLSEL_3_4_F (3 << 0) -#define TIVA_IFLS_TXIFLSEL_7_8_F (4 << 0) - -#define TIVA_IFLS_RXIFLSEL_MASK (7 << 3) -#define TIVA_IFLS_RXIFLSEL_7_8_E (0 << 3) -#define TIVA_IFLS_RXIFLSEL_3_4_E (1 << 3) -#define TIVA_IFLS_RXIFLSEL_1_2_E (2 << 3) -#define TIVA_IFLS_RXIFLSEL_1_4_E (3 << 3) -#define TIVA_IFLS_RXIFLSEL_1_8_E (4 << 3) - -/** - * @} - */ - -/** - * @name MIS register bits definitions - * @{ - */ - -#define TIVA_MIS_CTSMIS (1 << 1) - -#define TIVA_MIS_RXMIS (1 << 4) - -#define TIVA_MIS_TXMIS (1 << 5) - -#define TIVA_MIS_RTMIS (1 << 6) - -#define TIVA_MIS_FEMIS (1 << 7) - -#define TIVA_MIS_PEMIS (1 << 8) - -#define TIVA_MIS_BEMIS (1 << 9) - -#define TIVA_MIS_OEMIS (1 << 10) - -#define TIVA_MIS_9BITMIS (1 << 12) - -/** - * @} - */ - -/** - * @name IM register bits definitions - * @{ - */ - -#define TIVA_IM_CTSIM (1 << 1) - -#define TIVA_IM_RXIM (1 << 4) - -#define TIVA_IM_TXIM (1 << 5) - -#define TIVA_IM_RTIM (1 << 6) +#define SERIAL_ADVANCED_BUFFERING_SUPPORT TRUE -#define TIVA_IM_FEIM (1 << 7) - -#define TIVA_IM_PEIM (1 << 8) - -#define TIVA_IM_BEIM (1 << 9) - -#define TIVA_IM_OEIM (1 << 10) - -#define TIVA_IM_9BITIM (1 << 12) - -/** - * @} - */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -196,7 +48,6 @@ * @name Configuration options * @{ */ - /** * @brief UART0 driver enable switch. * @details If set to @p TRUE the support for UART0 is included. @@ -326,8 +177,117 @@ #endif /** - * @} + * @brief Input buffer size for UART0. + */ +#if !defined(TIVA_SERIAL_UART0_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART0_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART0. + */ +#if !defined(TIVA_SERIAL_UART0_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART0_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART1. + */ +#if !defined(TIVA_SERIAL_UART1_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART1_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART1. + */ +#if !defined(TIVA_SERIAL_UART1_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART1_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART2. + */ +#if !defined(TIVA_SERIAL_UART2_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART2_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART2. + */ +#if !defined(TIVA_SERIAL_UART2_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART2_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART3. + */ +#if !defined(TIVA_SERIAL_UART3_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART3_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART3. + */ +#if !defined(TIVA_SERIAL_UART3_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART3_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART4. + */ +#if !defined(TIVA_SERIAL_UART4_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART4_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART4. */ +#if !defined(TIVA_SERIAL_UART4_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART4_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART5. + */ +#if !defined(TIVA_SERIAL_UART5_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART5_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART5. + */ +#if !defined(TIVA_SERIAL_UART5_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART5_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART6. + */ +#if !defined(TIVA_SERIAL_UART6_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART6_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART6. + */ +#if !defined(TIVA_SERIAL_UART6_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART6_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART7. + */ +#if !defined(TIVA_SERIAL_UART7_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART7_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART7. + */ +#if !defined(TIVA_SERIAL_UART7_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART7_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ @@ -388,22 +348,32 @@ * @brief Tiva Serial Driver configuration structure. * @details An instance of this structure must be passed to @p sdStart() * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. */ typedef struct { /** * @brief Bit rate. */ - uint32_t sc_speed; + uint32_t speed; /* End of the mandatory fields. */ /** - * @brief Initialization value for the LCRH (Line Control) register. + * @brief Initialization value for the CTL register. + */ + uint16_t ctl; + /** + * @brief Initialization value for the LCRH register. + */ + uint8_t lcrh; + /** + * @brief Initialization value for the IFLS register. */ - uint32_t sc_lcrh; + uint8_t ifls; /** - * @brief Initialization value for the IFLS (Interrupt FIFO Level Select) - * register. + * @brief Initialization value for the CC register. */ - uint32_t sc_ifls; + uint8_t cc; } SerialConfig; /** @@ -417,13 +387,9 @@ typedef struct { input_queue_t iqueue; \ /* Output queue.*/ \ output_queue_t oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ /* End of the mandatory fields.*/ \ /* Pointer to the USART registers block.*/ \ - UART_TypeDef *uart; + uint32_t uart; /*===========================================================================*/ /* Driver macros. */ diff --git a/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c new file mode 100644 index 0000000..374ea6d --- /dev/null +++ b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c @@ -0,0 +1,826 @@ +/* + Copyright (C) 2014..2017 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UART/hal_uart_lld.c + * @brief Tiva low level UART driver code. + * + * @addtogroup UART + * @{ + */ + +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief UART0 UART driver identifier.*/ +#if TIVA_UART_USE_UART0 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/** @brief UART1 UART driver identifier.*/ +#if TIVA_UART_USE_UART1 || defined(__DOXYGEN__) +UARTDriver UARTD2; +#endif + +/** @brief UART2 UART driver identifier.*/ +#if TIVA_UART_USE_UART2 || defined(__DOXYGEN__) +UARTDriver UARTD3; +#endif + +/** @brief UART3 UART driver identifier.*/ +#if TIVA_UART_USE_UART3 || defined(__DOXYGEN__) +UARTDriver UARTD4; +#endif + +/** @brief UART4 UART driver identifier.*/ +#if TIVA_UART_USE_UART4 || defined(__DOXYGEN__) +UARTDriver UARTD5; +#endif + +/** @brief UART5 UART driver identifier.*/ +#if TIVA_UART_USE_UART5 || defined(__DOXYGEN__) +UARTDriver UARTD6; +#endif + +/** @brief UART6 UART driver identifier.*/ +#if TIVA_UART_USE_UART6 || defined(__DOXYGEN__) +UARTDriver UARTD7; +#endif + +/** @brief UART7 UART driver identifier.*/ +#if TIVA_UART_USE_UART7 || defined(__DOXYGEN__) +UARTDriver UARTD8; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Status bits translation. + * + * @param[in] err UART LSR register value + * + * @return The error flags. + */ +static uartflags_t translate_errors(uint32_t err) +{ + uartflags_t sts = 0; + + if (err & UART_MIS_FEMIS) + sts |= UART_FRAMING_ERROR; + if (err & UART_MIS_PEMIS) + sts |= UART_PARITY_ERROR; + if (err & UART_MIS_BEMIS) + sts |= UART_BREAK_DETECTED; + if (err & UART_MIS_OEMIS) + sts |= UART_OVERRUN_ERROR; + + return sts; +} + +/** + * @brief Puts the receiver in the UART_RX_IDLE state. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_enter_rx_idle_loop(UARTDriver *uartp) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + dmaChannelDisable(uartp->dmarxnr); + + /* Configure for 8-bit transfers.*/ + primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR); + primary[uartp->dmarxnr].dstendp = (volatile void *)&uartp->rxbuf; + primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(1) | + UDMA_CHCTL_XFERMODE_BASIC; + + dmaChannelSingleBurst(uartp->dmarxnr); + dmaChannelPrimary(uartp->dmarxnr); + dmaChannelPriorityDefault(uartp->dmarxnr); + dmaChannelEnableRequest(uartp->dmarxnr); + + /* Enable DMA channel, transfer starts immediately.*/ + dmaChannelEnable(uartp->dmarxnr); +} + +/** + * @brief UART de-initialization. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_stop(UARTDriver *uartp) +{ + /* Stops RX and TX DMA channels.*/ + dmaChannelDisable(uartp->dmarxnr); + dmaChannelDisable(uartp->dmatxnr); + + /* Stops USART operations.*/ + HWREG(uartp->uart + UART_O_CTL) &= ~UART_CTL_UARTEN; +} + +/** + * @brief UART initialization. + * + * @param[in] uartp pointer to a @p UARTDriver object + */ +static void uart_init(UARTDriver *uartp) +{ + uint32_t u = uartp->uart; + const UARTConfig *config = uartp->config; + uint32_t brd; + uint32_t speed = config->speed; + uint32_t clock_source; + + if (uartp->config->ctl & UART_CTL_HSE) { + /* High speed mode is enabled, half the baud rate to compensate + * for high speed mode.*/ + speed = (speed + 1) / 2; + } + + if ((config->cc & UART_CC_CS_M) == UART_CC_CS_SYSCLK) { + /* UART is clocked using the SYSCLK.*/ + clock_source = TIVA_SYSCLK * 8; + } + else { + /* UART is clocked using the PIOSC.*/ + clock_source = 16000000 * 8; + } + + /* Calculate the baud rate divisor */ + brd = ((clock_source / speed) + 1) / 2; + + /* Disable UART.*/ + HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN; + + /* Set baud rate.*/ + HWREG(u + UART_O_IBRD) = brd / 64; + HWREG(u + UART_O_FBRD) = brd % 64; + + /* Line control/*/ + HWREG(u + UART_O_LCRH) = config->lcrh; + + /* Select clock source.*/ + HWREG(u + UART_O_CC) = config->cc & UART_CC_CS_M; + + /* FIFO configuration.*/ + HWREG(u + UART_O_IFLS) = config->ifls & (UART_IFLS_RX_M | UART_IFLS_TX_M); + + /* Enable interrupts.*/ + HWREG(u + UART_O_IM) = UART_IM_TXIM | UART_IM_OEIM | UART_IM_BEIM | UART_IM_PEIM | UART_IM_FEIM; + + /* Enable DMA for the UART */ + HWREG(u + UART_O_DMACTL) = UART_DMACTL_TXDMAE | UART_DMACTL_RXDMAE | UART_DMACTL_DMAERR; + + /* Note that some bits are enforced.*/ + HWREG(u + UART_O_CTL) = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN | UART_CTL_EOT; + + /* Starting the receiver idle loop.*/ + uart_enter_rx_idle_loop(uartp); +} + +/** + * @brief UART common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_serve_interrupt(UARTDriver *uartp) +{ + uint32_t dmachis = HWREG(UDMA_CHIS); + uint32_t mis = HWREG(uartp->uart + UART_O_MIS); + + if (mis & UART_MIS_TXMIS) { + /* End of transfer */ + _uart_tx2_isr_code(uartp); + } + + if (mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_PEMIS | UART_MIS_FEMIS)) { + /* Error occurred */ + _uart_rx_error_isr_code(uartp, translate_errors(mis)); + } + + if (dmachis & (1 << uartp->dmarxnr)) { + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, if enabled, for each + received character and then the driver stays in the same state.*/ + _uart_rx_idle_code(uartp); + uart_enter_rx_idle_loop(uartp); + } + else { + /* Receiver in active state, a callback is generated, if enabled, after + a completed transfer.*/ + _uart_rx_complete_isr_code(uartp); + } + } + + if (dmachis & (1 << uartp->dmatxnr)) { + /* A callback is generated, if enabled, after a completed transfer.*/ + _uart_tx1_isr_code(uartp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_UART_USE_UART0 || defined(__DOXYGEN__) +#if !defined(TIVA_UART0_HANDLER) +#error "TIVA_UART0_HANDLER not defined" +#endif +/** + * @brief UART0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART1 || defined(__DOXYGEN__) +#if !defined(TIVA_UART1_HANDLER) +#error "TIVA_UART1_HANDLER not defined" +#endif +/** + * @brief UART1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART2 || defined(__DOXYGEN__) +#if !defined(TIVA_UART2_HANDLER) +#error "TIVA_UART2_HANDLER not defined" +#endif +/** + * @brief UART2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART3 || defined(__DOXYGEN__) +#if !defined(TIVA_UART3_HANDLER) +#error "TIVA_UART3_HANDLER not defined" +#endif +/** + * @brief UART3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART4 || defined(__DOXYGEN__) +#if !defined(TIVA_UART4_HANDLER) +#error "TIVA_UART4_HANDLER not defined" +#endif +/** + * @brief UART4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD5); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART5 || defined(__DOXYGEN__) +#if !defined(TIVA_UART5_HANDLER) +#error "TIVA_UART5_HANDLER not defined" +#endif +/** + * @brief UART5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD6); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART6 || defined(__DOXYGEN__) +#if !defined(TIVA_UART6_HANDLER) +#error "TIVA_UART6_HANDLER not defined" +#endif +/** + * @brief UART6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_UART_USE_UART7 || defined(__DOXYGEN__) +#if !defined(TIVA_UART7_HANDLER) +#error "TIVA_UART7_HANDLER not defined" +#endif +/** + * @brief UART7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UART7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + uart_serve_interrupt(&UARTD8); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) +{ +#if TIVA_UART_USE_UART0 + uartObjectInit(&UARTD1); + UARTD1.uart = UART0_BASE; + UARTD1.dmarxnr = TIVA_UART_UART0_RX_UDMA_CHANNEL; + UARTD1.dmatxnr = TIVA_UART_UART0_TX_UDMA_CHANNEL; + UARTD1.rxchnmap = TIVA_UART_UART0_RX_UDMA_MAPPING; + UARTD1.txchnmap = TIVA_UART_UART0_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART1 + uartObjectInit(&UARTD2); + UARTD2.uart = UART1_BASE; + UARTD2.dmarxnr = TIVA_UART_UART1_RX_UDMA_CHANNEL; + UARTD2.dmatxnr = TIVA_UART_UART1_TX_UDMA_CHANNEL; + UARTD2.rxchnmap = TIVA_UART_UART1_RX_UDMA_MAPPING; + UARTD2.txchnmap = TIVA_UART_UART1_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART2 + uartObjectInit(&UARTD3); + UARTD2.uart = UART2_BASE; + UARTD2.dmarxnr = TIVA_UART_UART2_RX_UDMA_CHANNEL; + UARTD2.dmatxnr = TIVA_UART_UART2_TX_UDMA_CHANNEL; + UARTD2.rxchnmap = TIVA_UART_UART2_RX_UDMA_MAPPING; + UARTD2.txchnmap = TIVA_UART_UART2_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART3 + uartObjectInit(&UARTD4); + UARTD4.uart = UART3_BASE; + UARTD4.dmarxnr = TIVA_UART_UART3_RX_UDMA_CHANNEL; + UARTD4.dmatxnr = TIVA_UART_UART3_TX_UDMA_CHANNEL; + UARTD4.rxchnmap = TIVA_UART_UART3_RX_UDMA_MAPPING; + UARTD4.txchnmap = TIVA_UART_UART3_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART4 + uartObjectInit(&UARTD5); + UARTD5.uart = UART4_BASE; + UARTD5.dmarxnr = TIVA_UART_UART4_RX_UDMA_CHANNEL; + UARTD5.dmatxnr = TIVA_UART_UART4_TX_UDMA_CHANNEL; + UARTD5.rxchnmap = TIVA_UART_UART4_RX_UDMA_MAPPING; + UARTD5.txchnmap = TIVA_UART_UART4_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART5 + uartObjectInit(&UARTD6); + UARTD6.uart = UART5_BASE; + UARTD6.dmarxnr = TIVA_UART_UART5_RX_UDMA_CHANNEL; + UARTD6.dmatxnr = TIVA_UART_UART5_TX_UDMA_CHANNEL; + UARTD6.rxchnmap = TIVA_UART_UART5_RX_UDMA_MAPPING; + UARTD6.txchnmap = TIVA_UART_UART5_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART6 + uartObjectInit(&UARTD7); + UARTD7.uart = UART6_BASE; + UARTD7.dmarxnr = TIVA_UART_UART6_RX_UDMA_CHANNEL; + UARTD7.dmatxnr = TIVA_UART_UART6_TX_UDMA_CHANNEL; + UARTD7.rxchnmap = TIVA_UART_UART6_RX_UDMA_MAPPING; + UARTD7.txchnmap = TIVA_UART_UART6_TX_UDMA_MAPPING; +#endif +#if TIVA_UART_USE_UART7 + uartObjectInit(&UARTD8); + UARTD8.uart = UART7_BASE; + UARTD8.dmarxnr = TIVA_UART_UART7_RX_UDMA_CHANNEL; + UARTD8.dmatxnr = TIVA_UART_UART7_TX_UDMA_CHANNEL; + UARTD8.rxchnmap = TIVA_UART_UART7_RX_UDMA_MAPPING; + UARTD8.txchnmap = TIVA_UART_UART7_TX_UDMA_MAPPING; +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + if (uartp->state == UART_STOP) { +#if TIVA_UART_USE_UART0 + if (&UARTD1 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 0); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 0))) + ; + + nvicEnableVector(TIVA_UART0_NUMBER, TIVA_UART_UART0_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART1 + if (&UARTD2 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 1); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 1))) + ; + + nvicEnableVector(TIVA_UART1_NUMBER, TIVA_UART_UART1_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART2 + if (&UARTD3 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 2); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 2))) + ; + + nvicEnableVector(TIVA_UART2_NUMBER, TIVA_UART_UART2_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART3 + if (&UARTD4 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 3); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 3))) + ; + + nvicEnableVector(TIVA_UART3_NUMBER, TIVA_UART_UART3_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART4 + if (&UARTD5 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 4); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 4))) + ; + + nvicEnableVector(TIVA_UART4_NUMBER, TIVA_UART_UART4_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART5 + if (&UARTD6 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 5); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 5))) + ; + + nvicEnableVector(TIVA_UART5_NUMBER, TIVA_UART_UART5_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART6 + if (&UARTD7 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 6); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 6))) + ; + + nvicEnableVector(TIVA_UART6_NUMBER, TIVA_UART_UART6_PRIORITY); + } +#endif +#if TIVA_UART_USE_UART7 + if (&UARTD8 == uartp) { + bool b; + b = udmaChannelAllocate(uartp->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(uartp->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + HWREG(SYSCTL_RCGCUART) |= (1 << 7); + + while (!(HWREG(SYSCTL_PRUART) & (1 << 7))) + ; + + nvicEnableVector(TIVA_UART7_NUMBER, TIVA_UART_UART7_PRIORITY); + } +#endif + + uartp->rxbuf = 0; + + HWREG(UDMA_CHMAP0 + (uartp->dmarxnr / 8) * 4) |= (uartp->rxchnmap << (uartp->dmarxnr % 8)); + HWREG(UDMA_CHMAP0 + (uartp->dmatxnr / 8) * 4) |= (uartp->txchnmap << (uartp->dmatxnr % 8)); + } + + uartp->rxstate = UART_RX_IDLE; + uartp->txstate = UART_TX_IDLE; + uart_init(uartp); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + + if (uartp->state == UART_READY) { + uart_stop(uartp); + udmaChannelRelease(uartp->dmarxnr); + udmaChannelRelease(uartp->dmatxnr); + +#if TIVA_UART_USE_UART0 + if (&UARTD1 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 0); + return; + } +#endif +#if TIVA_UART_USE_UART1 + if (&UARTD2 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 1); + return; + } +#endif +#if TIVA_UART_USE_UART2 + if (&UARTD3 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 2); + return; + } +#endif +#if TIVA_UART_USE_UART3 + if (&UARTD4 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 3); + return; + } +#endif +#if TIVA_UART_USE_UART4 + if (&UARTD5 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 4); + return; + } +#endif +#if TIVA_UART_USE_UART5 + if (&UARTD6 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 5); + return; + } +#endif +#if TIVA_UART_USE_UART6 + if (&UARTD7 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 6); + return; + } +#endif +#if TIVA_UART_USE_UART7 + if (&UARTD8 == uartp) { + HWREG(SYSCTL_RCGCUART) &= ~(1 << 7); + return; + } +#endif + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + /* TODO: This assert should be moved to the dma helper driver */ + osalDbgAssert((uint32_t)txbuf >= SRAM_BASE, "txbuf should be in SRAM region."); + + dmaChannelDisable(uartp->dmatxnr); + + /* Configure for 8-bit transfers.*/ + primary[uartp->dmatxnr].srcendp = (volatile void *)txbuf+n-1; + primary[uartp->dmatxnr].dstendp = (void *)(uartp->uart + UART_O_DR); + primary[uartp->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + dmaChannelSingleBurst(uartp->dmatxnr); + dmaChannelPrimary(uartp->dmatxnr); + dmaChannelPriorityDefault(uartp->dmatxnr); + dmaChannelEnableRequest(uartp->dmatxnr); + + /* Enable DMA channel, transfer starts immediately.*/ + dmaChannelEnable(uartp->dmatxnr); +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + uint16_t left; + + dmaChannelDisable(uartp->dmatxnr); + + left = ((primary[uartp->dmatxnr].chctl & UDMA_CHCTL_XFERSIZE_M) + 1) >> 4; + + return left; +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + /* TODO: This assert should be moved to the dma helper driver */ + osalDbgAssert((uint32_t)rxbuf >= SRAM_BASE, "rxbuf should be in SRAM region."); + + dmaChannelDisable(uartp->dmarxnr); + + /* Configure for 8-bit transfers.*/ + primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR); + primary[uartp->dmarxnr].dstendp = (volatile void *)rxbuf+n-1; + primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + dmaChannelSingleBurst(uartp->dmarxnr); + dmaChannelPrimary(uartp->dmarxnr); + dmaChannelPriorityDefault(uartp->dmarxnr); + dmaChannelEnableRequest(uartp->dmarxnr); + + /* Enable DMA channel, transfer starts immediately.*/ + dmaChannelEnable(uartp->dmarxnr); +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + uint16_t left; + + dmaChannelDisable(uartp->dmatxnr); + + left = ((primary[uartp->dmatxnr].chctl & UDMA_CHCTL_XFERSIZE_M) + 1) >> 4; + + uart_enter_rx_idle_loop(uartp); + + return left; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h new file mode 100644 index 0000000..1dc743b --- /dev/null +++ b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h @@ -0,0 +1,471 @@ +/* + Copyright (C) 2014..2017 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UART/hal_uart_lld.h + * @brief Tiva low level UART driver header. + * + * @addtogroup UART + * @{ + */ + +#ifndef HAL_UART_LLD_H +#define HAL_UART_LLD_H + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART driver on UART0 enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART0) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART0 FALSE +#endif + +/** + * @brief UART driver on UART1 enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART1) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART1 FALSE +#endif + +/** + * @brief UART driver on UART2 enable switch. + * @details If set to @p TRUE the support for UART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART2) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART2 FALSE +#endif + +/** + * @brief UART driver on UART3 enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART3) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART3 FALSE +#endif + +/** + * @brief UART driver on UART4 enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART4) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART4 FALSE +#endif + +/** + * @brief UART driver on UART5 enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART5) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART5 FALSE +#endif + +/** + * @brief UART driver on UART6 enable switch. + * @details If set to @p TRUE the support for UART6 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART6) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART6 FALSE +#endif + +/** + * @brief UART driver on UART7 enable switch. + * @details If set to @p TRUE the support for UART7 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_UART_USE_UART7) || defined(__DOXYGEN__) +#define TIVA_UART_USE_UART7 FALSE +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART0_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART1_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART2_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART3 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART3_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART4 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART4_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART5 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART5_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART6 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART6_IRQ_PRIORITY 5 +#endif + +/** + * @brief UART7 interrupt priority level setting. + */ +#if !defined(TIVA_UART_UART7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UART_UART7_IRQ_PRIORITY 5 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TIVA_UART_USE_UART0 && !TIVA_HAS_UART0 +#error "UART0 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART1 && !TIVA_HAS_UART1 +#error "UART1 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART2 && !TIVA_HAS_UART2 +#error "UART2 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART3 && !TIVA_HAS_UART3 +#error "UART3 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART4 && !TIVA_HAS_UART4 +#error "UART4 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART5 && !TIVA_HAS_UART5 +#error "UART5 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART6 && !TIVA_HAS_UART6 +#error "UART6 not present in the selected device" +#endif + +#if TIVA_UART_USE_UART7 && !TIVA_HAS_UART7 +#error "UART7 not present in the selected device" +#endif + +#if !TIVA_UART_USE_UART0 && !TIVA_UART_USE_UART1 && !TIVA_UART_USE_UART2 && \ + !TIVA_UART_USE_UART3 && !TIVA_UART_USE_UART4 && !TIVA_UART_USE_UART5 && \ + !TIVA_UART_USE_UART6 && !TIVA_UART_USE_UART7 +#error "UART driver activated but no UART peripheral assigned" +#endif + +#if TIVA_UART_USE_UART0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART0" +#endif + +#if TIVA_UART_USE_UART1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART1" +#endif + +#if TIVA_UART_USE_UART2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART2" +#endif + +#if TIVA_UART_USE_UART3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART3" +#endif + +#if TIVA_UART_USE_UART4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART4" +#endif + +#if TIVA_UART_USE_UART5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART5" +#endif + +#if TIVA_UART_USE_UART6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART6" +#endif + +#if TIVA_UART_USE_UART7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART7" +#endif + +#if !defined(TIVA_UDMA_REQUIRED) +#define TIVA_UDMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + /** + * @brief Bit rate. + */ + uint32_t speed; + /* End of the mandatory fields. */ + /** + * @brief Initialization value for the CTL register. + */ + uint16_t ctl; + /** + * @brief Initialization value for the LCRH register. + */ + uint8_t lcrh; + /** + * @brief Initialization value for the IFLS register. + */ + uint8_t ifls; + /** + * @brief Initialization value for the CC register. + */ + uint8_t cc; +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Synchronization flag for transmit operations. + */ + bool early; + /** + * @brief Waiting thread on RX. + */ + thread_reference_t threadrx; + /** + * @brief Waiting thread on TX. + */ + thread_reference_t threadtx; +#endif /* UART_USE_WAIT */ +#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + mutex_t mutex; +#endif /* UART_USE_MUTUAL_EXCLUSION */ +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the UART registers block. + */ + uint32_t uart; + /** + * @brief Receive DMA channel number. + */ + uint8_t dmarxnr; + /** + * @brief Transmit DMA channel number. + */ + uint8_t dmatxnr; + /** + * @brief Receive DMA channel map. + */ + uint8_t rxchnmap; + /** + * @brief Transmit DMA channel map. + */ + uint8_t txchnmap; + /** + * @brief Default receive buffer while into @p UART_RX_IDLE state. + */ + volatile uint16_t rxbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if TIVA_UART_USE_UART0 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#if TIVA_UART_USE_UART1 && !defined(__DOXYGEN__) +extern UARTDriver UARTD2; +#endif + +#if TIVA_UART_USE_UART2 && !defined(__DOXYGEN__) +extern UARTDriver UARTD3; +#endif + +#if TIVA_UART_USE_UART3 && !defined(__DOXYGEN__) +extern UARTDriver UARTD4; +#endif + +#if TIVA_UART_USE_UART4 && !defined(__DOXYGEN__) +extern UARTDriver UARTD5; +#endif + +#if TIVA_UART_USE_UART5 && !defined(__DOXYGEN__) +extern UARTDriver UARTD6; +#endif + +#if TIVA_UART_USE_UART6 && !defined(__DOXYGEN__) +extern UARTDriver UARTD7; +#endif + +#if TIVA_UART_USE_UART7 && !defined(__DOXYGEN__) +extern UARTDriver UARTD8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* HAL_UART_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/WDT/driver.mk b/os/hal/ports/TIVA/LLD/WDT/driver.mk new file mode 100644 index 0000000..867d0e6 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/WDT/driver.mk @@ -0,0 +1,9 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_WDG TRUE,$(HALCONF)),) +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c +endif +else +PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c +endif + +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c index 38dcef0..705fce6 100644 --- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c +++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,7 +16,7 @@ /** - * @file TIVA/wdg_lld.c + * @file WDT/hal_wdg_lld.c * @brief WDG Driver subsystem low level driver source. * * @addtogroup WDG @@ -60,14 +60,14 @@ static void serve_interrupt(WDGDriver *wdgp) { uint32_t mis; - mis = wdgp->wdt->MIS; + mis = HWREG(wdgp->wdt + WDT_O_MIS); - if (mis & MIS_WDTMIS) { + if (mis & WDT_MIS_WDTMIS) { /* Invoke callback, if any */ if (wdgp->config->callback) { if (wdgp->config->callback(wdgp)) { /* Clear interrupt */ - wdgp->wdt->ICR = 0; + HWREG(wdgp->wdt + WDT_O_ICR) = 0; wdgTivaSyncWrite(wdgp); } } @@ -113,12 +113,12 @@ void wdg_lld_init(void) { #if TIVA_WDG_USE_WDT0 WDGD1.state = WDG_STOP; - WDGD1.wdt = WDT0; + WDGD1.wdt = WATCHDOG0_BASE; #endif /* TIVA_WDG_USE_WDT0 */ #if TIVA_WDG_USE_WDT1 WDGD2.state = WDG_STOP; - WDGD2.wdt = WDT1; + WDGD2.wdt = WATCHDOG1_BASE; #endif /* TIVA_WDG_USE_WDT1 */ /* The shared vector is initialized on driver initialization and never @@ -137,32 +137,32 @@ void wdg_lld_start(WDGDriver *wdgp) { #if TIVA_WDG_USE_WDT0 if (&WDGD1 == wdgp) { - SYSCTL->RCGCWD |= (1 << 0); + HWREG(SYSCTL_RCGCWD) |= (1 << 0); - while (!(SYSCTL->PRWD & (1 << 0))) + while (!(HWREG(SYSCTL_PRWD) & (1 << 0))) ; } #endif /* TIVA_WDG_USE_WDT0 */ #if TIVA_WDG_USE_WDT1 if (&WDGD2 == wdgp) { - SYSCTL->RCGCWD |= (1 << 1); + HWREG(SYSCTL_RCGCWD) |= (1 << 1); - while (!(SYSCTL->PRWD & (1 << 1))) + while (!(HWREG(SYSCTL_PRWD) & (1 << 1))) ; } #endif /* TIVA_WDG_USE_WDT1 */ - wdgp->wdt->LOAD = wdgp->config->load; + HWREG(wdgp->wdt + WDT_O_LOAD) = wdgp->config->load; wdgTivaSyncWrite(wdgp); - wdgp->wdt->TEST = wdgp->config->test; + HWREG(wdgp->wdt + WDT_O_TEST) = wdgp->config->test; wdgTivaSyncWrite(wdgp); - wdgp->wdt->CTL |= CTL_RESEN; + HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_RESEN; wdgTivaSyncWrite(wdgp); - wdgp->wdt->CTL |= CTL_INTEN; + HWREG(wdgp->wdt + WDT_O_CTL) |= WDT_CTL_INTEN; wdgTivaSyncWrite(wdgp); } @@ -177,15 +177,15 @@ void wdg_lld_stop(WDGDriver *wdgp) { #if TIVA_WDG_USE_WDT0 if (&WDGD1 == wdgp) { - SYSCTL->SRWD |= (1 << 0); - SYSCTL->SRWD &= ~(1 << 0); + HWREG(SYSCTL_SRWD) |= (1 << 0); + HWREG(SYSCTL_SRWD) &= ~(1 << 0); } #endif /* TIVA_WDG_USE_WDT0 */ #if TIVA_WDG_USE_WDT1 if (&WDGD2 == wdgp) { - SYSCTL->SRWD |= (1 << 1); - SYSCTL->SRWD &= ~(1 << 1); + HWREG(SYSCTL_SRWD) |= (1 << 1); + HWREG(SYSCTL_SRWD) &= ~(1 << 1); } #endif /* TIVA_WDG_USE_WDT1 */ } @@ -219,7 +219,7 @@ void wdg_lld_reset(WDGDriver *wdgp) #endif /* defined(TM4C123_USE_REVISION_6_FIX) || defined(TM4C123_USE_REVISION_7_FIX) */ - wdgp->wdt->LOAD = wdgp->config->load; + HWREG(wdgp->wdt + WDT_O_LOAD) = wdgp->config->load; wdgTivaSyncWrite(wdgp); } @@ -234,7 +234,7 @@ void wdg_lld_reset(WDGDriver *wdgp) void wdgTivaSyncWrite(WDGDriver *wdgp) { if (&WDGD2 == wdgp) { - while (!(wdgp->wdt->CTL & CTL_WRC)) { + while (!(HWREG(wdgp->wdt + WDT_O_CTL) & CTL_WRC)) { ; } } diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h index f88fa26..0f694c5 100644 --- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h +++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,7 +16,7 @@ /** - * @file TIVA/wdg_lld.h + * @file WDT/hal_wdg_lld.h * @brief WDG Driver subsystem low level driver header. * * @addtogroup WDG @@ -32,23 +32,6 @@ /* Driver constants. */ /*===========================================================================*/ -#define LOCK_UNLOCK 0x1ACCE551U -#define LOCK_LOCK 0x00000000U - -#define LOCK_IS_UNLOCKED 0U -#define LOCK_IS_LOCKED 1U - -#define TEST_STALL (1 << 8) - -#define MIS_WDTMIS (1 << 0) -#define RIS_WDTRIS (1 << 0) -#define ICR_WDTICR (1 << 0) - -#define CTL_INTEN (1 << 0) -#define CTL_RESEN (1 << 1) -#define CTL_INTTYPE (1 << 2) -#define CTL_WRC (1 << 31) - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -146,7 +129,7 @@ struct WDGDriver /** * @brief Pointer to the WDT registers block. */ - WDT_TypeDef *wdt; + uint32_t wdt; }; /*===========================================================================*/ diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.c b/os/hal/ports/TIVA/LLD/hal_ext_lld.c deleted file mode 100644 index efe6421..0000000 --- a/os/hal/ports/TIVA/LLD/hal_ext_lld.c +++ /dev/null @@ -1,981 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Tiva/ext_lld.c - * @brief Tiva EXT subsystem low level driver source. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Generic interrupt serving code for multiple pins per interrupt - * handler. - */ -#define ext_lld_serve_port_interrupt(gpiop, start) \ - do { \ - uint32_t mis = gpiop->MIS; \ - \ - gpiop->ICR = mis; \ - \ - if (mis & (1 << 0)) { \ - EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0); \ - } \ - if (mis & (1 << 1)) { \ - EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1); \ - } \ - if (mis & (1 << 2)) { \ - EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2); \ - } \ - if (mis & (1 << 3)) { \ - EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3); \ - } \ - if (mis & (1 << 4)) { \ - EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4); \ - } \ - if (mis & (1 << 5)) { \ - EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5); \ - } \ - if (mis & (1 << 6)) { \ - EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6); \ - } \ - if (mis & (1 << 7)) { \ - EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7); \ - } \ - } while (0); - -/** - * @brief Generic interrupt serving code for single pin per interrupt - * handler. - */ -#define ext_lld_serve_pin_interrupt(gpiop, start, pin) \ - do { \ - gpiop->ICR = (1 << pin); \ - EXTD1.config->channels[start].cb(&EXTD1, start); \ - } while (0); - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EXTD1 driver identifier. - */ -EXTDriver EXTD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -const ioportid_t gpio[] = -{ -#if TIVA_HAS_GPIOA - GPIOA, -#endif -#if TIVA_HAS_GPIOB - GPIOB, -#endif -#if TIVA_HAS_GPIOC - GPIOC, -#endif -#if TIVA_HAS_GPIOD - GPIOD, -#endif -#if TIVA_HAS_GPIOE - GPIOE, -#endif -#if TIVA_HAS_GPIOF - GPIOF, -#endif -#if TIVA_HAS_GPIOG - GPIOG, -#endif -#if TIVA_HAS_GPIOH - GPIOH, -#endif -#if TIVA_HAS_GPIOJ - GPIOJ, -#endif -#if TIVA_HAS_GPIOK - GPIOK, -#endif -#if TIVA_HAS_GPIOL - GPIOL, -#endif -#if TIVA_HAS_GPIOM - GPIOM, -#endif -#if TIVA_HAS_GPION - GPION, -#endif -#if TIVA_HAS_GPIOP - GPIOP, -#endif -#if TIVA_HAS_GPIOQ - GPIOQ, -#endif -#if TIVA_HAS_GPIOR - GPIOR, -#endif -#if TIVA_HAS_GPIOS - GPIOS, -#endif -#if TIVA_HAS_GPIOT - GPIOT, -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Enables GPIO IRQ sources. - * - * @notapi - */ -static void ext_lld_irq_enable(void) -{ -#if TIVA_HAS_GPIOA - nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOB - nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOC - nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOD - nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOE - nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOF - nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOG - nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOH - nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOJ - nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOK - nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOL - nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOM - nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPION - nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOP - nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOQ - nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOR - nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOS - nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOT - nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY); -#endif -} - -/** - * @brief Disables GPIO IRQ sources. - * - * @notapi - */ -static void ext_lld_irq_disable(void) -{ -#if TIVA_HAS_GPIOA - nvicDisableVector(TIVA_GPIOA_NUMBER); -#endif -#if TIVA_HAS_GPIOB - nvicDisableVector(TIVA_GPIOB_NUMBER); -#endif -#if TIVA_HAS_GPIOC - nvicDisableVector(TIVA_GPIOC_NUMBER); -#endif -#if TIVA_HAS_GPIOD - nvicDisableVector(TIVA_GPIOD_NUMBER); -#endif -#if TIVA_HAS_GPIOE - nvicDisableVector(TIVA_GPIOE_NUMBER); -#endif -#if TIVA_HAS_GPIOF - nvicDisableVector(TIVA_GPIOF_NUMBER); -#endif -#if TIVA_HAS_GPIOG - nvicDisableVector(TIVA_GPIOG_NUMBER); -#endif -#if TIVA_HAS_GPIOH - nvicDisableVector(TIVA_GPIOH_NUMBER); -#endif -#if TIVA_HAS_GPIOJ - nvicDisableVector(TIVA_GPIOJ_NUMBER); -#endif -#if TIVA_HAS_GPIOK - nvicDisableVector(TIVA_GPIOK_NUMBER); -#endif -#if TIVA_HAS_GPIOL - nvicDisableVector(TIVA_GPIOL_NUMBER); -#endif -#if TIVA_HAS_GPIOM - nvicDisableVector(TIVA_GPIOM_NUMBER); -#endif -#if TIVA_HAS_GPION - nvicDisableVector(TIVA_GPION_NUMBER); -#endif -#if TIVA_HAS_GPIOP - nvicDisableVector(TIVA_GPIOP0_NUMBER); - nvicDisableVector(TIVA_GPIOP1_NUMBER); - nvicDisableVector(TIVA_GPIOP2_NUMBER); - nvicDisableVector(TIVA_GPIOP3_NUMBER); - nvicDisableVector(TIVA_GPIOP4_NUMBER); - nvicDisableVector(TIVA_GPIOP5_NUMBER); - nvicDisableVector(TIVA_GPIOP6_NUMBER); - nvicDisableVector(TIVA_GPIOP7_NUMBER); -#endif -#if TIVA_HAS_GPIOQ - nvicDisableVector(TIVA_GPIOQ0_NUMBER); - nvicDisableVector(TIVA_GPIOQ1_NUMBER); - nvicDisableVector(TIVA_GPIOQ2_NUMBER); - nvicDisableVector(TIVA_GPIOQ3_NUMBER); - nvicDisableVector(TIVA_GPIOQ4_NUMBER); - nvicDisableVector(TIVA_GPIOQ5_NUMBER); - nvicDisableVector(TIVA_GPIOQ6_NUMBER); - nvicDisableVector(TIVA_GPIOQ7_NUMBER); -#endif -#if TIVA_HAS_GPIOR - nvicDisableVector(TIVA_GPIOR_NUMBER); -#endif -#if TIVA_HAS_GPIOS - nvicDisableVector(TIVA_GPIOS_NUMBER); -#endif -#if TIVA_HAS_GPIOT - nvicDisableVector(TIVA_GPIOT_NUMBER); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) -/** - * @brief GPIOA interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOA, 0); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) -/** - * @brief GPIOB interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOB, 8); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) -/** - * @brief GPIOC interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOC, 16); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) -/** - * @brief GPIOD interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOD, 24); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) -/** - * @brief GPIOE interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOE, 32); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) -/** - * @brief GPIOF interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOF, 40); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) -/** - * @brief GPIOG interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOG, 48); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) -/** - * @brief GPIOH interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOH, 56); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) -/** - * @brief GPIOJ interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOJ, 64); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) -/** - * @brief GPIOK interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOK, 72); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) -/** - * @brief GPIOL interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOL, 80); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) -/** - * @brief GPIOM interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOM, 88); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) -/** - * @brief GPION interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPION, 96); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) -/** - * @brief GPIOP0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 104, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 105, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 106, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 107, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 108, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 109, 5); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 110, 6); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 111, 7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) -/** - * @brief GPIOQ0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 112, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 113, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 114, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 115, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 116, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 117, 5); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 118, 6); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 119, 7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) -/** - * @brief GPIOR interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOR, 120); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) -/** - * @brief GPIOS interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOS, 128); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) -/** - * @brief GPIOT interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOT, 132); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EXT driver initialization. - * - * @notapi - */ -void ext_lld_init(void) -{ - extObjectInit(&EXTD1); -} - -/** - * @brief Configures and activates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_start(EXTDriver *extp) -{ - uint8_t i; - - if (extp->state == EXT_STOP) { - ext_lld_irq_enable(); - } - - /* Configuration of automatic channels.*/ - for (i = 0; i < EXT_MAX_CHANNELS; i++) { - if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) { - ext_lld_channel_enable(extp, i); - } - else { - ext_lld_channel_disable(extp, i); - } - } -} - -/** - * @brief Deactivates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_stop(EXTDriver *extp) -{ - if (extp->state == EXT_ACTIVE) { - ext_lld_irq_disable(); - } - -#if TIVA_HAS_GPIOA - GPIOA->IM = 0; -#endif -#if TIVA_HAS_GPIOB - GPIOB->IM = 0; -#endif -#if TIVA_HAS_GPIOC - GPIOC->IM = 0; -#endif -#if TIVA_HAS_GPIOD - GPIOD->IM = 0; -#endif -#if TIVA_HAS_GPIOE - GPIOE->IM = 0; -#endif -#if TIVA_HAS_GPIOF - GPIOF->IM = 0; -#endif -#if TIVA_HAS_GPIOG - GPIOG->IM = 0; -#endif -#if TIVA_HAS_GPIOH - GPIOH->IM = 0; -#endif -#if TIVA_HAS_GPIOJ - GPIOJ->IM = 0; -#endif -#if TIVA_HAS_GPIOK - GPIOK->IM = 0; -#endif -#if TIVA_HAS_GPIOL - GPIOL->IM = 0; -#endif -#if TIVA_HAS_GPIOM - GPIOM->IM = 0; -#endif -#if TIVA_HAS_GPION - GPION->IM = 0; -#endif -#if TIVA_HAS_GPIOP - GPIOP->IM = 0; -#endif -#if TIVA_HAS_GPIOQ - GPIOQ->IM = 0; -#endif -#if TIVA_HAS_GPIOR - GPIOR->IM = 0; -#endif -#if TIVA_HAS_GPIOS - GPIOS->IM = 0; -#endif -#if TIVA_HAS_GPIOT - GPIOT->IM = 0; -#endif -} - -/** - * @brief Enables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @notapi - */ -void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) -{ - GPIO_TypeDef *gpiop; - uint8_t pin; - uint32_t im; - - pin = channel & 0x07; - gpiop = gpio[channel >> 3]; - - /* Disable interrupts */ - im = gpiop->IM; - gpiop->IM = 0; - - /* Configure pin to be edge-sensitive.*/ - gpiop->IS &= ~(1 << pin); - - /* Programming edge registers.*/ - if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_BOTH_EDGES) { - gpiop->IBE |= (1 << pin); - } - else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_FALLING_EDGE) { - gpiop->IBE &= ~(1 << pin); - gpiop->IEV &= ~(1 << pin); - } - else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_RISING_EDGE) { - gpiop->IBE &= ~(1 << pin); - gpiop->IEV |= (1 << pin); - } - - /* Programming interrupt and event registers.*/ - if ((extp->config->channels[channel].cb != NULL) && - ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) != - EXT_CH_MODE_DISABLED)) { - im |= (1 << pin); - } - else { - im &= ~(1 << pin); - } - - /* Restore interrupts */ - gpiop->IM = im; -} - -/** - * @brief Disables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @notapi - */ -void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) -{ - (void)extp; - GPIO_TypeDef *gpiop; - uint8_t pin; - - pin = channel & 0x07; - gpiop = gpio[channel >> 3]; - - gpiop->IM &= ~(1 << pin); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.h b/os/hal/ports/TIVA/LLD/hal_ext_lld.h deleted file mode 100644 index 08accb2..0000000 --- a/os/hal/ports/TIVA/LLD/hal_ext_lld.h +++ /dev/null @@ -1,523 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Tiva/ext_lld.h - * @brief Tiva EXT subsystem low level driver header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef HAL_EXT_LLD_H -#define HAL_EXT_LLD_H - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of EXT per port. - */ -#define EXT_MAX_CHANNELS TIVA_GPIO_PINS - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief GPIOA interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOA_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOB interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOB_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOC interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOC_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOD interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOD_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOE interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOE_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOF interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOF_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOG interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOG_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOH interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOH_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOJ interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOJ_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOK interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOK_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOL interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOL_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOM interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOM_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPION interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPION_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP0 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP0_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP1 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP1_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP2 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP2_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP3 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP3_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP4 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP4_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP5 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP5_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP6 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP6_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP7 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP7_IRQ_PRIORITY 3 -#endif -/** @} */ - -/** - * @brief GPIOQ0 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ1 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ2 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ3 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ4 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ5 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ6 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ7 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOR interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOR_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOS interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOS_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOT interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOT_IRQ_PRIORITY 3 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOA" -#endif - -#if TIVA_HAS_GPIOB && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOB" -#endif - -#if TIVA_HAS_GPIOC && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOC" -#endif - -#if TIVA_HAS_GPIOD && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOD" -#endif - -#if TIVA_HAS_GPIOE && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOE" -#endif - -#if TIVA_HAS_GPIOF && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOF" -#endif - -#if TIVA_HAS_GPIOG && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOG" -#endif - -#if TIVA_HAS_GPIOH && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOH" -#endif - -#if TIVA_HAS_GPIOJ && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOJ" -#endif - -#if TIVA_HAS_GPIOK && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOK" -#endif - -#if TIVA_HAS_GPIOL && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOL" -#endif - -#if TIVA_HAS_GPIOM && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOM" -#endif - -#if TIVA_HAS_GPION && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPION" -#endif - -#if TIVA_HAS_GPIOP0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP0" -#endif - -#if TIVA_HAS_GPIOP1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP1" -#endif - -#if TIVA_HAS_GPIOP2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP2" -#endif - -#if TIVA_HAS_GPIOP3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP3" -#endif - -#if TIVA_HAS_GPIOP4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP4" -#endif - -#if TIVA_HAS_GPIOP5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP5" -#endif - -#if TIVA_HAS_GPIOP6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP6" -#endif - -#if TIVA_HAS_GPIOP7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP7" -#endif - -#if TIVA_HAS_GPIOQ0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ0" -#endif - -#if TIVA_HAS_GPIOQ1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ1" -#endif - -#if TIVA_HAS_GPIOQ2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ2" -#endif - -#if TIVA_HAS_GPIOQ3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ3" -#endif - -#if TIVA_HAS_GPIOQ4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ4" -#endif - -#if TIVA_HAS_GPIOQ5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ5" -#endif - -#if TIVA_HAS_GPIOQ6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ6" -#endif - -#if TIVA_HAS_GPIOQ7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ7" -#endif - -#if TIVA_HAS_GPIOR && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOR" -#endif - -#if TIVA_HAS_GPIOS && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOS" -#endif - -#if TIVA_HAS_GPIOT && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOT" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief EXT channel identifier. - */ -typedef uint32_t expchannel_t; - -/** - * @brief Type of an EXT generic notification callback. - * - * @param[in] extp pointer to the @p EXPDriver object triggering the - * callback - */ -typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); - -/** - * @brief Channel configuration structure. - */ -typedef struct { - /** - * @brief Channel mode. - */ - uint32_t mode; - /** - * @brief Channel callback. - */ - extcallback_t cb; -} EXTChannelConfig; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Channel configurations. - */ - EXTChannelConfig channels[EXT_MAX_CHANNELS]; - /* End of the mandatory fields.*/ -} EXTConfig; - -/** - * @brief Structure representing an EXT driver. - */ -struct EXTDriver { - /** - * @brief Driver state. - */ - extstate_t state; - /** - * @brief Current configuration data. - */ - const EXTConfig *config; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern EXTDriver EXTD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_init(void); - void ext_lld_start(EXTDriver *extp); - void ext_lld_stop(EXTDriver *extp); - void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); - void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* HAL_EXT_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/hal_pal_lld.c deleted file mode 100644 index 5460fd4..0000000 --- a/os/hal/ports/TIVA/LLD/hal_pal_lld.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/pal_lld.c - * @brief TM4C123x/TM4C129x PAL subsystem low level driver. - * - * @addtogroup PAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) -#define GPIOA_BIT (1 << 0) -#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x) -#define GPIOA_AHB_BIT (1 << 0) -#else -#define GPIOA_AHB_BIT 0 -#endif -#else -#define GPIOA_BIT 0 -#define GPIOA_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) -#define GPIOB_BIT (1 << 1) -#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x) -#define GPIOB_AHB_BIT (1 << 1) -#else -#define GPIOB_AHB_BIT 0 -#endif -#else -#define GPIOB_BIT 0 -#define GPIOB_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) -#define GPIOC_BIT (1 << 2) -#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x) -#define GPIOC_AHB_BIT (1 << 2) -#else -#define GPIOC_AHB_BIT 0 -#endif -#else -#define GPIOC_BIT 0 -#define GPIOC_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) -#define GPIOD_BIT (1 << 3) -#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x) -#define GPIOD_AHB_BIT (1 << 3) -#else -#define GPIOD_AHB_BIT 0 -#endif -#else -#define GPIOD_BIT 0 -#define GPIOD_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) -#define GPIOE_BIT (1 << 4) -#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x) -#define GPIOE_AHB_BIT (1 << 4) -#else -#define GPIOE_AHB_BIT 0 -#endif -#else -#define GPIOE_BIT 0 -#define GPIOE_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) -#define GPIOF_BIT (1 << 5) -#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x) -#define GPIOF_AHB_BIT (1 << 5) -#else -#define GPIOF_AHB_BIT 0 -#endif -#else -#define GPIOF_BIT 0 -#define GPIOF_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) -#define GPIOG_BIT (1 << 6) -#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x) -#define GPIOG_AHB_BIT (1 << 6) -#else -#define GPIOG_AHB_BIT 0 -#endif -#else -#define GPIOG_BIT 0 -#define GPIOG_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) -#define GPIOH_BIT (1 << 7) -#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x) -#define GPIOH_AHB_BIT (1 << 7) -#else -#define GPIOH_AHB_BIT 0 -#endif -#else -#define GPIOH_BIT 0 -#define GPIOH_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) -#define GPIOJ_BIT (1 << 8) -#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) -#define GPIOJ_AHB_BIT (1 << 8) -#else -#define GPIOJ_AHB_BIT 0 -#endif -#else -#define GPIOJ_BIT 0 -#define GPIOJ_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) -#define GPIOK_BIT (1 << 9) -#define GPIOK_AHB_BIT (1 << 9) -#else -#define GPIOK_BIT 0 -#define GPIOK_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) -#define GPIOL_BIT (1 << 10) -#define GPIOL_AHB_BIT (1 << 10) -#else -#define GPIOL_BIT 0 -#define GPIOL_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) -#define GPIOM_BIT (1 << 11) -#define GPIOM_AHB_BIT (1 << 11) -#else -#define GPIOM_BIT 0 -#define GPIOM_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) -#define GPION_BIT (1 << 12) -#define GPION_AHB_BIT (1 << 12) -#else -#define GPION_BIT 0 -#define GPION_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) -#define GPIOP_BIT (1 << 13) -#define GPIOP_AHB_BIT (1 << 13) -#else -#define GPIOP_BIT 0 -#define GPIOP_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) -#define GPIOQ_BIT (1 << 14) -#define GPIOQ_AHB_BIT (1 << 14) -#else -#define GPIOQ_BIT 0 -#define GPIOQ_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) -#define GPIOR_BIT (1 << 15) -#define GPIOR_AHB_BIT (1 << 15) -#else -#define GPIOR_BIT 0 -#define GPIOR_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) -#define GPIOS_BIT (1 << 16) -#define GPIOS_AHB_BIT (1 << 16) -#else -#define GPIOS_BIT 0 -#define GPIOS_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) -#define GPIOT_BIT (1 << 17) -#define GPIOT_AHB_BIT (1 << 17) -#else -#define GPIOT_BIT 0 -#define GPIOT_AHB_BIT 0 -#endif - -#define RCGCGPIO_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ - GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ - GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT | \ - GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT | \ - GPIOS_BIT | GPIOR_BIT) - -#define GPIOHBCTL_MASK (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT | \ - GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT | \ - GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT | \ - GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT | \ - GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT | \ - GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT) - -/* GPIO lock password.*/ -#define TIVA_GPIO_LOCK_PWD 0x4C4F434B - -#define GPIOC_JTAG_MASK (0x0F) -#define GPIOD_NMI_MASK (0x80) -#define GPIOF_NMI_MASK (0x01) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the port with the port configuration. - * - * @param[in] port the port identifier - * @param[in] config the port configuration - */ -static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config) -{ - port->DATA = config->data; - port->DIR = config->dir; - port->AFSEL = config->afsel; - port->DR2R = config->dr2r; - port->DR4R = config->dr4r; - port->DR8R = config->dr8r; - port->ODR = config->odr; - port->PUR = config->pur; - port->PDR = config->pdr; - port->SLR = config->slr; - port->DEN = config->den; - port->AMSEL = config->amsel; - port->PCTL = config->pctl; -} - -/** - * @brief Unlocks the masked pins of the GPIO peripheral. - * @note This function is only useful for PORTC0-3, PORTD7 and PORTF0. - * - * @param[in] port the port identifier - * @param[in] mask the pin mask - */ -static void gpio_unlock(ioportid_t port, ioportmask_t mask) -{ - port->LOCK = TIVA_GPIO_LOCK_PWD; - port->CR = mask; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Tiva I/O ports configuration. - * @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled. - * - * @param[in] config the Tiva ports configuration - * - * @notapi - */ -void _pal_lld_init(const PALConfig *config) -{ - /* - * Enables all GPIO clocks. - */ - SYSCTL->RCGCGPIO = RCGCGPIO_MASK; -#if defined(TM4C123x) - SYSCTL->GPIOHBCTL = GPIOHBCTL_MASK; -#endif - - /* Wait until all GPIO modules are ready */ - while (!((SYSCTL->PRGPIO & RCGCGPIO_MASK) == RCGCGPIO_MASK)) - ; - -#if TIVA_HAS_GPIOA - gpio_init(GPIOA, &config->PAData); -#endif -#if TIVA_HAS_GPIOB - gpio_init(GPIOB, &config->PBData); -#endif -#if TIVA_HAS_GPIOC - /* Unlock JTAG pins.*/ - gpio_unlock(GPIOC, GPIOC_JTAG_MASK); - gpio_init(GPIOC, &config->PCData); -#endif -#if TIVA_HAS_GPIOD - /* Unlock NMI pin.*/ - gpio_unlock(GPIOD, GPIOD_NMI_MASK); - gpio_init(GPIOD, &config->PDData); -#endif -#if TIVA_HAS_GPIOE - gpio_init(GPIOE, &config->PEData); -#endif -#if TIVA_HAS_GPIOF - /* Unlock NMI pin.*/ - gpio_unlock(GPIOF, GPIOF_NMI_MASK); - gpio_init(GPIOF, &config->PFData); -#endif -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) - gpio_init(GPIOG, &config->PGData); -#endif -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) - gpio_init(GPIOH, &config->PHData); -#endif -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_init(GPIOJ, &config->PJData); -#endif -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) - gpio_init(GPIOK, &config->PKData); -#endif -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) - gpio_init(GPIOL, &config->PLData); -#endif -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) - gpio_init(GPIOM, &config->PMData); -#endif -#if TIVA_HAS_GPION || defined(__DOXYGEN__) - gpio_init(GPION, &config->PNData); -#endif -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) - gpio_init(GPIOP, &config->PPData); -#endif -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) - gpio_init(GPIOQ, &config->PQData); -#endif -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) - gpio_init(GPIOR, &config->PRData); -#endif -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) - gpio_init(GPIOS, &config->PSData); -#endif -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) - gpio_init(GPIOT, &config->PTData); -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) -{ - uint32_t dir = (mode & PAL_TIVA_DIR_MASK) >> 0; - uint32_t afsel = (mode & PAL_TIVA_AFSEL_MASK) >> 1; - uint32_t dr2r = (mode & PAL_TIVA_DR2R_MASK) >> 2; - uint32_t dr4r = (mode & PAL_TIVA_DR4R_MASK) >> 3; - uint32_t dr8r = (mode & PAL_TIVA_DR8R_MASK) >> 4; - uint32_t odr = (mode & PAL_TIVA_ODR_MASK) >> 5; - uint32_t pur = (mode & PAL_TIVA_PUR_MASK) >> 6; - uint32_t pdr = (mode & PAL_TIVA_PDR_MASK) >> 7; - uint32_t slr = (mode & PAL_TIVA_SLR_MASK) >> 8; - uint32_t den = (mode & PAL_TIVA_DEN_MASK) >> 9; - uint32_t amsel = (mode & PAL_TIVA_AMSEL_MASK) >> 10; - uint32_t pctl = (mode & PAL_TIVA_PCTL_MASK) >> 11; - uint32_t bit = 0; - - while(TRUE) { - uint32_t pctl_mask = (7 << (4 * bit)); - uint32_t bit_mask = (1 << bit); - - if ((mask & 1) != 0) { - port->DIR = (port->DIR & ~bit_mask) | dir; - port->AFSEL = (port->AFSEL & ~bit_mask) | afsel; - port->DR2R = (port->DR2R & ~bit_mask) | dr2r; - port->DR4R = (port->DR4R & ~bit_mask) | dr4r; - port->DR8R = (port->DR8R & ~bit_mask) | dr8r; - port->ODR = (port->ODR & ~bit_mask) | odr; - port->PUR = (port->PUR & ~bit_mask) | pur; - port->PDR = (port->PDR & ~bit_mask) | pdr; - port->SLR = (port->SLR & ~bit_mask) | slr; - port->DEN = (port->DEN & ~bit_mask) | den; - port->AMSEL = (port->AMSEL & ~bit_mask) | amsel; - port->PCTL = (port->PCTL & ~pctl_mask) | pctl; - } - - mask >>= 1; - if (!mask) { - return; - } - - dir <<= 1; - afsel <<= 1; - dr2r <<= 1; - dr4r <<= 1; - dr8r <<= 1; - odr <<= 1; - pur <<= 1; - pdr <<= 1; - slr <<= 1; - den <<= 1; - amsel <<= 1; - pctl <<= 4; - - bit++; - } -} - -#endif /* HAL_USE_PAL */ - -/** - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/hal_pal_lld.h deleted file mode 100644 index c0cd82b..0000000 --- a/os/hal/ports/TIVA/LLD/hal_pal_lld.h +++ /dev/null @@ -1,762 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/pal_lld.h - * @brief TM4C123x/TM4C129x PAL subsystem low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef HAL_PAL_LLD_H -#define HAL_PAL_LLD_H - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#undef PAL_MODE_RESET -#undef PAL_MODE_UNCONNECTED -#undef PAL_MODE_INPUT -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_INPUT_ANALOG -#undef PAL_MODE_OUTPUT_PUSHPULL -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/** - * @name TIVA-specific I/O mode flags - * @{ - */ -#define PAL_TIVA_DIR_MASK (1 << 0) -#define PAL_TIVA_DIR_INPUT (0 << 0) -#define PAL_TIVA_DIR_OUTPUT (1 << 0) - -#define PAL_TIVA_AFSEL_MASK (1 << 1) -#define PAL_TIVA_AFSEL_GPIO (0 << 1) -#define PAL_TIVA_AFSEL_ALTERNATE (1 << 1) - -#define PAL_TIVA_DR2R_MASK (1 << 2) -#define PAL_TIVA_DR2R_DISABLE (0 << 2) -#define PAL_TIVA_DR2R_ENABLE (1 << 2) - -#define PAL_TIVA_DR4R_MASK (1 << 3) -#define PAL_TIVA_DR4R_DISABLE (0 << 3) -#define PAL_TIVA_DR4R_ENABLE (1 << 3) - -#define PAL_TIVA_DR8R_MASK (1 << 4) -#define PAL_TIVA_DR8R_DISABLE (0 << 4) -#define PAL_TIVA_DR8R_ENABLE (1 << 4) - -#define PAL_TIVA_ODR_MASK (1 << 5) -#define PAL_TIVA_ODR_PUSHPULL (0 << 5) -#define PAL_TIVA_ODR_OPENDRAIN (1 << 5) - -#define PAL_TIVA_PUR_MASK (1 << 6) -#define PAL_TIVA_PUR_DISABLE (0 << 6) -#define PAL_TIVA_PUR_ENABLE (1 << 6) - -#define PAL_TIVA_PDR_MASK (1 << 7) -#define PAL_TIVA_PDR_DISABLE (0 << 7) -#define PAL_TIVA_PDR_ENABLE (1 << 7) - -#define PAL_TIVA_SLR_MASK (1 << 8) -#define PAL_TIVA_SLR_DISABLE (0 << 8) -#define PAL_TIVA_SLR_ENABLE (1 << 8) - -#define PAL_TIVA_DEN_MASK (1 << 9) -#define PAL_TIVA_DEN_DISABLE (0 << 9) -#define PAL_TIVA_DEN_ENABLE (1 << 9) - -#define PAL_TIVA_AMSEL_MASK (1 << 10) -#define PAL_TIVA_AMSEL_DISABLE (0 << 10) -#define PAL_TIVA_AMSEL_ENABLE (1 << 10) - -#define PAL_TIVA_PCTL_MASK (7 << 11) -#define PAL_TIVA_PCTL(n) ((n) << 11) - -/** - * @brief Alternate function. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALTERNATE(n) (PAL_TIVA_AFSEL_ALTERNATE | \ - PAL_TIVA_PCTL(n)) -/** - * @} - */ - -/** - * @name Standard I/O mode flags - * @{ - */ -/** - * @brief This mode is implemented as input. - */ -#define PAL_MODE_RESET PAL_MODE_INPUT - -/** - * @brief This mode is implemented as input with pull-up. - */ -#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP - -/** - * @brief Regular input high-Z pad. - */ -#define PAL_MODE_INPUT (PAL_TIVA_DEN_ENABLE | \ - PAL_TIVA_DIR_INPUT) - -/** - * @brief Input pad with weak pull up resistor. - */ -#define PAL_MODE_INPUT_PULLUP (PAL_TIVA_DIR_INPUT | \ - PAL_TIVA_PUR_ENABLE | \ - PAL_TIVA_DEN_ENABLE) - -/** - * @brief Input pad with weak pull down resistor. - */ -#define PAL_MODE_INPUT_PULLDOWN (PAL_TIVA_DIR_INPUT | \ - PAL_TIVA_PDR_ENABLE | \ - PAL_TIVA_DEN_ENABLE) - -/** - * @brief Analog input mode. - */ -#define PAL_MODE_INPUT_ANALOG (PAL_TIVA_DEN_DISABLE | \ - PAL_TIVA_AMSEL_ENABLE) - -/** - * @brief Push-pull output pad. - */ -#define PAL_MODE_OUTPUT_PUSHPULL (PAL_TIVA_DIR_OUTPUT | \ - PAL_TIVA_DR2R_ENABLE | \ - PAL_TIVA_ODR_PUSHPULL | \ - PAL_TIVA_DEN_ENABLE) - -/** - * @brief Open-drain output pad. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_TIVA_DIR_OUTPUT | \ - PAL_TIVA_DR2R_ENABLE | \ - PAL_TIVA_ODR_OPENDRAIN | \ - PAL_TIVA_DEN_ENABLE) -/** - * @} - */ - -/** @brief GPIOA port identifier.*/ -#define IOPORT1 GPIOA - -/** @brief GPIOB port identifier.*/ -#define IOPORT2 GPIOB - -/** @brief GPIOC port identifier.*/ -#define IOPORT3 GPIOC - -/** @brief GPIOD port identifier.*/ -#define IOPORT4 GPIOD - -/** @brief GPIOE port identifier.*/ -#define IOPORT5 GPIOE - -/** @brief GPIOF port identifier.*/ -#define IOPORT6 GPIOF - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) -/** @brief Port G setup data.*/ -#define IOPORT7 GPIOG -#endif /* TIVA_HAS_GPIOG.*/ - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) -/** @brief Port H setup data.*/ -#define IOPORT8 GPIOH -#endif /* TIVA_HAS_GPIOH.*/ - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) -/** @brief Port J setup data.*/ -#define IOPORT9 GPIOJ -#endif /* TIVA_HAS_GPIOJ.*/ - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) -/** @brief Port K setup data.*/ -#define IOPORT10 GPIOK -#endif /* TIVA_HAS_GPIOK.*/ - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) -/** @brief Port L setup data.*/ -#define IOPORT11 GPIOL -#endif /* TIVA_HAS_GPIOL.*/ - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) -/** @brief Port M setup data.*/ -#define IOPORT12 GPIOM -#endif /* TIVA_HAS_GPIOM.*/ - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) -/** @brief Port N setup data.*/ -#define IOPORT13 GPION -#endif /* TIVA_HAS_GPION.*/ - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) -/** @brief Port P setup data.*/ -#define IOPORT14 GPIOP -#endif /* TIVA_HAS_GPIOP.*/ - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) -/** @brief Port Q setup data.*/ -#define IOPORT15 GPIOQ -#endif /* TIVA_HAS_GPIOQ.*/ - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) -/** @brief Port R setup data.*/ -#define IOPORT16 GPIOR -#endif /* TIVA_HAS_GPIOR.*/ - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) -/** @brief Port S setup data.*/ -#define IOPORT17 GPIOS -#endif /* TIVA_HAS_GPIOS.*/ - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) -/** @brief Port T setup data.*/ -#define IOPORT18 GPIOT -#endif /* TIVA_HAS_GPIOT.*/ - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 8 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -#if defined(TM4C123x) - -/** - * @brief GPIOA AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set - * to @p FALSE the APB bus is used to access GPIOA. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOA_USE_AHB TRUE -#endif - -/** - * @brief GPIOB AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set - * to @p FALSE the APB bus is used to access GPIOB. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOB_USE_AHB TRUE -#endif - -/** - * @brief GPIOC AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set - * to @p FALSE the APB bus is used to access GPIOC. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOC_USE_AHB TRUE -#endif - -/** - * @brief GPIOD AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set - * to @p FALSE the APB bus is used to access GPIOD. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOD_USE_AHB TRUE -#endif - -/** - * @brief GPIOE AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set - * to @p FALSE the APB bus is used to access GPIOE. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOE_USE_AHB TRUE -#endif - -/** - * @brief GPIOF AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set - * to @p FALSE the APB bus is used to access GPIOF. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOF_USE_AHB TRUE -#endif - -/** - * @brief GPIOG AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set - * to @p FALSE the APB bus is used to access GPIOG. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOG_USE_AHB TRUE -#endif - -/** - * @brief GPIOH AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set - * to @p FALSE the APB bus is used to access GPIOH. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOH_USE_AHB TRUE -#endif - -/** - * @brief GPIOJ AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set - * to @p FALSE the APB bus is used to access GPIOJ. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOJ_USE_AHB TRUE -#endif - -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if defined(TM4C123x) - -#if TIVA_GPIO_GPIOA_USE_AHB -#define GPIOA GPIOA_AHB -#else -#define GPIOA GPIOA_APB -#endif - -#if TIVA_GPIO_GPIOB_USE_AHB -#define GPIOB GPIOB_AHB -#else -#define GPIOB GPIOB_APB -#endif - -#if TIVA_GPIO_GPIOC_USE_AHB -#define GPIOC GPIOC_AHB -#else -#define GPIOC GPIOC_APB -#endif - -#if TIVA_GPIO_GPIOD_USE_AHB -#define GPIOD GPIOD_AHB -#else -#define GPIOD GPIOD_APB -#endif - -#if TIVA_GPIO_GPIOE_USE_AHB -#define GPIOE GPIOE_AHB -#else -#define GPIOE GPIOE_APB -#endif - -#if TIVA_GPIO_GPIOF_USE_AHB -#define GPIOF GPIOF_AHB -#else -#define GPIOF GPIOF_APB -#endif - -#if TIVA_GPIO_GPIOG_USE_AHB -#define GPIOG GPIOG_AHB -#else -#define GPIOG GPIOG_APB -#endif - -#if TIVA_GPIO_GPIOH_USE_AHB -#define GPIOH GPIOH_AHB -#else -#define GPIOH GPIOH_APB -#endif - -#if TIVA_GPIO_GPIOJ_USE_AHB -#define GPIOJ GPIOJ_AHB -#else -#define GPIOJ GPIOJ_APB -#endif - -#define GPIOK GPIOK_AHB -#define GPIOL GPIOL_AHB -#define GPIOM GPIOM_AHB -#define GPION GPION_AHB -#define GPIOP GPIOP_AHB -#define GPIOQ GPIOQ_AHB - -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief GPIO port setup info. - */ -typedef struct -{ - /** @brief Initial value for DATA register.*/ - uint32_t data; - /** @brief Initial value for DIR register.*/ - uint32_t dir; - /** @brief Initial value for AFSEL register.*/ - uint32_t afsel; - /** @brief Initial value for DR2R register.*/ - uint32_t dr2r; - /** @brief Initial value for DR4R register.*/ - uint32_t dr4r; - /** @brief Initial value for DR8R register.*/ - uint32_t dr8r; - /** @brief Initial value for ODR register.*/ - uint32_t odr; - /** @brief Initial value for PUR register.*/ - uint32_t pur; - /** @brief Initial value for PDR register.*/ - uint32_t pdr; - /** @brief Initial value for SLR register.*/ - uint32_t slr; - /** @brief Initial value for DEN register.*/ - uint32_t den; - /** @brief Initial value for AMSEL register.*/ - uint32_t amsel; - /** @brief Initial value for PCTL register.*/ - uint32_t pctl; -} tiva_gpio_setup_t; - -/** - * @brief Tiva GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct -{ - /** @brief Port A setup data.*/ - tiva_gpio_setup_t PAData; - /** @brief Port B setup data.*/ - tiva_gpio_setup_t PBData; - /** @brief Port C setup data.*/ - tiva_gpio_setup_t PCData; - /** @brief Port D setup data.*/ - tiva_gpio_setup_t PDData; - /** @brief Port E setup data.*/ - tiva_gpio_setup_t PEData; - /** @brief Port F setup data.*/ - tiva_gpio_setup_t PFData; - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) - /** @brief Port G setup data.*/ - tiva_gpio_setup_t PGData; -#endif /* TIVA_HAS_GPIOG.*/ - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) - /** @brief Port H setup data.*/ - tiva_gpio_setup_t PHData; -#endif /* TIVA_HAS_GPIOH.*/ - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) - /** @brief Port J setup data.*/ - tiva_gpio_setup_t PJData; -#endif /* TIVA_HAS_GPIOJ.*/ - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) - /** @brief Port K setup data.*/ - tiva_gpio_setup_t PKData; -#endif /* TIVA_HAS_GPIOK.*/ - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) - /** @brief Port L setup data.*/ - tiva_gpio_setup_t PLData; -#endif /* TIVA_HAS_GPIOL.*/ - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) - /** @brief Port M setup data.*/ - tiva_gpio_setup_t PMData; -#endif /* TIVA_HAS_GPIOM.*/ - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) - /** @brief Port N setup data.*/ - tiva_gpio_setup_t PNData; -#endif /* TIVA_HAS_GPION.*/ - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) - /** @brief Port P setup data.*/ - tiva_gpio_setup_t PPData; -#endif /* TIVA_HAS_GPIOP.*/ - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) - /** @brief Port Q setup data.*/ - tiva_gpio_setup_t PQData; -#endif /* TIVA_HAS_GPIOQ.*/ - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) - /** @brief Port R setup data.*/ - tiva_gpio_setup_t PRData; -#endif /* TIVA_HAS_GPIOR.*/ - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) - /** @brief Port S setup data.*/ - tiva_gpio_setup_t PSData; -#endif /* TIVA_HAS_GPIOS.*/ - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) - /** @brief Port T setup data.*/ - tiva_gpio_setup_t PTData; -#endif /* TIVA_HAS_GPIOT.*/ -} PALConfig; - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Port Identifier. - */ -typedef GPIO_TypeDef *ioportid_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->DATA) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->DATA) - -/** - * @brief Writes a bits mask on a I/O port. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFF) - -/** - * @brief Clears a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) - -/** - * @brief Reads a group of bits. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @return The group logical states. - * - * @notapi - */ -#define pal_lld_readgroup(port, mask, offset) \ - ((port)->MASKED_ACCESS[(mask) << (offset)]) - -/** - * @brief Writes a group of bits. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group width - * are masked. - * - * @notapi - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -/** - * @brief Reads a logical state from an I/O pad. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @return The logical state. - * @retval PAL_LOW low logical state. - * @retval PAL_HIGH high logical state. - * - * @notapi - */ -#define pal_lld_readpad(port, pad) ((port)->MASKED_ACCESS[1 << (pad)]) - -/** - * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) \ - ((port)->MASKED_ACCESS[1 << (pad)] = (bit)) - -/** - * @brief Sets a pad logical state to @p PAL_HIGH. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_setpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) - -/** - * @brief Clears a pad logical state to @p PAL_LOW. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_clearpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 0) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* HAL_PAL_LLD_H */ - -/** - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/tiva_gpt.h b/os/hal/ports/TIVA/LLD/tiva_gpt.h deleted file mode 100644 index 114831b..0000000 --- a/os/hal/ports/TIVA/LLD/tiva_gpt.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file tiva_gpt.h - * @brief TIVA GPT registers layout header. - * - * @addtogroup TIVA_GPT - * @{ - */ - -#ifndef TIVA_GPT_H_ -#define TIVA_GPT_H_ - -// cfg -#define GPTM_CFG_CFG_MASK (7 << 0) -#define GPTM_CFG_CFG_WHOLE (0 << 0) -#define GPTM_CFG_CFG_RTC (1 << 0) -#define GPTM_CFG_CFG_SPLIT (4 << 0) - -// tamr -#define GPTM_TAMR_TAMR_MASK (3 << 0) -#define GPTM_TAMR_TAMR_ONESHOT (1 << 0) -#define GPTM_TAMR_TAMR_PERIODIC (2 << 0) -#define GPTM_TAMR_TAMR_CAPTURE (3 << 0) - -#define GPTM_TAMR_TACMR (1 << 2) - -#define GPTM_TAMR_TAAMS (1 << 3) - -#define GPTM_TAMR_TACDIR (1 << 4) - -#define GPTM_TAMR_TAMIE (1 << 5) - -#define GPTM_TAMR_TAWOT (1 << 6) - -#define GPTM_TAMR_TASNAPS (1 << 7) - -#define GPTM_TAMR_TAILD (1 << 8) - -#define GPTM_TAMR_TAPWMIE (1 << 9) - -#define GPTM_TAMR_TAMRSU (1 << 10) - -#define GPTM_TAMR_TAPLO (1 << 11) - -// ctl -#define GPTM_CTL_TAEN (1 << 0) - -#define GPTM_CTL_TASTALL (1 << 1) - -#define GPTM_CTL_TAEVENT_MASK (3 << 2) -#define GPTM_CTL_TAEVENT_POS (0 << 2) -#define GPTM_CTL_TAEVENT_NEG (1 << 2) -#define GPTM_CTL_TAEVENT_BOTH (3 << 2) - -#define GPTM_CTL_RTCEN (1 << 4) - -#define GPTM_CTL_TAOTE (1 << 5) - -#define GPTM_CTL_TAPWML (1 << 6) - -#define GPTM_CTL_TBEN (1 << 8) - -#define GPTM_CTL_TBSTALL (1 << 9) - -#define GPTM_CTL_TBEVENT_MASK (3 << 10) -#define GPTM_CTL_TBEVENT_POS (0 << 10) -#define GPTM_CTL_TBEVENT_NEG (1 << 10) -#define GPTM_CTL_TBEVENT_BOTH (3 << 10) - -#define GPTM_CTL_TBOTE (1 << 13) - -#define GPTM_CTL_TBPWML (1 << 14) - -// imr -#define GPTM_IMR_TATOIM (1 << 0) - -#define GPTM_IMR_CAMIM (1 << 1) - -#define GPTM_IMR_CAEIM (1 << 2) - -#define GPTM_IMR_RTCIM (1 << 3) - -#define GPTM_IMR_TAMIM (1 << 4) - -#define GPTM_IMR_TBTOIM (1 << 8) - -#define GPTM_IMR_CBMIM (1 << 9) - -#define GPTM_IMR_CBEIM (1 << 10) - -#define GPTM_IMR_TBMIM (1 << 11) - -#define GPTM_IMR_WUEIM (1 << 16) - -// icr -#define GPTM_ICR_TATOCINT (1 << 0) - -#define GPTM_ICR_CAMCINT (1 << 1) - -#define GPTM_ICR_CAECINT (1 << 2) - -#define GPTM_ICR_RTCCINT (1 << 3) - -#define GPTM_ICR_TAMCINT (1 << 4) - -#define GPTM_ICR_TBTOCINT (1 << 8) - -#define GPTM_ICR_CBMCINT (1 << 9) - -#define GPTM_ICR_CBECINT (1 << 10) - -#define GPTM_ICR_TBMCINT (1 << 11) - -#define GPTM_ICR_WUECINT (1 << 16) - -#endif /* TIVA_GPT_H_ */ - -/* - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/uDMA/driver.mk b/os/hal/ports/TIVA/LLD/uDMA/driver.mk new file mode 100644 index 0000000..3a2d929 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/uDMA/driver.mk @@ -0,0 +1,2 @@ +PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c +PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.c b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c index 9f122b2..2d18ff5 100644 --- a/os/hal/ports/TIVA/LLD/tiva_udma.c +++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,6 +14,14 @@ limitations under the License. */ +/** + * @file uDMA/tiva_udma.c + * @brief DMA helper driver code. + * + * @addtogroup TIVA_DMA + * @{ + */ + #include "hal.h" /* The following macro is only defined if some driver requiring DMA services @@ -75,8 +83,8 @@ OSAL_IRQ_HANDLER(TIVA_UDMA_ERR_HANDLER) /* TODO Do we need to halt the system on a DMA error?*/ - if (UDMA->ERRCLR) { - UDMA->ERRCLR = 1; + if (HWREG(UDMA_ERRCLR)) { + HWREG(UDMA_ERRCLR) = 1; } OSAL_IRQ_EPILOGUE(); @@ -96,18 +104,18 @@ void udmaInit(void) udma_channel_mask = 0; /* Enable UDMA module.*/ - SYSCTL->RCGCDMA = 1; - while (!(SYSCTL->PRDMA & (1 << 0))) + HWREG(SYSCTL_RCGCDMA) = 1; + while (!(HWREG(SYSCTL_PRDMA) & (1 << 0))) ; nvicEnableVector(TIVA_UDMA_ERR_NUMBER, TIVA_UDMA_ERR_IRQ_PRIORITY); nvicEnableVector(TIVA_UDMA_SW_NUMBER, TIVA_UDMA_SW_IRQ_PRIORITY); /* Enable UDMA controller.*/ - UDMA->CFG = 1; + HWREG(UDMA_CFG) = UDMA_CFG_MASTEN; /* Set address of control table.*/ - UDMA->CTLBASE = (uint32_t)udmaControlTable.primary; + HWREG(UDMA_CTLBASE) = (uint32_t)udmaControlTable.primary; } /** @@ -139,3 +147,5 @@ void udmaChannelRelease(uint8_t dmach) } #endif + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.h b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h index 6479b08..a473f6c 100644 --- a/os/hal/ports/TIVA/LLD/tiva_udma.h +++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,6 +14,14 @@ limitations under the License. */ +/** + * @file uDMA/tiva_udma.h + * @brief DMA helper driver header. + * + * @addtogroup TIVA_DMA + * @{ + */ + #ifndef TIVA_UDMA_H_ #define TIVA_UDMA_H_ @@ -22,52 +30,9 @@ /*===========================================================================*/ /** - * @name CHCTL register defines. - * @{ + * @brief CHCTL XFERSIZE helper. */ -#define UDMA_CHCTL_DSTINC_MASK 0xC0000000 -#define UDMA_CHCTL_DSTINC_0 0xC0000000 -#define UDMA_CHCTL_DSTINC_8 0x00000000 -#define UDMA_CHCTL_DSTINC_16 0x40000000 -#define UDMA_CHCTL_DSTINC_32 0x80000000 -#define UDMA_CHCTL_DSTSIZE_MASK 0x30000000 -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 -#define UDMA_CHCTL_SRCINC_MASK 0x0C000000 -#define UDMA_CHCTL_SRCINC_0 0x0C000000 -#define UDMA_CHCTL_SRCINC_8 0x00000000 -#define UDMA_CHCTL_SRCINC_16 0x04000000 -#define UDMA_CHCTL_SRCINC_32 0x08000000 -#define UDMA_CHCTL_SRCSIZE_MASK 0x03000000 -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 -#define UDMA_CHCTL_ARBSIZE_MASK 0x0003C000 -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 -#define UDMA_CHCTL_XFERSIZE_MASK 0x00003FF0 -#define UDMA_CHCTL_XFERSIZE(n) ((n-1) << 4) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 -#define UDMA_CHCTL_XFERMODE_MASK 0x00000007 -#define UDMA_CHCTL_XFERMODE_STOP 0x00000000 -#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 -#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 -#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 -#define UDMA_CHCTL_XFERMODE_MSG 0x00000004 -#define UDMA_CHCTL_XFERMODE_AMSG 0x00000005 -#define UDMA_CHCTL_XFERMODE_PSG 0x00000006 -#define UDMA_CHCTL_XFERMODE_APSG 0x00000007 -/** @} */ +#define UDMA_CHCTL_XFERSIZE(n) (((n)-1) << 4) /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -137,43 +102,43 @@ typedef struct __attribute__((packed, aligned(1024))) /*===========================================================================*/ #define dmaChannelEnable(dmach) {\ - UDMA->ENASET = (1 << dmach);\ + HWREG(UDMA_ENASET) = (1 << dmach);\ } #define dmaChannelDisable(dmach) { \ - UDMA->ENACLR = (1 << dmach); \ + HWREG(UDMA_ENACLR) = (1 << dmach); \ } #define dmaChannelPrimary(dmach) {\ - UDMA->ALTCLR = (1 << dmach); \ + HWREG(UDMA_ALTCLR) = (1 << dmach); \ } #define dmaChannelAlternate(dmach) { \ - UDMA->ALTSET = (1 << dmach); \ + HWREG(UDMA_ALTSET) = (1 << dmach); \ } #define dmaChannelSingleBurst(dmach) { \ - UDMA->USEBURSTCLR = (1 << dmach); \ + HWREG(UDMA_USEBURSTCLR) = (1 << dmach); \ } #define dmaChannelBurstOnly(dmach) { \ - UDMA->USEBURSTSET = (1 << dmach); \ + HWREG(UDMA_USEBURSTSET) = (1 << dmach); \ } #define dmaChannelPriorityHigh(dmach) { \ - UDMA->PRIOSET = (1 << dmach); \ + HWREG(UDMA_PRIOSET) = (1 << dmach); \ } #define dmaChannelPriorityDefault(dmach) { \ - UDMA->PRIOCLR = (1 << dmach); \ + HWREG(UDMA_PRIOCLR) = (1 << dmach); \ } #define dmaChannelEnableRequest(dmach) {\ - UDMA->REQMASKCLR = (1 << dmach); \ + HWREG(UDMA_REQMASKCLR) = (1 << dmach); \ } #define dmaChannelDisableRequest(dmach) {\ - UDMA->REQMASKSET = (1 << dmach); \ + HWREG(UDMA_REQMASKSET) = (1 << dmach); \ } /*===========================================================================*/ @@ -193,3 +158,5 @@ extern "C" { #endif #endif /* TIVA_UDMA_H_ */ + +/** @} */ diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.c b/os/hal/ports/TIVA/TM4C123x/hal_lld.c index ddcddb3..10cd903 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.c +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -76,60 +76,60 @@ void tiva_clock_init(void) * PLL. */ /* read */ - rcc = SYSCTL->RCC; - rcc2 = SYSCTL->RCC2; + rcc = HWREG(SYSCTL_RCC); + rcc2 = HWREG(SYSCTL_RCC2); /* modify */ - rcc |= TIVA_RCC_BYPASS; - rcc &= ~TIVA_RCC_USESYSDIV; - rcc2 |= TIVA_RCC2_BYPASS2 | TIVA_RCC2_USERCC2; + rcc |= SYSCTL_RCC_BYPASS; + rcc &= ~SYSCTL_RCC_USESYSDIV; + rcc2 |= SYSCTL_RCC2_BYPASS2 | SYSCTL_RCC2_USERCC2; /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; /* 2 Select the crystal value (XTAL) and oscillator source (OSCSRC), and * clear the PWRDN bit in RCC and RCC2. Setting the XTAL field automatically * pulls valid PLL configuration data for the appropriate crystal, and * clearing the PWRDN bit powers and enables the PLL and its output. */ /* modify */ - rcc &= ~(TIVA_RCC_OSCSRC_MASK | TIVA_RCC_XTAL_MASK | TIVA_RCC_PWRDN | TIVA_RCC_MOSCDIS); - rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (TIVA_RCC_XTAL_MASK | TIVA_RCC_OSCSRC_MASK | TIVA_RCC_MOSCDIS)); - rcc2 &= ~(TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_PWRDN2); - rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (TIVA_RCC2_OSCSRC2_MASK | TIVA_RCC2_DIV400)); + rcc &= ~(SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_XTAL_M | SYSCTL_RCC_PWRDN | SYSCTL_RCC_MOSCDIS); + rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_MOSCDIS)); + rcc2 &= ~(SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_PWRDN2); + rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_DIV400)); /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; for(i = 100000; i; i--); /* 3. Select the desired system divider (SYSDIV) in RCC and RCC2 and set the * USESYSDIV bit in RCC. The SYSDIV field determines the system frequency for * the microcontroller. */ /* modify */ - rcc &= ~TIVA_RCC_SYSDIV_MASK; - rcc |= (TIVA_SYSDIV & TIVA_RCC_SYSDIV_MASK) | TIVA_USESYSDIV; - rcc2 &= ~(TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB); - rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (TIVA_RCC2_SYSDIV2_MASK | TIVA_RCC2_SYSDIV2LSB)); + rcc &= ~SYSCTL_RCC_SYSDIV_M; + rcc |= (TIVA_SYSDIV & SYSCTL_RCC_SYSDIV_M) | SYSCTL_RCC_USESYSDIV; + rcc2 &= ~(SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB); + rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB)); /* write */ - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; /* 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw * Interrupt Status (RIS) register. */ - while ((SYSCTL->RIS & SYSCTL_RIS_PLLLRIS) == 0); + while ((HWREG(SYSCTL_RIS) & SYSCTL_RIS_PLLLRIS) == 0); /* 5. Enable use of the PLL by clearing the BYPASS bit in RCC and RCC2. */ - rcc &= ~TIVA_RCC_BYPASS; - rcc2 &= ~TIVA_RCC2_BYPASS2; + rcc &= ~SYSCTL_RCC_BYPASS; + rcc2 &= ~SYSCTL_RCC2_BYPASS2; rcc |= (TIVA_BYPASS_VALUE << 11); rcc2 |= (TIVA_BYPASS_VALUE << 11); - SYSCTL->RCC = rcc; - SYSCTL->RCC2 = rcc2; + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; #if HAL_USE_PWM - SYSCTL->RCC |= TIVA_PWM_FIELDS; + HWREG(SYSCTL_RCC) |= TIVA_PWM_FIELDS; #endif #if defined(TIVA_UDMA_REQUIRED) diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h index ec81806..5d38a67 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -45,123 +45,6 @@ * @} */ -/** - * @name RCC register bits definitions - * @{ - */ - -#define TIVA_RCC_MOSCDIS (0x01 << 0) - -#define TIVA_RCC_OSCSRC_MASK (0x03 << 4) -#define TIVA_RCC_OSCSRC_MOSC (0x00 << 4) -#define TIVA_RCC_OSCSRC_PIOSC (0x01 << 4) -#define TIVA_RCC_OSCSRC_PIOSC_4 (0x02 << 4) -#define TIVA_RCC_OSCSRC_LFIOSC (0x03 << 4) - -#define TIVA_RCC_XTAL_MASK (0x1f << 6) -#define TIVA_RCC_XTAL_4000000 (0x06 << 6) -#define TIVA_RCC_XTAL_4096000 (0x07 << 6) -#define TIVA_RCC_XTAL_4915200 (0x08 << 6) -#define TIVA_RCC_XTAL_5000000 (0x09 << 6) -#define TIVA_RCC_XTAL_5120000 (0x0a << 6) -#define TIVA_RCC_XTAL_6000000 (0x0b << 6) -#define TIVA_RCC_XTAL_6144000 (0x0c << 6) -#define TIVA_RCC_XTAL_7372800 (0x0d << 6) -#define TIVA_RCC_XTAL_8000000 (0x0e << 6) -#define TIVA_RCC_XTAL_8192000 (0x0f << 6) -#define TIVA_RCC_XTAL_10000000 (0x10 << 6) -#define TIVA_RCC_XTAL_12000000 (0x11 << 6) -#define TIVA_RCC_XTAL_12288000 (0x12 << 6) -#define TIVA_RCC_XTAL_13560000 (0x13 << 6) -#define TIVA_RCC_XTAL_14318180 (0x14 << 6) -#define TIVA_RCC_XTAL_16000000 (0x15 << 6) -#define TIVA_RCC_XTAL_16384000 (0x16 << 6) -#define TIVA_RCC_XTAL_18000000 (0x17 << 6) -#define TIVA_RCC_XTAL_20000000 (0x18 << 6) -#define TIVA_RCC_XTAL_24000000 (0x19 << 6) -#define TIVA_RCC_XTAL_25000000 (0x1a << 6) - -#define TIVA_RCC_BYPASS (1 << 11) - -#define TIVA_RCC_PWRDN (1 << 13) - -#define TIVA_RCC_PWMDIV_MASK (0x07 << 17) -#define TIVA_RCC_PWMDIV_2 (0x00 << 17) -#define TIVA_RCC_PWMDIV_4 (0x01 << 17) -#define TIVA_RCC_PWMDIV_8 (0x02 << 17) -#define TIVA_RCC_PWMDIV_16 (0x03 << 17) -#define TIVA_RCC_PWMDIV_32 (0x04 << 17) -#define TIVA_RCC_PWMDIV_64 (0x07 << 17) - -#define TIVA_RCC_USEPWMDIV (1 << 20) - -#define TIVA_RCC_USESYSDIV (1 << 22) - -#define TIVA_RCC_SYSDIV_MASK (0x0f << 23) -#define TIVA_RCC_SYSDIV_1 (0x00 << 23) -#define TIVA_RCC_SYSDIV_2 (0x01 << 23) -#define TIVA_RCC_SYSDIV_3 (0x02 << 23) -#define TIVA_RCC_SYSDIV_4 (0x03 << 23) -#define TIVA_RCC_SYSDIV_5 (0x04 << 23) -#define TIVA_RCC_SYSDIV_6 (0x05 << 23) -#define TIVA_RCC_SYSDIV_7 (0x06 << 23) -#define TIVA_RCC_SYSDIV_8 (0x07 << 23) -#define TIVA_RCC_SYSDIV_9 (0x08 << 23) -#define TIVA_RCC_SYSDIV_10 (0x09 << 23) -#define TIVA_RCC_SYSDIV_11 (0x0a << 23) -#define TIVA_RCC_SYSDIV_12 (0x0b << 23) -#define TIVA_RCC_SYSDIV_13 (0x0c << 23) -#define TIVA_RCC_SYSDIV_14 (0x0d << 23) -#define TIVA_RCC_SYSDIV_15 (0x0e << 23) -#define TIVA_RCC_SYSDIV_16 (0x0f << 23) - -#define TIVA_RCC_ACG (1 << 27) - -/** - * @} - */ - -/** - * @name RCC2 register bits definitions - * @{ - */ - -#define TIVA_RCC2_OSCSRC2_MASK (0x07 << 4) -#define TIVA_RCC2_OSCSRC2_MOSC (0x00 << 4) -#define TIVA_RCC2_OSCSRC2_PIOSC (0x01 << 4) -#define TIVA_RCC2_OSCSRC2_PIOSC_4 (0x02 << 4) -#define TIVA_RCC2_OSCSRC2_LFIOSC (0x03 << 4) -#define TIVA_RCC2_OSCSRC2_32768 (0x07 << 4) - -#define TIVA_RCC2_BYPASS2 (1 << 11) - -#define TIVA_RCC2_PWRDN2 (1 << 13) - -#define TIVA_RCC2_USBPWRDN (1 << 14) - -#define TIVA_RCC2_SYSDIV2LSB (1 << 22) - -#define TIVA_RCC2_SYSDIV2_MASK (0x3f << 23) - -#define TIVA_RCC2_DIV400 (1 << 30) - -#define TIVA_RCC2_USERCC2 (1 << 31) - -/** - * @} - */ - -/** - * @name RIS register bits definitions - * @{ - */ - -#define SYSCTL_RIS_PLLLRIS (1 << 6) - -/** - * @} - */ - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -172,7 +55,7 @@ */ #if !defined(TIVA_OSCSRC) -#define TIVA_OSCSRC TIVA_RCC2_OSCSRC2_MOSC +#define TIVA_OSCSRC SYSCTL_RCC2_OSCSRC2_MO #endif #if !defined(TIVA_MOSC_ENABLE) @@ -217,56 +100,56 @@ /* * Oscillator-related checks. */ -#if !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_MOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_PIOSC_4) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_LFIOSC) && \ - !(TIVA_OSCSRC == TIVA_RCC2_OSCSRC2_32768) +#if !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO4) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_30) && \ + !(TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_32) #error "Invalid value for TIVA_OSCSRC defined" #endif #if TIVA_XTAL_VALUE == 4000000 -#define TIVA_XTAL_ (0x06 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4MHZ #elif TIVA_XTAL_VALUE == 4096000 -#define TIVA_XTAL_ (0x07 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_09MHZ #elif TIVA_XTAL_VALUE == 4915200 -#define TIVA_XTAL_ (0x08 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_91MHZ #elif TIVA_XTAL_VALUE == 5000000 -#define TIVA_XTAL_ (0x09 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5MHZ #elif TIVA_XTAL_VALUE == 5120000 -#define TIVA_XTAL_ (0x0a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5_12MHZ #elif TIVA_XTAL_VALUE == 6000000 -#define TIVA_XTAL_ (0x0b << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6MHZ #elif TIVA_XTAL_VALUE == 6144000 -#define TIVA_XTAL_ (0x0c << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6_14MHZ #elif TIVA_XTAL_VALUE == 7372800 -#define TIVA_XTAL_ (0x0d << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_7_37MHZ #elif TIVA_XTAL_VALUE == 8000000 -#define TIVA_XTAL_ (0x0e << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8MHZ #elif TIVA_XTAL_VALUE == 8192000 -#define TIVA_XTAL_ (0x0f << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8_19MHZ #elif TIVA_XTAL_VALUE == 10000000 -#define TIVA_XTAL_ (0x10 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_10MHZ #elif TIVA_XTAL_VALUE == 12000000 -#define TIVA_XTAL_ (0x11 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12MHZ #elif TIVA_XTAL_VALUE == 12288000 -#define TIVA_XTAL_ (0x12 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12_2MHZ #elif TIVA_XTAL_VALUE == 13560000 -#define TIVA_XTAL_ (0x13 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_13_5MHZ #elif TIVA_XTAL_VALUE == 14318180 -#define TIVA_XTAL_ (0x14 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_14_3MHZ #elif TIVA_XTAL_VALUE == 16000000 -#define TIVA_XTAL_ (0x15 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16MHZ #elif TIVA_XTAL_VALUE == 16384000 -#define TIVA_XTAL_ (0x16 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16_3MHZ #elif TIVA_XTAL_VALUE == 18000000 -#define TIVA_XTAL_ (0x17 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_18MHZ #elif TIVA_XTAL_VALUE == 20000000 -#define TIVA_XTAL_ (0x18 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_20MHZ #elif TIVA_XTAL_VALUE == 24000000 -#define TIVA_XTAL_ (0x19 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_24MHZ #elif TIVA_XTAL_VALUE == 25000000 -#define TIVA_XTAL_ (0x1a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_25MHZ #else #error "Invalid value for TIVA_XTAL_VALUE defined" #endif @@ -320,7 +203,7 @@ #error "Invalid value for TIVA_BYPASS_VALUE defined" #endif -#if (TIVA_OSCSRC == TIVA_RCC_OSCSRC_MOSC) && (TIVA_MOSC_ENABLE == FALSE) +#if (TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) && (TIVA_MOSC_ENABLE == FALSE) #error "Main Oscillator selected but not enabled" #endif diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk index 0abafcc..8e447ec 100644 --- a/os/hal/ports/TIVA/TM4C123x/platform.mk +++ b/os/hal/ports/TIVA/TM4C123x/platform.mk @@ -1,18 +1,33 @@ -# List of all the TM4C123x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_i2c_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_gpt_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pwm_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_spi_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/tiva_udma.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c +# Required platform files. +PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD +# Required include directories. +PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x + +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define")) +else +endif + +# Drivers compatible with the platform. +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/ADC/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/I2C/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/PWM/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_isr.h b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h index b380e46..f4bec51 100644 --- a/os/hal/ports/TIVA/TM4C123x/tiva_isr.h +++ b/os/hal/ports/TIVA/TM4C123x/tiva_isr.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -42,11 +42,11 @@ #define TIVA_UDMA_ERR_NUMBER 47 /* GPIO units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) \ - || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM) \ - || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) \ + || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1236D5PM) \ + || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -63,11 +63,11 @@ #define TIVA_GPIOF_NUMBER 30 #define TIVA_GPIOG_NUMBER 31 #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -82,11 +82,11 @@ #define TIVA_GPIOE_NUMBER 4 #define TIVA_GPIOF_NUMBER 30 #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ) \ - || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PZ) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PZ) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -111,8 +111,8 @@ #define TIVA_GPIOK_NUMBER 55 #define TIVA_GPIOL_NUMBER 56 #endif -#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\ - || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE) +#if defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1237H6PGE)\ + || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123GH6PGE) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -157,7 +157,7 @@ #define TIVA_GPIOP6_NUMBER 122 #define TIVA_GPIOP7_NUMBER 123 #endif -#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -220,23 +220,23 @@ #endif /* GPTM units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_GPT0A_HANDLER Vector8C #define TIVA_GPT0B_HANDLER Vector90 #define TIVA_GPT1A_HANDLER Vector94 @@ -291,46 +291,46 @@ #endif /* WDT units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_WDT_HANDLER Vector88 #define TIVA_WDT_NUMBER 18 #endif /* ADC units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_ADC0_SEQ0_HANDLER Vector78 #define TIVA_ADC0_SEQ1_HANDLER Vector7C #define TIVA_ADC0_SEQ2_HANDLER Vector80 @@ -351,23 +351,23 @@ #endif /* UART units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_UART0_HANDLER Vector54 #define TIVA_UART1_HANDLER Vector58 #define TIVA_UART2_HANDLER VectorC4 @@ -388,23 +388,23 @@ #endif /* SPI units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_SSI0_HANDLER Vector5C #define TIVA_SSI1_HANDLER VectorC8 #define TIVA_SSI2_HANDLER Vector124 @@ -417,18 +417,18 @@ #endif /* I2C units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \ - || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) \ - || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PGE) \ + || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) \ + || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_I2C0_HANDLER Vector60 #define TIVA_I2C1_HANDLER VectorD4 #define TIVA_I2C2_HANDLER Vector150 @@ -443,11 +443,11 @@ #define TIVA_I2C4_NUMBER 109 #define TIVA_I2C5_NUMBER 110 #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_I2C0_HANDLER Vector60 #define TIVA_I2C1_HANDLER VectorD4 #define TIVA_I2C2_HANDLER Vector150 @@ -460,28 +460,28 @@ #endif /* CAN units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) #define TIVA_CAN0_HANDLER VectorDC #define TIVA_CAN0_NUMBER 39 #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_CAN0_HANDLER VectorDC #define TIVA_CAN1_HANDLER VectorE0 @@ -490,55 +490,55 @@ #endif /* USB units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) /* No interrupt handler and number.*/ #endif -#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) \ - || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \ - || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) \ + || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) \ + || defined(PART_TM4C123GH5ZXR) #define TIVA_USB0_HANDLER VectorF0 #define TIVA_USB0_NUMBER 44 #endif /* AC units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM) \ - || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM) \ - || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || defined(PART_TM4C1233E6PM) \ + || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_AC0_HANDLER VectorA4 #define TIVA_AC1_HANDLER VectorA8 #define TIVA_AC0_NUMBER 25 #define TIVA_AC1_NUMBER 26 #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE) \ - || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \ - || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PGE) \ + || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1237D5PZ) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PZ) \ + || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE)\ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_AC0_HANDLER VectorA4 #define TIVA_AC1_HANDLER VectorA8 #define TIVA_AC2_HANDLER VectorAC @@ -549,26 +549,26 @@ #endif /* PWM units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) /* No interrupt handler and number.*/ #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_PWM0FAULT_HANDLER Vector64 #define TIVA_PWM0GEN0_HANDLER Vector68 #define TIVA_PWM0GEN1_HANDLER Vector6C @@ -593,25 +593,25 @@ #endif /* QEI units.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) /* No interrupt handler and number.*/ #endif -#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_QEI0_HANLDER Vector74 #define TIVA_QEI1_HANLDER VectorD8 diff --git a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h index ac7a1d2..7604936 100644 --- a/os/hal/ports/TIVA/TM4C123x/tiva_registry.h +++ b/os/hal/ports/TIVA/TM4C123x/tiva_registry.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -29,35 +29,41 @@ /* Defined device check. */ /*===========================================================================*/ -#if !defined(TM4C1230C3PM) && !defined(TM4C1230D5PM) && \ - !defined(TM4C1230E6PM) && !defined(TM4C1230H6PM) && \ - !defined(TM4C1231C3PM) && !defined(TM4C1231D5PM) && \ - !defined(TM4C1231D5PZ) && !defined(TM4C1231E6PM) && \ - !defined(TM4C1231E6PZ) && !defined(TM4C1231H6PGE) && \ - !defined(TM4C1231H6PM) && !defined(TM4C1231H6PZ) && \ - !defined(TM4C1232C3PM) && !defined(TM4C1232D5PM) && \ - !defined(TM4C1232E6PM) && !defined(TM4C1232H6PM) && \ - !defined(TM4C1233C3PM) && !defined(TM4C1233D5PM) && \ - !defined(TM4C1233D5PZ) && !defined(TM4C1233E6PM) && \ - !defined(TM4C1233E6PZ) && !defined(TM4C1233H6PGE) && \ - !defined(TM4C1233H6PM) && !defined(TM4C1233H6PZ) && \ - !defined(TM4C1236D5PM) && !defined(TM4C1236E6PM) && \ - !defined(TM4C1236H6PM) && !defined(TM4C1237D5PM) && \ - !defined(TM4C1237D5PZ) && !defined(TM4C1237E6PM) && \ - !defined(TM4C1237E6PZ) && !defined(TM4C1237H6PGE) && \ - !defined(TM4C1237H6PM) && !defined(TM4C1237H6PZ) && \ - !defined(TM4C123AE6PM) && !defined(TM4C123AH6PM) && \ - !defined(TM4C123BE6PM) && !defined(TM4C123BE6PZ) && \ - !defined(TM4C123BH6PGE) && !defined(TM4C123BH6PM) && \ - !defined(TM4C123BH6PZ) && !defined(TM4C123BH6ZRB) && \ - !defined(TM4C123FE6PM) && !defined(TM4C123FH6PM) && \ - !defined(TM4C123GE6PM) && !defined(TM4C123GE6PZ) && \ - !defined(TM4C123GH6PGE) && !defined(TM4C123GH6PM) && \ - !defined(TM4C123GH6PZ) && !defined(TM4C123GH6ZRB) && \ - !defined(TM4C123GH5ZXR) +#if !defined(PART_TM4C1230C3PM) && !defined(PART_TM4C1230D5PM) && \ + !defined(PART_TM4C1230E6PM) && !defined(PART_TM4C1230H6PM) && \ + !defined(PART_TM4C1231C3PM) && !defined(PART_TM4C1231D5PM) && \ + !defined(PART_TM4C1231D5PZ) && !defined(PART_TM4C1231E6PM) && \ + !defined(PART_TM4C1231E6PZ) && !defined(PART_TM4C1231H6PGE) && \ + !defined(PART_TM4C1231H6PM) && !defined(PART_TM4C1231H6PZ) && \ + !defined(PART_TM4C1232C3PM) && !defined(PART_TM4C1232D5PM) && \ + !defined(PART_TM4C1232E6PM) && !defined(PART_TM4C1232H6PM) && \ + !defined(PART_TM4C1233C3PM) && !defined(PART_TM4C1233D5PM) && \ + !defined(PART_TM4C1233D5PZ) && !defined(PART_TM4C1233E6PM) && \ + !defined(PART_TM4C1233E6PZ) && !defined(PART_TM4C1233H6PGE) && \ + !defined(PART_TM4C1233H6PM) && !defined(PART_TM4C1233H6PZ) && \ + !defined(PART_TM4C1236D5PM) && !defined(PART_TM4C1236E6PM) && \ + !defined(PART_TM4C1236H6PM) && !defined(PART_TM4C1237D5PM) && \ + !defined(PART_TM4C1237D5PZ) && !defined(PART_TM4C1237E6PM) && \ + !defined(PART_TM4C1237E6PZ) && !defined(PART_TM4C1237H6PGE) && \ + !defined(PART_TM4C1237H6PM) && !defined(PART_TM4C1237H6PZ) && \ + !defined(PART_TM4C123AE6PM) && !defined(PART_TM4C123AH6PM) && \ + !defined(PART_TM4C123BE6PM) && !defined(PART_TM4C123BE6PZ) && \ + !defined(PART_TM4C123BH6PGE) && !defined(PART_TM4C123BH6PM) && \ + !defined(PART_TM4C123BH6PZ) && !defined(PART_TM4C123BH6ZRB) && \ + !defined(PART_TM4C123FE6PM) && !defined(PART_TM4C123FH6PM) && \ + !defined(PART_TM4C123GE6PM) && !defined(PART_TM4C123GE6PZ) && \ + !defined(PART_TM4C123GH6PGE) && !defined(PART_TM4C123GH6PM) && \ + !defined(PART_TM4C123GH6PZ) && !defined(PART_TM4C123GH6ZRB) && \ + !defined(PART_TM4C123GH5ZXR) #error "No valid device defined." #endif +#if !defined(TARGET_IS_TM4C123_RA1) && !defined(TARGET_IS_TM4C123_RA2) && \ + !defined(TARGET_IS_TM4C123_RA3) && !defined(TARGET_IS_TM4C123_RB0) && \ + !defined(TARGET_IS_TM4C123_RB1) +#error "No valid device revision defined." +#endif + /** * @brief Sub-family identifier. */ @@ -75,11 +81,11 @@ */ /* GPIO attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) \ - || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) || defined(TM4C1236D5PM) \ - || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) \ + || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1236D5PM) \ + || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -100,11 +106,11 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 56 #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -125,11 +131,11 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 48 #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PZ) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PZ) \ - || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PZ) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PZ) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PZ) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -150,8 +156,8 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 88 #endif -#if defined(TM4C1231H6PGE) || defined(TM4C1233H6PGE) || defined(TM4C1237H6PGE)\ - || defined(TM4C123BH6PGE) || defined(TM4C123GH6PGE) +#if defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1237H6PGE)\ + || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123GH6PGE) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -172,7 +178,7 @@ #define TIVA_HAS_GPIOT FALSE #define TIVA_GPIO_PINS 112 #endif -#if defined(TM4C123BH6ZRB) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -195,23 +201,23 @@ #endif /* GPTM attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_GPT0 TRUE #define TIVA_HAS_GPT1 TRUE #define TIVA_HAS_GPT2 TRUE @@ -229,67 +235,67 @@ #endif /* WDT attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_WDT0 TRUE #define TIVA_HAS_WDT1 TRUE #endif /* ADC attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_ADC0 TRUE #define TIVA_HAS_ADC1 TRUE #endif /* UART attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_UART0 TRUE #define TIVA_HAS_UART1 TRUE #define TIVA_HAS_UART2 TRUE @@ -301,23 +307,23 @@ #endif /* SPI attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_SSI0 TRUE #define TIVA_HAS_SSI1 TRUE #define TIVA_HAS_SSI2 TRUE @@ -325,18 +331,18 @@ #endif /* I2C attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PZ) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) || defined(TM4C1233H6PGE) \ - || defined(TM4C1233H6PZ) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PZ) \ - || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) \ - || defined(TM4C123AH6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PGE) \ + || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PZ) \ + || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) \ + || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_I2C0 TRUE #define TIVA_HAS_I2C1 TRUE #define TIVA_HAS_I2C2 TRUE @@ -348,11 +354,11 @@ #define TIVA_HAS_I2C8 FALSE #define TIVA_HAS_I2C9 FALSE #endif -#if defined(TM4C1231C3PM) || defined(TM4C1231D5PM) || defined(TM4C1231E6PM) \ - || defined(TM4C1231H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233E6PM) || defined(TM4C1233H6PM) || defined(TM4C1237D5PM) \ - || defined(TM4C1237E6PM) || defined(TM4C1237H6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231E6PM) \ + || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1237D5PM) \ + || defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_HAS_I2C0 TRUE #define TIVA_HAS_I2C1 TRUE #define TIVA_HAS_I2C2 TRUE @@ -366,129 +372,129 @@ #endif /* CAN attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) #define TIVA_HAS_CAN0 TRUE #define TIVA_HAS_CAN1 FALSE #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_CAN0 TRUE #define TIVA_HAS_CAN1 TRUE #endif /* USB attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) #define TIVA_HAS_USB0 FALSE #endif -#if defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) \ - || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) \ - || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) \ - || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) \ + || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) \ + || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) \ + || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_USB0 TRUE #endif /* AC attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231E6PM) || defined(TM4C1231H6PM) || defined(TM4C1232C3PM) \ - || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) || defined(TM4C1232H6PM) \ - || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) || defined(TM4C1233E6PM) \ - || defined(TM4C1233H6PM) || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) \ - || defined(TM4C1236H6PM) || defined(TM4C1237D5PM) || defined(TM4C1237E6PM) \ - || defined(TM4C1237H6PM) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) \ - || defined(TM4C123BE6PM) || defined(TM4C123BH6PM) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1232C3PM) \ + || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) \ + || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || defined(PART_TM4C1233E6PM) \ + || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) \ + || defined(PART_TM4C1236H6PM) || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237H6PM) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) \ + || defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GH6PM) #define TIVA_HAS_AC0 TRUE #define TIVA_HAS_AC1 TRUE #define TIVA_HAS_AC2 FALSE #endif -#if defined(TM4C1231D5PZ) || defined(TM4C1231E6PZ) || defined(TM4C1231H6PGE) \ - || defined(TM4C1231H6PZ) || defined(TM4C1233D5PZ) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PZ) || defined(TM4C1237D5PZ) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PZ) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PZ) \ - || defined(TM4C123BH6ZRB) || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE)\ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PZ) || defined(PART_TM4C1231H6PGE) \ + || defined(PART_TM4C1231H6PZ) || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1237D5PZ) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PZ) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PZ) \ + || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE)\ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_AC0 TRUE #define TIVA_HAS_AC1 TRUE #define TIVA_HAS_AC2 TRUE #endif /* PWM attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) #define TIVA_HAS_PWM0 FALSE #define TIVA_HAS_PWM1 FALSE #endif -#if defined(TM4C123AE6PM) || defined(TM4C123AH6PM) || defined(TM4C123BE6PM) \ - || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) || defined(TM4C123BH6PM) \ - || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) || defined(TM4C123FE6PM) \ - || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) || defined(TM4C123GE6PZ) \ - || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) || defined(TM4C123GH6PZ) \ - || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || defined(PART_TM4C123BE6PM) \ + || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) || defined(PART_TM4C123BH6PM) \ + || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123FE6PM) \ + || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) \ + || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) \ + || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_PWM0 TRUE #define TIVA_HAS_PWM1 TRUE #endif /* QEI attributes.*/ -#if defined(TM4C1230C3PM) || defined(TM4C1230D5PM) || defined(TM4C1230E6PM) \ - || defined(TM4C1230H6PM) || defined(TM4C1231C3PM) || defined(TM4C1231D5PM) \ - || defined(TM4C1231D5PZ) || defined(TM4C1231E6PM) || defined(TM4C1231E6PZ) \ - || defined(TM4C1231H6PGE) || defined(TM4C1231H6PM) || defined(TM4C1231H6PZ) \ - || defined(TM4C1232C3PM) || defined(TM4C1232D5PM) || defined(TM4C1232E6PM) \ - || defined(TM4C1232H6PM) || defined(TM4C1233C3PM) || defined(TM4C1233D5PM) \ - || defined(TM4C1233D5PZ) || defined(TM4C1233E6PM) || defined(TM4C1233E6PZ) \ - || defined(TM4C1233H6PGE) || defined(TM4C1233H6PM) || defined(TM4C1233H6PZ) \ - || defined(TM4C1236D5PM) || defined(TM4C1236E6PM) || defined(TM4C1236H6PM) \ - || defined(TM4C1237D5PM) || defined(TM4C1237D5PZ) || defined(TM4C1237E6PM) \ - || defined(TM4C1237E6PZ) || defined(TM4C1237H6PGE) || defined(TM4C1237H6PM) \ - || defined(TM4C1237H6PZ) || defined(TM4C123AE6PM) || defined(TM4C123AH6PM) +#if defined(PART_TM4C1230C3PM) || defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) \ + || defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || defined(PART_TM4C1231D5PM) \ + || defined(PART_TM4C1231D5PZ) || defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) \ + || defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) \ + || defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || defined(PART_TM4C1232E6PM) \ + || defined(PART_TM4C1232H6PM) || defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) \ + || defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || defined(PART_TM4C1233E6PZ) \ + || defined(PART_TM4C1233H6PGE) || defined(PART_TM4C1233H6PM) || defined(PART_TM4C1233H6PZ) \ + || defined(PART_TM4C1236D5PM) || defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) \ + || defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || defined(PART_TM4C1237E6PM) \ + || defined(PART_TM4C1237E6PZ) || defined(PART_TM4C1237H6PGE) || defined(PART_TM4C1237H6PM) \ + || defined(PART_TM4C1237H6PZ) || defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) #define TIVA_HAS_QEI0 FALSE #define TIVA_HAS_QEI1 FALSE #endif -#if defined(TM4C123BE6PM) || defined(TM4C123BE6PZ) || defined(TM4C123BH6PGE) \ - || defined(TM4C123BH6PM) || defined(TM4C123BH6PZ) || defined(TM4C123BH6ZRB) \ - || defined(TM4C123FE6PM) || defined(TM4C123FH6PM) || defined(TM4C123GE6PM) \ - || defined(TM4C123GE6PZ) || defined(TM4C123GH6PGE) || defined(TM4C123GH6PM) \ - || defined(TM4C123GH6PZ) || defined(TM4C123GH6ZRB) || defined(TM4C123GH5ZXR) +#if defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || defined(PART_TM4C123BH6PGE) \ + || defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || defined(PART_TM4C123BH6ZRB) \ + || defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || defined(PART_TM4C123GE6PM) \ + || defined(PART_TM4C123GE6PZ) || defined(PART_TM4C123GH6PGE) || defined(PART_TM4C123GH6PM) \ + || defined(PART_TM4C123GH6PZ) || defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH5ZXR) #define TIVA_HAS_QEI0 TRUE #define TIVA_HAS_QEI1 TRUE #endif diff --git a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h b/os/hal/ports/TIVA/TM4C123x/tm4c123x.h deleted file mode 100644 index d64afa8..0000000 --- a/os/hal/ports/TIVA/TM4C123x/tm4c123x.h +++ /dev/null @@ -1,958 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @addtogroup CMSIS - * @{ - */ - -/** - * @addtogroup TM4C123x - * @{ - */ - -#ifndef __TM4C123x_H -#define __TM4C123x_H - -/** - * @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /**< MPU present */ -#define __NVIC_PRIO_BITS 3 /**< Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Use different SysTick Config */ -#define __FPU_PRESENT 1 /**< FPU present */ - -/** - * @brief TM4C123x Interrupt Number Definitions - */ -typedef enum IRQn -{ - /***** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< Cortex-M4 Non-Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -3, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - /***** TM4C123x Specific Interrupt Numbers *********************************/ - GPIOA_IRQn = 0, /**< GPIO Port A */ - GPIOB_IRQn = 1, /**< GPIO Port B */ - GPIOC_IRQn = 2, /**< GPIO Port C */ - GPIOD_IRQn = 3, /**< GPIO Port D */ - GPIOE_IRQn = 4, /**< GPIO Port E */ - UART0_IRQn = 5, /**< UART0 */ - UART1_IRQn = 6, /**< UART1 */ - SSI0_IRQn = 7, /**< SSI0 */ - I2C0_IRQn = 8, /**< I2C0 */ - PWM0FAULT_IRQn = 9, /**< PWM0 Fault */ - PWM0GEN0_IRQn = 10, /**< PWM0 Generator 0 */ - PWM0GEN1_IRQn = 11, /**< PWM0 Generator 1 */ - PWM0GEN2_IRQn = 12, /**< PWM0 Generator 2 */ - QEI0_IRQn = 13, /**< QEI0 */ - ADC0SEQ0_IRQn = 14, /**< ADC0 Sequence 0 */ - ADC0SEQ1_IRQn = 15, /**< ADC0 Sequence 1 */ - ADC0SEQ2_IRQn = 16, /**< ADC0 Sequence 2 */ - ADC0SEQ3_IRQn = 17, /**< ADC0 Sequence 3 */ - WATCHDOG_IRQn = 18, /**< Watchdog Timers 0 and 1 */ - TIMER0A_IRQn = 19, /**< 16/32-Bit Timer 0A */ - TIMER0B_IRQn = 20, /**< 16/32-Bit Timer 0B */ - TIMER1A_IRQn = 21, /**< 16/32-Bit Timer 1A */ - TIMER1B_IRQn = 22, /**< 16/32-Bit Timer 1B */ - TIMER2A_IRQn = 23, /**< 16/32-Bit Timer 2A */ - TIMER2B_IRQn = 24, /**< 16/32-Bit Timer 2B */ - ACOMP0_IRQn = 25, /**< Analog Comparator 0 */ - ACOMP1_IRQn = 26, /**< Analog Comparator 1 */ - SYSCON_IRQn = 28, /**< System Control */ - FMCEECON_IRQn = 29, /**< Flash Memory Control and EEPROM Control */ - GPIOF_IRQn = 30, /**< GPIO Port F */ - UART2_IRQn = 33, /**< UART2 */ - SSI1_IRQn = 34, /**< SSI1 */ - TIMER3A_IRQn = 35, /**< 16/32-Bit Timer 3A */ - TIMER3B_IRQn = 36, /**< 16/32-Bit Timer 3B */ - I2C1_IRQn = 37, /**< I2C1 */ - QEI1_IRQn = 38, /**< QEI1 */ - CAN0_IRQn = 39, /**< CAN0 */ - CAN1_IRQn = 40, /**< CAN1 */ - HIBMODULE_IRQn = 43, /**< Hibernation Module */ - USB_IRQn = 44, /**< USB */ - PWM0GEN3_IRQn = 45, /**< PWM0 Generator 3 */ - UDMASFW_IRQn = 46, /**< UDMA Software */ - UDMAERR_IRQn = 47, /**< UDMA Error */ - ADC1SEQ0_IRQn = 48, /**< ADC1 Sequence 0 */ - ADC1SEQ1_IRQn = 49, /**< ADC1 Sequence 1 */ - ADC1SEQ2_IRQn = 50, /**< ADC1 Sequence 2 */ - ADC1SEQ3_IRQn = 51, /**< ADC1 Sequence 3 */ - SSI2_IRQn = 57, /**< SSI2 */ - SSI3_IRQn = 58, /**< SSI3 */ - UART3_IRQn = 59, /**< UART3 */ - UART4_IRQn = 60, /**< UART4 */ - UART5_IRQn = 61, /**< UART5 */ - UART6_IRQn = 62, /**< UART6 */ - UART7_IRQn = 63, /**< UART7 */ - I2C2_IRQn = 68, /**< I2C2 */ - I2C3_IRQn = 69, /**< I2C3 */ - TIMER4A_IRQn = 70, /**< 16/32-Bit Timer 4A */ - TIMER4B_IRQn = 71, /**< 16/32-Bit Timer 4B */ - TIMER5A_IRQn = 92, /**< 16/32-Bit Timer 5A */ - TIMER5B_IRQn = 93, /**< 16/32-Bit Timer 5B */ - WTIMER0A_IRQn = 94, /**< 32/64-Bit Timer 0A */ - WTIMER0B_IRQn = 95, /**< 32/64-Bit Timer 0B */ - WTIMER1A_IRQn = 96, /**< 32/64-Bit Timer 1A */ - WTIMER1B_IRQn = 97, /**< 32/64-Bit Timer 1B */ - WTIMER2A_IRQn = 98, /**< 32/64-Bit Timer 2A */ - WTIMER2B_IRQn = 99, /**< 32/64-Bit Timer 2B */ - WTIMER3A_IRQn = 100, /**< 32/64-Bit Timer 3A */ - WTIMER3B_IRQn = 101, /**< 32/64-Bit Timer 3B */ - WTIMER4A_IRQn = 102, /**< 32/64-Bit Timer 4A */ - WTIMER4B_IRQn = 103, /**< 32/64-Bit Timer 4B */ - WTIMER5A_IRQn = 104, /**< 32/64-Bit Timer 5A */ - WTIMER5B_IRQn = 105, /**< 32/64-Bit Timer 5B */ - SYSEXCEPT_IRQn = 106, /**< System Exception (imprecise) */ - PWM1GEN0_IRQn = 134, /**< PWM1 Generator 0 */ - PWM1GEN1_IRQn = 135, /**< PWM1 Generator 1 */ - PWM1GEN2_IRQn = 136, /**< PWM1 Generator 2 */ - PWM1GEN3_IRQn = 137, /**< PWM1 Generator 3 */ - PWM1FAULT_IRQn = 138 /**< PWM1 Fault */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals.*/ -#include <stdint.h> - -/** - * @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog Comparator - */ -typedef struct -{ - __IO uint32_t MIS; /**< Masked Interrupt Status */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t REFCTL; /**< Reference Voltage Control */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __I uint32_t STAT0; /**< Status 0 */ - __IO uint32_t CTL0; /**< Control 0 */ - __I uint32_t _RESERVED2[6]; /**< Reserved */ - __I uint32_t STAT1; /**< Status 1 */ - __IO uint32_t CTL1; /**< Control 1 */ - __I uint32_t _RESERVED3[990];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} ACMP_TypeDef; - -/** - * @brief Analog-to-Digital Converter - */ -typedef struct -{ - __IO uint32_t MUX; /**< Sample Sequence Input Multiplexer - Select */ - __IO uint32_t CTL; /**< Sample Sequence Control */ - __I uint32_t FIFO; /**< Sample Sequence Result FIFO */ - __I uint32_t FSTAT; /**< Sample Sequence FIFO Status */ - __IO uint32_t OP; /**< Sample Sequence Operation */ - __IO uint32_t DC; /**< Sample Sequence Digital Comparator - Select */ - __I uint32_t _RESERVED0[2]; /**< Reserved */ -} ADC_SS_t; - -typedef struct -{ - __IO uint32_t ACTSS; /**< Active Sample Sequencer */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t IM; /**< Interrupt Mask */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __IO uint32_t OSTAT; /**< Overflow Status */ - __IO uint32_t EMUX; /**< Event Multiplexer Select */ - __IO uint32_t USTAT; /**< Underflow Status */ - __IO uint32_t TSSEL; /**< Trigger Source Select */ - __IO uint32_t SSPRI; /**< Sample Sequencer Priority */ - __IO uint32_t SPC; /**< Sample Phase Control */ - __IO uint32_t PSSI; /**< Processor Sample Sequence Initiate */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t SAC; /**< Sample Averaging Control */ - __IO uint32_t DCISC; /**< Digital Comparator Interrupt Status and - Clear */ - __IO uint32_t CTL; /**< Control */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - ADC_SS_t SS[4]; /**< Sample Sequence 0, 1, 2 and 3 */ - __I uint32_t _RESERVED2[784];/**< Reserved */ - __O uint32_t DCRIC; /**< Digital Comparator Reset Initial - Conditions */ - __I uint32_t _RESERVED3[63]; /**< Reserved */ - __IO uint32_t DCCTL[8]; /**< Digital Comparator Control 0 - 7 */ - __I uint32_t _RESERVED4[8]; /**< Reserved */ - __IO uint32_t DCCMP[8]; /**< Digital Comparator Range 0 - 7 */ - __I uint32_t _RESERVED5[88]; /**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __IO uint32_t PC; /**< Peripheral Configuration */ - __IO uint32_t CC; /**< Clock Configuration */ -} ADC_TypeDef; - -/** - * @brief Controller Area Network - */ -typedef struct -{ - __IO uint32_t CRQ; /**< Command Request */ - __IO uint32_t CMSK; /**< Command Mask */ - __IO uint32_t MSK[2]; /**< Mask 1 and 2 */ - __IO uint32_t ARB[2]; /**< Arbitration 1 and 2 */ - __IO uint32_t MCTL; /**< Message Control */ - __IO uint32_t DA[2]; /**< Data A1 and A2 */ - __IO uint32_t DB[2]; /**< Data B1 and B2 */ - __I uint32_t _RESERVED0[13]; /**< Reserved */ -} CAN_INTERFACE_t; - -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t STS; /**< Status */ - __I uint32_t ERR; /**< Error Counter */ - __IO uint32_t BIT; /**< Bit Timing */ - __I uint32_t INT; /**< Interrupt */ - __IO uint32_t TST; /**< Test */ - __IO uint32_t BRPE; /**< Baud Rate Prescaler Extension */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - CAN_INTERFACE_t IF[2]; /**< IF1 and IF2 */ - __I uint32_t _RESERVED1[8]; /**< Reserved */ - __I uint32_t TXRQ[2]; /**< Transmission Request 1 and 2 */ - __I uint32_t _RESERVED2[6]; /**< Reserved */ - __I uint32_t NWDA[2]; /**< New Data 1 and 2 */ - __I uint32_t _RESERVED3[6]; /**< Reserved */ - __I uint32_t MSGINT[2]; /**< Message 1 and 2 Interrupt Pending */ - __I uint32_t _RESERVED4[6]; /**< Reserved */ - __I uint32_t MSGVAL[2]; /**< Message 1 and 2 Valid */ -} CAN_TypeDef; - -/** - * @brief EEPROM Memory - */ -typedef struct -{ - __IO uint32_t EESIZE; /**< Size Information */ - __IO uint32_t EEBLOCK; /**< Current Block */ - __IO uint32_t EEOFFSET; /**< Current Offset */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t EERDWR; /**< Read-Write */ - __IO uint32_t EERDWRINC; /**< Read-Write with Increment */ - __IO uint32_t EEDONE; /**< Done Status */ - __IO uint32_t EESUPP; /**< Support Control and Status */ - __IO uint32_t EEUNLOCK; /**< Unlock */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __IO uint32_t EEPROT; /**< Protection */ - __IO uint32_t EEPASS[3]; /**< Password */ - __IO uint32_t EEINT; /**< Interrupt */ - __I uint32_t _RESERVED2[3]; /**< Reserved */ - __IO uint32_t EEHIDE; /**< Block Hide */ - __I uint32_t _RESERVED3[11]; /**< Reserved */ - __IO uint32_t EEDBGME; /**< Debug Mass Erase */ - __I uint32_t _RESERVED4[975];/**< Reserved */ - __IO uint32_t EEPROMPP; /**< Peripheral Properties */ -} EEPROM_TypeDef; - -/** - * @brief Flash Memory - */ -typedef struct -{ - __IO uint32_t FMA; /**< Flash Memory Address */ - __IO uint32_t FMD; /**< Flash Memory Data */ - __IO uint32_t FMC; /**< Flash Memory Control */ - __I uint32_t FCRIS; /**< Flash Controller Raw Interrupt Status */ - __IO uint32_t FCIM; /**< Flash Controller Interrupt Mask */ - __IO uint32_t FCMISC; /**< Masked Interrupt Status and Clear */ - __I uint32_t _RESERVED0[2]; /**< Reserved */ - __IO uint32_t FMC2; /**< Flash Memory Control 2 */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __IO uint32_t FWBVAL; /**< Flash Write Buffer Valid */ - __I uint32_t _RESERVED2[51]; /**< Reserved */ - __IO uint32_t FWBN; /**< Flash Write Buffer n */ - __I uint32_t _RESERVED3[943];/**< Reserved */ - __I uint32_t FSIZE; /**< Flash Size */ - __I uint32_t SSIZE; /**< SRAM Size */ - __I uint32_t _RESERVED4[1]; /**< Reserved */ - __IO uint32_t ROMSWMAP; /**< ROM Software Map */ -} FLASH_TypeDef; - -/** - * @brief General Purpose Input/Outputs - */ -typedef struct -{ - union { - __IO uint32_t MASKED_ACCESS[256]; /**< Masked access of Data Register */ - struct { - __I uint32_t _RESERVED0[255]; /**< Reserved */ - __IO uint32_t DATA; /**< Data */ - }; - }; - __IO uint32_t DIR; /**< Direction */ - __IO uint32_t IS; /**< Interrupt Sense */ - __IO uint32_t IBE; /**< Interrupt Both Edges */ - __IO uint32_t IEV; /**< Interrupt Event */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t AFSEL; /**< Alternate Function Select */ - __I uint32_t _RESERVED1[55]; /**< Reserved */ - __IO uint32_t DR2R; /**< 2-mA Drive Select */ - __IO uint32_t DR4R; /**< 4-mA Drive Select */ - __IO uint32_t DR8R; /**< 8-mA Drive Select */ - __IO uint32_t ODR; /**< Open Drain Select */ - __IO uint32_t PUR; /**< Pull-Up Select */ - __IO uint32_t PDR; /**< Pull-Down Select */ - __IO uint32_t SLR; /**< Slew Rate Control Select */ - __IO uint32_t DEN; /**< Digital Enable */ - __IO uint32_t LOCK; /**< Lock */ - __IO uint32_t CR; /**< Commit */ - __IO uint32_t AMSEL; /**< Analog Mode Select */ - __IO uint32_t PCTL; /**< Port Control */ - __IO uint32_t ADCCTL; /**< ADC Control */ - __IO uint32_t DMACTL; /**< DMA Control */ -} GPIO_TypeDef; - -/** - * @brief General Purpose Timer - */ -typedef struct -{ - __IO uint32_t CFG; /**< Configuration */ - __IO uint32_t TAMR; /**< Timer A Mode */ - __IO uint32_t TBMR; /**< Timer B Mode */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t SYNC; /**< Synchronize */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t IMR; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t TAILR; /**< Timer A Interval Load */ - __IO uint32_t TBILR; /**< Timer B Interval Load */ - __IO uint32_t TAMATCHR; /**< Timer A Match */ - __IO uint32_t TBMATCHR; /**< Timer B Match */ - __IO uint32_t TAPR; /**< Timer A Prescale */ - __IO uint32_t TBPR; /**< Timer B Prescale */ - __IO uint32_t TAPMR; /**< Timer A Prescale Match */ - __IO uint32_t TBPMR; /**< Timer B Prescale Match */ - __I uint32_t TAR; /**< Timer A */ - __I uint32_t TBR; /**< Timer B */ - __IO uint32_t TAV; /**< Timer A Value */ - __IO uint32_t TBV; /**< Timer B Value */ - __I uint32_t RTCPD; /**< RTC Predivide */ - __I uint32_t TAPS; /**< Timer A Prescale Snapshot */ - __I uint32_t TBPS; /**< Timer B Prescale Snapshot */ - __I uint32_t TAPV; /**< Timer A Prescale Value */ - __I uint32_t TBPV; /**< Timer B Prescale Value */ - __I uint32_t _RESERVED1[981];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} GPT_TypeDef; - -/** - * @brief Hibernation Module - */ -typedef struct -{ - __I uint32_t RTCC; /**< RTC Counter */ - __IO uint32_t RTCM0; /**< RTC Match 0 */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t RTCLD; /**< RTC Load */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __IO uint32_t IC; /**< Interrupt Clear */ - __IO uint32_t RTCT; /**< RTC Trim */ - __IO uint32_t RTCSS; /**< RTC Sub Seconds */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - __IO uint32_t DATA; /**< Data */ -} HIB_TypeDef; - -/** - * @brief Inter-Integrated Circuit - */ -typedef struct -{ - __IO uint32_t MSA; /**< Master Slave Address */ - __IO uint32_t MCS; /**< Master Control/Status */ - __IO uint32_t MDR; /**< Master Data */ - __IO uint32_t MTPR; /**< Master Timer Period */ - __IO uint32_t MIMR; /**< Master Interrupt Mask */ - __I uint32_t MRIS; /**< Master Raw Interrupt Status */ - __IO uint32_t MMIS; /**< Master Masked Interrupt Status */ - __O uint32_t MICR; /**< Master Interrupt Clear */ - __IO uint32_t MCR; /**< Master Configuration */ - __IO uint32_t MCLKOCNT; /**< Master Clock Low Timeout Count */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __I uint32_t MBMON; /**< Master Bus Monitor */ - __IO uint32_t MCR2; /**< Master Configuration 2 */ - __I uint32_t _RESERVED1[497];/**< Reserved */ - __IO uint32_t SOAR; /**< Slave Own Address */ - __IO uint32_t SCSR; /**< Slave Control/Status */ - __IO uint32_t SDR; /**< Slave Data */ - __IO uint32_t SIMR; /**< Slave Interrupt Mask */ - __I uint32_t SRIS; /**< Slave Raw Interrupt Status */ - __I uint32_t SMIS; /**< Slave Masked Interrupt Status */ - __O uint32_t SICR; /**< Slave Interrupt Clear */ - __IO uint32_t SOAR2; /**< Slave Own Address 2 */ - __IO uint32_t SACKCTL; /**< Slave ACK Control */ - __I uint32_t _RESERVED2[487];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __I uint32_t PC; /**< Peripheral Configuration */ -} I2C_TypeDef; - -/* - * @brief Pulse Width Modulator - */ -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t INTEN; /**< Interrupt and Trigger Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __IO uint32_t LOAD; /**< Load */ - __I uint32_t COUNT; /**< Counter */ - __IO uint32_t CMP[2]; /**< Compare A, B */ - __IO uint32_t GEN[2]; /**< Generator A, B Control */ - __IO uint32_t DBCTL; /**< Dead-Band Control */ - __IO uint32_t DBRISE; /**< Dead-Band Rising-Edge Delay */ - __IO uint32_t DBFALL; /**< Dead-Band Falling-Edge Delay */ - __IO uint32_t FLTSRC[2]; /**< Fault Source 0, 1 */ - __IO uint32_t MINFLTPER; /**< Minimum Fault Period */ -} PWM_GENERATOR_T; - -typedef struct -{ - union { - __IO uint32_t SEN; /**< Fault Pin Logic Sense, for GEN 0 and 1 */ - __I uint32_t _RESERVED0[1];/**< Reserved, for GEN 2 and 3 */ - }; - __IO uint32_t STAT[2]; /**< Fault Status */ - __I uint32_t _RESERVED1[29]; /**< Reserved */ -} PWM_FLT_t; - -typedef struct -{ - __IO uint32_t CTL; /**< Master Control */ - __IO uint32_t SYNC; /**< Time Base Sync */ - __IO uint32_t ENABLE; /**< Output Enable */ - __IO uint32_t INVERT; /**< Output Inversion */ - __IO uint32_t FAULT; /**< Output Fault */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __I uint32_t STATUS; /**< Status */ - __IO uint32_t FAULTVAL; /**< Fault Condition Value */ - __IO uint32_t ENUPD; /**< Enable Update */ - __I uint32_t _RESERVED0[5]; /**< Reserved */ - __IO PWM_GENERATOR_T PWM[4]; /**< PWM Generator 0, 1, 2 and 3 */ - __I uint32_t _RESERVED1[432];/**< Reserved */ - PWM_FLT_t FLT[4]; /**< Fault registers 0, 1, 2 and 3 */ - __I uint32_t _RESERVED2[368];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} PWM_TypeDef; - -/** - * @brief Quadrature Encoder Interface - */ -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __I uint32_t STAT; /**< Status */ - __IO uint32_t POS; /**< Position */ - __IO uint32_t MAXPOS; /**< Maximum Position */ - __IO uint32_t LOAD; /**< Timer Load */ - __I uint32_t TIME; /**< Timer */ - __I uint32_t COUNT; /**< Velocity Counter */ - __I uint32_t SPEED; /**< Velocity */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ -} QEI_TypeDef; - -/** - * @brief Synchronous Serial Interface - */ -typedef struct -{ - __IO uint32_t CR0; /**< Control 0 */ - __IO uint32_t CR1; /**< Control 1 */ - __IO uint32_t DR; /**< Data */ - __I uint32_t SR; /**< Status */ - __IO uint32_t CPSR; /**< Clock Prescale */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t DMACTL; /**< DMA Control */ - __I uint32_t _RESERVED0[1000];/**< Reserved */ - __IO uint32_t CC; /**< Clock Configuration */ -} SSI_TypeDef; - -/** - * @brief System Control - */ -typedef struct -{ - __I uint32_t DID0; /**< Device Identification 0 */ - __I uint32_t DID1; /**< Device Identification 1 */ - __I uint32_t RESERVED0[10]; /**< Reserved */ - __IO uint32_t PBORCTL; /**< Brown-Out Reset Control */ - __I uint32_t RESERVED1[7]; /**< Reserved */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t IMC; /**< Interrupt Mask Control */ - __IO uint32_t MISC; /**< Interrupt Status and Clear */ - __IO uint32_t RESC; /**< Reset Cause */ - __IO uint32_t RCC; /**< Run-Mode Clock Configuration */ - __I uint32_t RESERVED2[2]; /**< Reserved */ - __IO uint32_t GPIOHBCTL; /**< GPIO High-Performance Bus Control */ - __IO uint32_t RCC2; /**< Run-Mode Clock Configuration 2 */ - __I uint32_t RESERVED3[2]; /**< Reserved */ - __IO uint32_t MOSCCTL; /**< Main Oscillator Control */ - __I uint32_t RESERVED4[49]; /**< Reserved */ - __IO uint32_t DSLPCLKCFG; /**< Deep Sleep Clock Configuration */ - __I uint32_t RESERVED5[1]; /**< Reserved */ - __I uint32_t SYSPROP; /**< System Properties */ - __IO uint32_t PIOSCCAL; /**< PIOSC Calibration */ - __I uint32_t PIOSCSTAT; /**< PIOSC Statistics */ - __I uint32_t RESERVED6[2]; /**< Reserved */ - __I uint32_t PLLFREQ0; /**< PLL Frequency 0 */ - __I uint32_t PLLFREQ1; /**< PLL Frequency 1 */ - __I uint32_t PLLSTAT; /**< PLL Frequency Status */ - __I uint32_t RESERVED7[7]; /**< Reserved */ - __IO uint32_t SLPPWRCFG; /**< Sleep Power Configuration */ - __IO uint32_t DSLPPWRCFG; /**< Deep-Sleep Power Configuration */ - __I uint32_t RESERVED8[9]; /**< Reserved */ - __IO uint32_t LDOSPCTL; /**< LDO Sleep Power Control */ - __I uint32_t LDOSPCAL; /**< LDO Sleep Power Calibration */ - __IO uint32_t LDODPCTL; /**< LDO Deep-Sleep Power Control */ - __I uint32_t LDODPCAL; /**< LDO Deep-Sleep Power Calibration */ - __I uint32_t RESERVED9[2]; /**< Reserved */ - __I uint32_t SDPMST; /**< Sleep/Deep-Sleep Power Mode Status */ - __I uint32_t RESERVED10[76]; /**< Reserved */ - __I uint32_t PPWD; /**< WDT Peripheral Present */ - __I uint32_t PPTIMER; /**< GPT Peripheral Present */ - __I uint32_t PPGPIO; /**< GPIO Peripheral Present */ - __I uint32_t PPDMA; /**< UDMA Peripheral Present */ - __I uint32_t RESERVED11[1]; /**< Reserved */ - __I uint32_t PPHIB; /**< HIB Peripheral Present */ - __I uint32_t PPUART; /**< UART Peripheral Present */ - __I uint32_t PPSSI; /**< SSI Peripheral Present */ - __I uint32_t PPI2C; /**< I2C Peripheral Present */ - __I uint32_t RESERVED12[1]; /**< Reserved */ - __I uint32_t PPUSB; /**< USB Peripheral Present */ - __I uint32_t RESERVED13[2]; /**< Reserved */ - __I uint32_t PPCAN; /**< CAN Peripheral Present */ - __I uint32_t PPADC; /**< ADC Peripheral Present */ - __I uint32_t PPACMP; /**< ACMP Peripheral Present */ - __I uint32_t PPPWM; /**< PWM Peripheral Present */ - __I uint32_t PPQEI; /**< QEI Peripheral Present */ - __I uint32_t RESERVED14[4]; /**< Reserved */ - __I uint32_t PPEEPROM; /**< EEPROM Peripheral Present */ - __I uint32_t PPWTIMER; /**< Wide GPT Peripheral Present */ - __I uint32_t RESERVED15[104];/**< Reserved */ - __IO uint32_t SRWD; /**< WDT Software Reset */ - __IO uint32_t SRTIMER; /**< GPT Software Reset */ - __IO uint32_t SRGPIO; /**< GPIO Software Reset */ - __IO uint32_t SRDMA; /**< UDMA Software Reset */ - __I uint32_t RESERVED16[1]; /**< Reserved */ - __IO uint32_t SRHIB; /**< HIB Software Reset */ - __IO uint32_t SRUART; /**< UART Software Reset */ - __IO uint32_t SRSSI; /**< SSI Software Reset */ - __IO uint32_t SRI2C; /**< I2C Software Reset */ - __I uint32_t RESERVED17[1]; /**< Reserved */ - __IO uint32_t SRUSB; /**< USB Software Reset */ - __I uint32_t RESERVED18[2]; /**< Reserved */ - __IO uint32_t SRCAN; /**< CAN Software Reset */ - __IO uint32_t SRADC; /**< ADC Software Reset */ - __IO uint32_t SRACMP; /**< ACMP Software Reset */ - __IO uint32_t SRPWM; /**< PWM Software Reset */ - __IO uint32_t SRQEI; /**< QEI Software Reset */ - __I uint32_t RESERVED19[4]; /**< Reserved */ - __IO uint32_t SREEPROM; /**< EEPROM Software Reset */ - __IO uint32_t SRWTIMER; /**< Wide GPT Software Reset */ - __I uint32_t RESERVED20[40]; /**< Reserved */ - __IO uint32_t RCGCWD; /**< WDT Run Mode Clock Gating Control */ - __IO uint32_t RCGCTIMER; /**< GPT Run Mode Clock Gating Control */ - __IO uint32_t RCGCGPIO; /**< GPIO Run Mode Clock Gating Control */ - __IO uint32_t RCGCDMA; /**< UDMA Run Mode Clock Gating Control */ - __I uint32_t RESERVED21[1]; /**< Reserved */ - __IO uint32_t RCGCHIB; /**< HIB Run Mode Clock Gating Control */ - __IO uint32_t RCGCUART; /**< UART Run Mode Control */ - __IO uint32_t RCGCSSI; /**< SSI Run Mode Clock Gating Control */ - __IO uint32_t RCGCI2C; /**< I2C Run Mode Clock Gating Control */ - __I uint32_t RESERVED22[1]; /**< Reserved */ - __IO uint32_t RCGCUSB; /**< USB Run Mode Clock Gating Control */ - __I uint32_t RESERVED23[2]; /**< Reserved */ - __IO uint32_t RCGCCAN; /**< CAN Run Mode Clock Gating Control */ - __IO uint32_t RCGCADC; /**< ADC Run Mode Clock Gating Control */ - __IO uint32_t RCGCACMP; /**< ACMP Run Mode Clock Gating Control */ - __IO uint32_t RCGCPWM; /**< PWM Run Mode Clock Gating Control */ - __IO uint32_t RCGCQEI; /**< QEI Run Mode Clock Gating Control */ - __I uint32_t RESERVED24[4]; /**< Reserved */ - __IO uint32_t RCGCEEPROM; /**< EEPROM Run Mode Clock Gating Control */ - __IO uint32_t RCGCWTIMER; /**< Wide GPT Run Mode Clock Gating Control */ - __I uint32_t RESERVED25[40]; /**< Reserved */ - __IO uint32_t SCGCWD; /**< WDT Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCTIMER; /**< GPT Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCGPIO; /**< GPIO Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCDMA; /**< UDMA Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED26[1]; /**< Reserved */ - __IO uint32_t SCGCHIB; /**< HIB Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCUART; /**< UART Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCSSI; /**< SSI Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCI2C; /**< I2C Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED27[1]; /**< Reserved */ - __IO uint32_t SCGCUSB; /**< USB Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED28[2]; /**< Reserved */ - __IO uint32_t SCGCCAN; /**< CAN Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCADC; /**< ADC Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCACMP; /**< ACMP Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCPWM; /**< PWM Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCQEI; /**< QEI Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED29[4]; /**< Reserved */ - __IO uint32_t SCGCEEPROM; /**< EEPROM Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCWTIMER; /**< Wide GPT Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED30[40]; /**< Reserved */ - __IO uint32_t DCGCWD; /**< WDT Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCTIMER; /**< GPT Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCGPIO; /**< GPIO Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCDMA; /**< UDMA Deep-Sleep Mode Clock Gating - Control */ - __I uint32_t RESERVED31[1]; /**< Reserved */ - __IO uint32_t DCGCHIB; /**< HIB Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCUART; /**< UART Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCSSI; /**< SSI Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCI2C; /**< I2C Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED32[1]; /**< Reserved */ - __IO uint32_t DCGCUSB; /**< USB Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED33[2]; /**< Reserved */ - __IO uint32_t DCGCCAN; /**< CAN Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCADC; /**< ADC Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCACMP; /**< ACMP Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCPWM; /**< PWM Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCQEI; /**< QEI Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED34[4]; /**< Reserved */ - __IO uint32_t DCGCEEPROM; /**< EEPROM Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCWTIMER; /**< Wide GPT Deep-Sleep Mode Clock Gating - Control */ - __I uint32_t RESERVED35[104];/**< Reserved */ - __IO uint32_t PRWD; /**< WDT Peripheral Ready */ - __IO uint32_t PRTIMER; /**< GPT Peripheral Ready */ - __IO uint32_t PRGPIO; /**< GPIO Peripheral Ready */ - __IO uint32_t PRDMA; /**< UDMA Peripheral Ready */ - __I uint32_t RESERVED36[1]; /**< Reserved */ - __IO uint32_t PRHIB; /**< HIB Peripheral Ready */ - __IO uint32_t PRUART; /**< UART Peripheral Ready */ - __IO uint32_t PRSSI; /**< SSI Peripheral Ready */ - __IO uint32_t PRI2C; /**< I2C Peripheral Ready */ - __I uint32_t RESERVED37[1]; /**< Reserved */ - __IO uint32_t PRUSB; /**< USB Peripheral Ready */ - __I uint32_t RESERVED38[2]; /**< Reserved */ - __IO uint32_t PRCAN; /**< CAN Peripheral Ready */ - __IO uint32_t PRADC; /**< ADC Peripheral Ready */ - __IO uint32_t PRACMP; /**< ACMP Peripheral Ready */ - __IO uint32_t PRPWM; /**< PWM Peripheral Ready */ - __IO uint32_t PRQEI; /**< QEI Peripheral Ready */ - __I uint32_t RESERVED39[4]; /**< Reserved */ - __IO uint32_t PREEPROM; /**< EEPROM Peripheral Ready */ - __IO uint32_t PRWTIMER; /**< Wide GPT Peripheral Ready */ -} SYSCTL_TypeDef; - -/** - * @brief Universal Asynchronous Receiver/Transmitter - */ -typedef struct -{ - __IO uint32_t DR; /**< Data */ - union { - __I uint32_t RSR; /**< Receive Status */ - __O uint32_t ECR; /**< Error Clear */ - }; - __I uint32_t _RESERVED0[4]; /**< Reserved */ - __I uint32_t FR; /**< Flag */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - __IO uint32_t ILPR; /**< IrDA Low-Power Register */ - __IO uint32_t IBRD; /**< Integer Baud-Rate Divisor */ - __IO uint32_t FBRD; /**< Fractional Baud-Rate Divisor */ - __IO uint32_t LCRH; /**< Line Control */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t IFLS; /**< Interrupt FIFO Level Select */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t DMACTL; /**< DMA Control */ - __I uint32_t _RESERVED2[22]; /**< Reserved */ - __IO uint32_t BIT9ADDR; /**< 9-Bit Self Address */ - __IO uint32_t BIT9AMASK; /**< 9-Bit Self Address Mask */ - __I uint32_t _RESERVED3[965];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __I uint32_t _RESERVED4[1]; /**< Reserved */ - __IO uint32_t CC; /**< Clock Configuration */ -} UART_TypeDef; - -/** - * @brief Micro Direct Memory Access - */ -typedef struct -{ - __IO uint32_t SET; /**< Set */ - __O uint32_t CLR; /**< Clear */ -} UDMA_SC_t; - -typedef struct -{ - __IO uint32_t STAT; /**< Status */ - __O uint32_t CFG; /**< Configuration */ - __IO uint32_t CTLBASE; /**< Channel Control Base Pointer */ - __IO uint32_t ALTBASE; /**< Alternate Channel Control Base Pointer */ - __IO uint32_t WAITSTAT; /**< Channel Wait-on-Request Status */ - __O uint32_t SWREQ; /**< Channel Software Request */ - __IO uint32_t USEBURSTSET; /**< Channel Useburst Set */ - __O uint32_t USEBURSTCLR; /**< Channel Useburst Clear */ - __IO uint32_t REQMASKSET; /**< Channel Request Mask Set */ - __O uint32_t REQMASKCLR; /**< Channel Request Mask Clear */ - __IO uint32_t ENASET; /**< Channel Enable Set */ - __O uint32_t ENACLR; /**< Channel Enable Clear */ - __IO uint32_t ALTSET; /**< Channel Primary Alternate Set */ - __O uint32_t ALTCLR; /**< Channel Primary Alternate Clear */ - __IO uint32_t PRIOSET; /**< Channel Priority Set */ - __O uint32_t PRIOCLR; /**< Channel Priority Clear */ - __I uint32_t _RESERVED0[3]; /**< Reserved */ - __IO uint32_t ERRCLR; /**< Bus Error Clear */ - __I uint32_t _RESERVED1[300];/**< Reserved */ - __IO uint32_t CHASGN; /**< Channel Assignment */ - __IO uint32_t CHIS; /**< Channel Interrupt Status */ - __I uint32_t _RESERVED2[2]; /**< Reserved */ - __IO uint32_t CHMAP[4]; /**< Channel Map Select 0, 1, 2 and 3 */ -} UDMA_TypeDef; - -// USB - -/** - * @brief Watchdog Timer - */ -typedef struct -{ - __IO uint32_t LOAD; /**< Load */ - __I uint32_t VALUE; /**< Value */ - __IO uint32_t CTL; /**< Control */ - __O uint32_t ICR; /**< Interrupt Clear */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __I uint32_t _RESERVED0[256];/**< Reserved */ - __IO uint32_t TEST; /**< Test */ - __I uint32_t _RESERVED1[505];/**< Reserved */ - __IO uint32_t LOCK; /**< Lock */ -} WDT_TypeDef; - -/** - * @} - */ - -/** - * @addtogroup Peripheral_memorymap - * @{ - */ - -#define SYSCTL_BASE 0x400FE000 -#define HIB_BASE 0x400FC000 -#define FLASH_BASE 0x400FD000 -#define EEPROM_BASE 0x400AF000 -#define UDMA_BASE 0x400FF000 -#define GPIOA_APB_BASE 0x40004000 -#define GPIOA_AHB_BASE 0x40058000 -#define GPIOB_APB_BASE 0x40005000 -#define GPIOB_AHB_BASE 0x40059000 -#define GPIOC_APB_BASE 0x40006000 -#define GPIOC_AHB_BASE 0x4005A000 -#define GPIOD_APB_BASE 0x40007000 -#define GPIOD_AHB_BASE 0x4005B000 -#define GPIOE_APB_BASE 0x40024000 -#define GPIOE_AHB_BASE 0x4005C000 -#define GPIOF_APB_BASE 0x40025000 -#define GPIOF_AHB_BASE 0x4005D000 -#define GPIOG_APB_BASE 0x40026000 -#define GPIOG_AHB_BASE 0x4005E000 -#define GPIOH_APB_BASE 0x40027000 -#define GPIOH_AHB_BASE 0x4005F000 -#define GPIOJ_APB_BASE 0x4003D000 -#define GPIOJ_AHB_BASE 0x40060000 -#define GPIOK_AHB_BASE 0x40061000 -#define GPIOL_AHB_BASE 0x40062000 -#define GPIOM_AHB_BASE 0x40063000 -#define GPION_AHB_BASE 0x40064000 -#define GPIOP_AHB_BASE 0x40065000 -#define GPIOQ_AHB_BASE 0x40066000 -#define GPT0_BASE 0x40030000 -#define GPT1_BASE 0x40031000 -#define GPT2_BASE 0x40032000 -#define GPT3_BASE 0x40033000 -#define GPT4_BASE 0x40034000 -#define GPT5_BASE 0x40035000 -#define WGPT0_BASE 0x40036000 -#define WGPT1_BASE 0x40037000 -#define WGPT2_BASE 0x4004C000 -#define WGPT3_BASE 0x4004D000 -#define WGPT4_BASE 0x4004E000 -#define WGPT5_BASE 0x4004F000 -#define WDT0_BASE 0x40000000 -#define WDT1_BASE 0x40001000 -#define ADC0_BASE 0x40038000 -#define ADC1_BASE 0x40039000 -#define UART0_BASE 0x4000C000 -#define UART1_BASE 0x4000D000 -#define UART2_BASE 0x4000E000 -#define UART3_BASE 0x4000F000 -#define UART4_BASE 0x40010000 -#define UART5_BASE 0x40011000 -#define UART6_BASE 0x40012000 -#define UART7_BASE 0x40013000 -#define SSI0_BASE 0x40008000 -#define SSI1_BASE 0x40009000 -#define SSI2_BASE 0x4000A000 -#define SSI3_BASE 0x4000B000 -#define I2C0_BASE 0x40020000 -#define I2C1_BASE 0x40021000 -#define I2C2_BASE 0x40022000 -#define I2C3_BASE 0x40023000 -#define I2C4_BASE 0x40023000 -#define I2C5_BASE 0x40023000 -#define CAN0_BASE 0x40040000 -#define CAN1_BASE 0x40041000 -// usb -#define ACMP_BASE 0x4003C000 -#define PWM0_BASE 0x40028000 -#define PWM1_BASE 0x40029000 -#define QEI0_BASE 0x4002C000 -#define QEI1_BASE 0x4002D000 - -/** - * @} - */ - -/** - * @addtogroup Peripheral_declaration - * @{ - */ - -#define SYSCTL ((SYSCTL_TypeDef *) SYSCTL_BASE) -#define HIB ((HIB_TypeDef *) HIB_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_BASE) -#define EEPROM ((EEPROM_TypeDef *) EEPROM_BASE) -#define UDMA ((UDMA_TypeDef *) UDMA_BASE) -#define GPIOA_APB ((GPIO_TypeDef *) GPIOA_APB_BASE) -#define GPIOA_AHB ((GPIO_TypeDef *) GPIOA_AHB_BASE) -#define GPIOB_APB ((GPIO_TypeDef *) GPIOB_APB_BASE) -#define GPIOB_AHB ((GPIO_TypeDef *) GPIOB_AHB_BASE) -#define GPIOC_APB ((GPIO_TypeDef *) GPIOC_APB_BASE) -#define GPIOC_AHB ((GPIO_TypeDef *) GPIOC_AHB_BASE) -#define GPIOD_APB ((GPIO_TypeDef *) GPIOD_APB_BASE) -#define GPIOD_AHB ((GPIO_TypeDef *) GPIOD_AHB_BASE) -#define GPIOE_APB ((GPIO_TypeDef *) GPIOE_APB_BASE) -#define GPIOE_AHB ((GPIO_TypeDef *) GPIOE_AHB_BASE) -#define GPIOF_APB ((GPIO_TypeDef *) GPIOF_APB_BASE) -#define GPIOF_AHB ((GPIO_TypeDef *) GPIOF_AHB_BASE) -#define GPIOG_APB ((GPIO_TypeDef *) GPIOG_APB_BASE) -#define GPIOG_AHB ((GPIO_TypeDef *) GPIOG_AHB_BASE) -#define GPIOH_APB ((GPIO_TypeDef *) GPIOH_APB_BASE) -#define GPIOH_AHB ((GPIO_TypeDef *) GPIOH_AHB_BASE) -#define GPIOJ_APB ((GPIO_TypeDef *) GPIOJ_APB_BASE) -#define GPIOJ_AHB ((GPIO_TypeDef *) GPIOJ_AHB_BASE) -#define GPIOK_AHB ((GPIO_TypeDef *) GPIOK_AHB_BASE) -#define GPIOL_AHB ((GPIO_TypeDef *) GPIOL_AHB_BASE) -#define GPIOM_AHB ((GPIO_TypeDef *) GPIOM_AHB_BASE) -#define GPION_AHB ((GPIO_TypeDef *) GPION_AHB_BASE) -#define GPIOP_AHB ((GPIO_TypeDef *) GPIOP_AHB_BASE) -#define GPIOQ_AHB ((GPIO_TypeDef *) GPIOQ_AHB_BASE) -#define GPT0 ((GPT_TypeDef *) GPT0_BASE) -#define GPT1 ((GPT_TypeDef *) GPT1_BASE) -#define GPT2 ((GPT_TypeDef *) GPT2_BASE) -#define GPT3 ((GPT_TypeDef *) GPT3_BASE) -#define GPT4 ((GPT_TypeDef *) GPT4_BASE) -#define GPT5 ((GPT_TypeDef *) GPT5_BASE) -#define WGPT0 ((GPT_TypeDef *) WGPT0_BASE) -#define WGPT1 ((GPT_TypeDef *) WGPT1_BASE) -#define WGPT2 ((GPT_TypeDef *) WGPT2_BASE) -#define WGPT3 ((GPT_TypeDef *) WGPT3_BASE) -#define WGPT4 ((GPT_TypeDef *) WGPT4_BASE) -#define WGPT5 ((GPT_TypeDef *) WGPT5_BASE) -#define WDT0 ((WDT_TypeDef *) WDT0_BASE) -#define WDT1 ((WDT_TypeDef *) WDT1_BASE) -#define ADC0 ((ADC_TypeDef*) ADC0_BASE) -#define ADC1 ((ADC_TypeDef*) ADC1_BASE) -#define UART0 ((UART_TypeDef *) UART0_BASE) -#define UART1 ((UART_TypeDef *) UART1_BASE) -#define UART2 ((UART_TypeDef *) UART2_BASE) -#define UART3 ((UART_TypeDef *) UART3_BASE) -#define UART4 ((UART_TypeDef *) UART4_BASE) -#define UART5 ((UART_TypeDef *) UART5_BASE) -#define UART6 ((UART_TypeDef *) UART6_BASE) -#define UART7 ((UART_TypeDef *) UART7_BASE) -#define SSI0 ((SSI_TypeDef *) SSI0_BASE) -#define SSI1 ((SSI_TypeDef *) SSI1_BASE) -#define SSI2 ((SSI_TypeDef *) SSI2_BASE) -#define SSI3 ((SSI_TypeDef *) SSI3_BASE) -#define I2C0 ((I2C_TypeDef *) I2C0_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define I2C4 ((I2C_TypeDef *) I2C4_BASE) -#define I2C5 ((I2C_TypeDef *) I2C5_BASE) -#define CAN0 ((CAN_TypeDef *) CAN0_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -// usb -#define ACMP ((ACMP_TypeDef *) ACMP_BASE) -#define PWM0 ((PWM_TypeDef *) PWM0_BASE) -#define PWM1 ((PWM_TypeDef *) PWM1_BASE) -#define QEI0 ((QEI_TypeDef *) QEI0_BASE) -#define QEI1 ((QEI_TypeDef *) QEI1_BASE) - -/** - * @} - */ - -#endif /* __TM4C123x_H */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.c b/os/hal/ports/TIVA/TM4C129x/hal_lld.c index 60d6763..7af3cc4 100644 --- a/os/hal/ports/TIVA/TM4C129x/hal_lld.c +++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -76,8 +76,8 @@ void tiva_clock_init(void) /* * 2. Power up the MOSC by clearing the NOXTAL bit in the MOSCCTL register. */ - moscctl = SYSCTL->MOSCCTL; - moscctl &= ~MOSCCTL_NOXTAL; + moscctl = HWREG(SYSCTL_MOSCCTL); + moscctl &= ~SYSCTL_MOSCCTL_NOXTAL; /* * 3. If single-ended MOSC mode is required, the MOSC is ready to use. If crystal mode is required, @@ -85,18 +85,18 @@ void tiva_clock_init(void) * (RIS), indicating MOSC crystal mode is ready. */ #if TIVA_MOSC_SINGLE_ENDED - SYSCTL->MOSCCTL = moscctl; + HWREG(SYSCTL_MOSCCTL) = moscctl; #else - moscctl &= ~MOSCCTL_PWRDN; - SYSCTL->MOSCCTL = moscctl; + moscctl &= ~SYSCTL_MOSCCTL_PWRDN; + HWREG(SYSCTL_MOSCCTL) = moscctl; - while (!(SYSCTL->RIS & SYSCTL_RIS_MOSCPUPRIS)); + while (!(HWREG(SYSCTL_RIS) & SYSCTL_RIS_MOSCPUPRIS)); #endif /* * 4. Set the OSCSRC field to 0x3 in the RSCLKCFG register at offset 0x0B0. */ - rsclkcfg = SYSCTL->RSCLKCFG; + rsclkcfg = HWREG(SYSCTL_RSCLKCFG); rsclkcfg |= TIVA_RSCLKCFG_OSCSRC; @@ -109,44 +109,42 @@ void tiva_clock_init(void) * 6. Write the PLLFREQ0 and PLLFREQ1 registers with the values of Q, N, MINT, and MFRAC to * the configure the desired VCO frequency setting. */ - SYSCTL->PLLFREQ1 = (0x04 << 0); // 5 - 1 - SYSCTL->PLLFREQ0 = (0x60 << 0) | PLLFREQ0_PLLPWR; + HWREG(SYSCTL_PLLFREQ1) = (0x04 << 0); // 5 - 1 + HWREG(SYSCTL_PLLFREQ0) = (0x60 << 0) | SYSCTL_PLLFREQ0_PLLPWR; /* * 7. Write the MEMTIM0 register to correspond to the new system clock setting. */ - SYSCTL->MEMTIM0 = (MEMTIM0_FBCHT_3_5 | MEMTIM0_FWS_5 | MEMTIM0_EBCHT_3_5 | MEMTIM0_EWS_5 | MEMTIM0_MB1); + HWREG(SYSCTL_MEMTIM0) = (SYSCTL_MEMTIM0_FBCHT_3_5 | (5 << SYSCTL_MEMTIM0_FWS_S) | SYSCTL_MEMTIM0_EBCHT_3_5 | (5 << SYSCTL_MEMTIM0_EWS_S) | SYSCTL_MEMTIM0_MB1); /* * Wait for the PLLSTAT register to indicate the PLL has reached lock at the new operating point * (or that a timeout period has passed and lock has failed, in which case an error condition exists * and this sequence is abandoned and error processing is initiated). */ - while (!SYSCTL->PLLSTAT & PLLSTAT_LOCK); + while (!HWREG(SYSCTL_PLLSTAT) & SYSCTL_PLLSTAT_LOCK); /* * 9. Write the RSCLKCFG register's PSYSDIV value, set the USEPLL bit to enabled, and MEMTIMU * bit. */ - rsclkcfg = SYSCTL->RSCLKCFG; + rsclkcfg = HWREG(SYSCTL_RSCLKCFG); - rsclkcfg |= (RSCLKCFG_USEPLL | (0x03 << 0) | (0x03 << 20) | (0x03 << 24)); + rsclkcfg |= (SYSCTL_RSCLKCFG_USEPLL | (0x03 << 0) | (0x03 << 20) | (0x03 << 24)); //rsclkcfg |= ((0x03 << 0) | (1 << 28) | (0x03 << 20)); - rsclkcfg |= RSCLKCFG_MEMTIMU; + rsclkcfg |= SYSCTL_RSCLKCFG_MEMTIMU; // set new configuration - SYSCTL->RSCLKCFG = rsclkcfg; + HWREG(SYSCTL_RSCLKCFG) = rsclkcfg; #if HAL_USE_PWM #if TIVA_PWM_USE_PWM0 - PWM0->CC = TIVA_PWM_FIELDS; + HWREG(PWM0_CC) = TIVA_PWM_FIELDS; #endif #endif } -/** - * @} - */ +/** @} */ diff --git a/os/hal/ports/TIVA/TM4C129x/hal_lld.h b/os/hal/ports/TIVA/TM4C129x/hal_lld.h index e5c667d..1080fae 100644 --- a/os/hal/ports/TIVA/TM4C129x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C129x/hal_lld.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -38,170 +38,8 @@ * @name Platform identification * @{ */ - #define PLATFORM_NAME "Tiva C Series TM4C129x" - -/** - * @} - */ - -/** - * @name RIS register bits definitions - * @{ - */ - -#define SYSCTL_RIS_PLLLRIS (1 << 6) -#define SYSCTL_RIS_MOSCPUPRIS (1 << 8) - -/** - * @} - */ - -/** - * @name MOSCCTL register bits definitions - * @{ - */ - -#define MOSCCTL_CVAL (1 << 0) -#define MOSCCTL_MOSCIM (1 << 1) -#define MOSCCTL_NOXTAL (1 << 2) -#define MOSCCTL_PWRDN (1 << 3) -#define MOSCCTL_OSCRNG (1 << 4) - -/** - * @} - */ - -/** - * @name RSCLKCFG register bits definitions - * @{ - */ - -#define RSCLKCFG_PSYSDIV_bm (0xfffff << 0) -#define RSCLKCFG_OSYSDIV_bm (0xfffff << 10 - -#define RSCLKCFG_OSCSRC_bm (0xff << 20) -#define RSCLKCFG_OSCSRC_PIOSC (0 << 20) -#define RSCLKCFG_OSCSRC_LFIOSC (0x02 << 20) -#define RSCLKCFG_OSCSRC_MOSC (0x03 << 20) -#define RSCLKCFG_OSCSRC_RTCOSC (0x04 << 20) - -#define RSCLKCFG_PLLSRC_bm (0xff << 24) -#define RSCLKCFG_PLLSRC_PIOSC (0 << 24) -#define RSCLKCFG_PLLSRC_MOSC (0x03 << 24) - -#define RSCLKCFG_USEPLL (1 << 28) - -#define RSCLKCFG_ACG (1 << 29) - -#define RSCLKCFG_NEWFREQ (1 << 30) - -#define RSCLKCFG_MEMTIMU (1 << 31) - -/** - * @} - */ - -/** - * @name PLLFREQ0 register bits definitions - * The PLL frequency can be calculated using the following equation: - * fVCO = (fIN * MDIV) - * where - * fIN = fXTAL/(Q+1)(N+1) or fPIOSC/(Q+1)(N+1) - * MDIV = MINT + (MFRAC / 1024) - * The Q and N values are programmed in the PLLFREQ1 register. Note that to reduce jitter, MFRAC - * should be programmed to 0x0. - * @{ - */ - -#define PLLFREQ0_MINT_bm (0xfffff << 0) -#define PLLFREQ0_MFRAC_bm (0xfffff << 10) -#define PLLFREQ0_PLLPWR (1 << 23) - -/** - * @} - */ - -/** - * @name PLLFREQ1 register bits definitions - * @{ - */ - -#define PLLFREQ1_N_bm (0x7ff << 0) -#define PLLFREQ1_Q_bm (0x7ff << 8) - -/** - * @} - */ - -/** - * @name MEMTIM0 register bits definitions - * @{ - */ - -#define MEMTIM0_FWS_bm (0xff << 0) -#define MEMTIM0_FWS_0 (0x00 << 0) -#define MEMTIM0_FWS_1 (0x01 << 0) -#define MEMTIM0_FWS_2 (0x02 << 0) -#define MEMTIM0_FWS_3 (0x03 << 0) -#define MEMTIM0_FWS_4 (0x04 << 0) -#define MEMTIM0_FWS_5 (0x05 << 0) -#define MEMTIM0_FWS_6 (0x06 << 0) -#define MEMTIM0_FWS_7 (0x07 << 0) - -#define MEMTIM0_FBCE (1 << 5) - -#define MEMTIM0_FBCHT_bm (0xff << 6) -#define MEMTIM0_FBCHT_0_5 (0x00 << 6) -#define MEMTIM0_FBCHT_1 (0x01 << 6) -#define MEMTIM0_FBCHT_1_5 (0x02 << 6) -#define MEMTIM0_FBCHT_2 (0x03 << 6) -#define MEMTIM0_FBCHT_2_5 (0x04 << 6) -#define MEMTIM0_FBCHT_3 (0x05 << 6) -#define MEMTIM0_FBCHT_3_5 (0x06 << 6) -#define MEMTIM0_FBCHT_4 (0x07 << 6) -#define MEMTIM0_FBCHT_4_5 (0x08 << 6) - -#define MEMTIM0_EWS_bm (0xff << 16) -#define MEMTIM0_EWS_0 (0x00 << 16) -#define MEMTIM0_EWS_1 (0x01 << 16) -#define MEMTIM0_EWS_2 (0x02 << 16) -#define MEMTIM0_EWS_3 (0x03 << 16) -#define MEMTIM0_EWS_4 (0x04 << 16) -#define MEMTIM0_EWS_5 (0x05 << 16) -#define MEMTIM0_EWS_6 (0x06 << 16) -#define MEMTIM0_EWS_7 (0x07 << 16) - -#define MEMTIM0_EBCE (1 << 21) - -#define MEMTIM0_EBCHT_bm (0xff << 22) -#define MEMTIM0_EBCHT_0_5 (0x00 << 22) -#define MEMTIM0_EBCHT_1 (0x01 << 22) -#define MEMTIM0_EBCHT_1_5 (0x02 << 22) -#define MEMTIM0_EBCHT_2 (0x03 << 22) -#define MEMTIM0_EBCHT_2_5 (0x04 << 22) -#define MEMTIM0_EBCHT_3 (0x05 << 22) -#define MEMTIM0_EBCHT_3_5 (0x06 << 22) -#define MEMTIM0_EBCHT_4 (0x07 << 22) -#define MEMTIM0_EBCHT_4_5 (0x08 << 22) - -// XXX: what is this? -#define MEMTIM0_MB1 0x00100010 // MB1 = Must be one - -/** - * @} - */ - -/** - * @name PLLSTAT register bits definitions - * @{ - */ - -#define PLLSTAT_LOCK (1 << 0) - -/** - * @} - */ +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -212,7 +50,7 @@ #endif #if !defined(TIVA_RSCLKCFG_OSCSRC) -#define TIVA_RSCLKCFG_OSCSRC RSCLKCFG_OSCSRC_MOSC +#define TIVA_RSCLKCFG_OSCSRC SYSCTL_RSCLKCFG_OSCSRC_MOSC #endif /*===========================================================================*/ @@ -229,55 +67,55 @@ /* * Oscillator-related checks. */ -#if !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_PIOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_LFIOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_MOSC) && \ - !(TIVA_RSCLKCFG_OSCSRC == RSCLKCFG_OSCSRC_RTCOSC) +#if !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_PIOSC) && \ + !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_LFIOSC) && \ + !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_MOSC) && \ + !(TIVA_RSCLKCFG_OSCSRC == SYSCTL_RSCLKCFG_OSCSRC_RTC) #error "Invalid value for TIVA_RSCLKCFG_OSCSRC defined" #endif #if TIVA_XTAL_VALUE == 4000000 -#define TIVA_XTAL_ (0x06 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4MHZ #elif TIVA_XTAL_VALUE == 4096000 -#define TIVA_XTAL_ (0x07 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_09MHZ #elif TIVA_XTAL_VALUE == 4915200 -#define TIVA_XTAL_ (0x08 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_4_91MHZ #elif TIVA_XTAL_VALUE == 5000000 -#define TIVA_XTAL_ (0x09 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5MHZ #elif TIVA_XTAL_VALUE == 5120000 -#define TIVA_XTAL_ (0x0a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_5_12MHZ #elif TIVA_XTAL_VALUE == 6000000 -#define TIVA_XTAL_ (0x0b << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6MHZ #elif TIVA_XTAL_VALUE == 6144000 -#define TIVA_XTAL_ (0x0c << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_6_14MHZ #elif TIVA_XTAL_VALUE == 7372800 -#define TIVA_XTAL_ (0x0d << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_7_37MHZ #elif TIVA_XTAL_VALUE == 8000000 -#define TIVA_XTAL_ (0x0e << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8MHZ #elif TIVA_XTAL_VALUE == 8192000 -#define TIVA_XTAL_ (0x0f << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_8_19MHZ #elif TIVA_XTAL_VALUE == 10000000 -#define TIVA_XTAL_ (0x10 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_10MHZ #elif TIVA_XTAL_VALUE == 12000000 -#define TIVA_XTAL_ (0x11 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12MHZ #elif TIVA_XTAL_VALUE == 12288000 -#define TIVA_XTAL_ (0x12 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_12_2MHZ #elif TIVA_XTAL_VALUE == 13560000 -#define TIVA_XTAL_ (0x13 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_13_5MHZ #elif TIVA_XTAL_VALUE == 14318180 -#define TIVA_XTAL_ (0x14 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_14_3MHZ #elif TIVA_XTAL_VALUE == 16000000 -#define TIVA_XTAL_ (0x15 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16MHZ #elif TIVA_XTAL_VALUE == 16384000 -#define TIVA_XTAL_ (0x16 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_16_3MHZ #elif TIVA_XTAL_VALUE == 18000000 -#define TIVA_XTAL_ (0x17 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_18MHZ #elif TIVA_XTAL_VALUE == 20000000 -#define TIVA_XTAL_ (0x18 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_20MHZ #elif TIVA_XTAL_VALUE == 24000000 -#define TIVA_XTAL_ (0x19 << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_24MHZ #elif TIVA_XTAL_VALUE == 25000000 -#define TIVA_XTAL_ (0x1a << 6) +#define TIVA_XTAL_ SYSCTL_RCC_XTAL_25MHZ #else #error "Invalid value for TIVA_XTAL_VALUE defined" #endif diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk index b8363f3..9702796 100644 --- a/os/hal/ports/TIVA/TM4C129x/platform.mk +++ b/os/hal/ports/TIVA/TM4C129x/platform.mk @@ -1,14 +1,34 @@ -# List of all the TM4C129x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_mac_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD +# Required platform files. +PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x/hal_lld.c + +# Required include directories. +PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x + +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define")) +else +endif + +# Drivers compatible with the platform. +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/ADC/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPTM/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/I2C/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/MAC/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/PWM/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_isr.h b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h index 255bfd6..3db9ba3 100644 --- a/os/hal/ports/TIVA/TM4C129x/tiva_isr.h +++ b/os/hal/ports/TIVA/TM4C129x/tiva_isr.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -35,9 +35,9 @@ */ /* GPIO units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -98,10 +98,10 @@ #define TIVA_GPIOQ6_NUMBER 90 #define TIVA_GPIOQ7_NUMBER 91 #endif -#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\ - || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_GPIOA_HANDLER Vector40 #define TIVA_GPIOB_HANDLER Vector44 #define TIVA_GPIOC_HANDLER Vector48 @@ -170,85 +170,85 @@ #endif /* EPI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_EPI0_HANDLER Vector108 #define TIVA_EPI0_NUMBER 50 #endif /* CRC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) /* CRC has no interrupts.*/ #endif /* AES Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) /* no interrupts.*/ #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) \ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_AES_HANDLER Vector1BC #define TIVA_AES_NUMBER 95 #endif /* DES Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) /* no interrupts.*/ #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_DES_HANDLER Vector1C0 #define TIVA_DES_NUMBER 51 #endif /* SHA/MD5 Accelerator units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) /* no interrupts.*/ #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_SHA_MD5_HANDLER Vector1B8 #define TIVA_SHA_MD5_NUMBER 94 #endif /* GPT units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_GPT0A_HANDLER Vector8C #define TIVA_GPT0B_HANDLER Vector90 #define TIVA_GPT1A_HANDLER Vector94 @@ -285,26 +285,26 @@ #endif /* WDT units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_WDT_HANDLER Vector88 #define TIVA_WDT_NUMBER 18 #endif /* ADC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_ADC0_SEQ0_HANDLER Vector78 #define TIVA_ADC0_SEQ1_HANDLER Vector7C #define TIVA_ADC0_SEQ2_HANDLER Vector80 @@ -325,13 +325,13 @@ #endif /* UART units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_UART0_HANDLER Vector54 #define TIVA_UART1_HANDLER Vector58 #define TIVA_UART2_HANDLER VectorC4 @@ -352,13 +352,13 @@ #endif /* QSSI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_QSSI0_HANDLER Vector5C #define TIVA_QSSI1_HANDLER VectorC8 #define TIVA_QSSI2_HANDLER Vector118 @@ -371,13 +371,13 @@ #endif /* I2C units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_I2C0_HANDLER Vector60 #define TIVA_I2C1_HANDLER VectorD4 #define TIVA_I2C2_HANDLER Vector134 @@ -402,28 +402,28 @@ #endif /* 1-Wire Master units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) #define TIVA_HAS_1WIRE FALSE #endif -#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_1WIRE_HANDLER Vector1E4 #define TIVA_1WIRE_NUMBER 105 #endif /* CAN units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_CAN0_HANDLER VectorD8 #define TIVA_CAN1_HANDLER VectorDC @@ -432,69 +432,69 @@ #endif /* Ethernet MAC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\ - || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1297NCZAD)\ + || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) /* no interrupts.*/ #endif -#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_MAC_HANDLER VectorE0 #define TIVA_MAC_NUMBER 40 #endif /* Ethernet PHY units.*/ -#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \ - || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) +#if defined(PART_TM4C1290NCPDT)|| defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) \ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) /* no interrupts.*/ #endif -#if defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\ - || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) /* no interrupts.*/ #endif /* USB units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_USB0_HANDLER VectorE8 #define TIVA_USB0_NUMBER 42 #endif /* LCD units.*/ -#if defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_LCD_HANDLER Vector1C4 #define TIVA_LCD_NUMBER 97 #endif -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) /* no interrupts.*/ #endif /* AC units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_AC0_HANDLER VectorA4 #define TIVA_AC1_HANDLER VectorA8 #define TIVA_AC2_HANDLER VectorAC @@ -505,13 +505,13 @@ #endif /* PWM units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_PWM0FAULT_HANDLER Vector64 #define TIVA_PWM0GEN0_HANDLER Vector68 #define TIVA_PWM0GEN1_HANDLER Vector6C @@ -526,13 +526,13 @@ #endif /* QEI units.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_QEI0_HANLDER Vector74 #define TIVA_QEI0_NUMBER 13 diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h index 5815351..cd8344d 100644 --- a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h +++ b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -25,6 +25,27 @@ #ifndef _TIVA_REGISTRY_H_ #define _TIVA_REGISTRY_H_ +#if !defined(PART_TM4C1290NCPDT) && !defined(PART_TM4C1290NCZAD) && !defined(PART_TM4C1292NCPDT)\ + && !defined(PART_TM4C1292NCZAD) && !defined(PART_TM4C1294KCPDT) && !defined(PART_TM4C1294NCPDT)\ + && !defined(PART_TM4C1294NCZAD) && !defined(PART_TM4C1297NCZAD) && !defined(PART_TM4C1299KCZAD)\ + && !defined(PART_TM4C1299NCZAD) && !defined(PART_TM4C129CNCPDT) && !defined(PART_TM4C129CNCZAD)\ + && !defined(PART_TM4C129DNCPDT) && !defined(PART_TM4C129DNCZAD) && !defined(PART_TM4C129EKCPDT)\ + && !defined(PART_TM4C129ENCPDT) && !defined(PART_TM4C129ENCZAD) && !defined(PART_TM4C129LNCZAD)\ + && !defined(PART_TM4C129XKCZAD) && !defined(PART_TM4C129XNCZAD) +#error "No valid device defined." +#endif + +#if !defined(TARGET_IS_TM4C129_RA0) +#error "No valid device revision defined." +#endif + +/** + * @brief Sub-family identifier. + */ +#if !defined(TM4C129x) || defined(__DOXYGEN__) +#define TM4C129x +#endif + /*===========================================================================*/ /* Platform capabilities. */ /*===========================================================================*/ @@ -35,9 +56,9 @@ */ /* GPIO attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1292NCPDT) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C129CNCPDT) || defined(TM4C129DNCPDT)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -56,11 +77,12 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 120 #endif -#if defined(TM4C1290NCZAD) || defined(TM4C1292NCZAD) || defined(TM4C1294NCZAD)\ - || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCZAD) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_GPIOA TRUE #define TIVA_HAS_GPIOB TRUE #define TIVA_HAS_GPIOC TRUE @@ -79,80 +101,81 @@ #define TIVA_HAS_GPIOR TRUE #define TIVA_HAS_GPIOS TRUE #define TIVA_HAS_GPIOT TRUE +#define TIVA_GPIO_PINS 144 #endif /* EPI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_EPI0 TRUE #endif /* CRC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_CRC0 TRUE #endif /* AES Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) #define TIVA_HAS_AES FALSE #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) \ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) \ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_AES TRUE #endif /* DES Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) #define TIVA_HAS_DES FALSE #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_DES TRUE #endif /* SHA/MD5 Accelerator attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) #define TIVA_HAS_SHA_MD5 FALSE #endif -#if defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT)\ - || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT)\ - || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD)\ - || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT)\ + || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT)\ + || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD)\ + || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_SHA_MD5 TRUE #endif /* GPT attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_GPT0 TRUE #define TIVA_HAS_GPT1 TRUE #define TIVA_HAS_GPT2 TRUE @@ -170,37 +193,37 @@ #endif /* WDT attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_WDT0 TRUE #define TIVA_HAS_WDT1 TRUE #endif /* ADC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_ADC0 TRUE #define TIVA_HAS_ADC1 TRUE #endif /* UART attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_UART0 TRUE #define TIVA_HAS_UART1 TRUE #define TIVA_HAS_UART2 TRUE @@ -212,13 +235,13 @@ #endif /* QSSI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_QSSI0 TRUE #define TIVA_HAS_QSSI1 TRUE #define TIVA_HAS_QSSI2 TRUE @@ -226,13 +249,13 @@ #endif /* I2C attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_I2C0 TRUE #define TIVA_HAS_I2C1 TRUE #define TIVA_HAS_I2C2 TRUE @@ -246,113 +269,113 @@ #endif /* 1-Wire Master attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD) #define TIVA_HAS_1WIRE FALSE #endif -#if defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_1WIRE TRUE #endif /* CAN attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_CAN0 TRUE #define TIVA_HAS_CAN1 TRUE #endif /* Ethernet MAC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1297NCZAD)\ - || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1297NCZAD)\ + || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD) #define TIVA_HAS_ETHERNET_MAC FALSE #endif -#if defined(TM4C1292NCPDT) || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT)\ - || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD)\ - || defined(TM4C129EKCPDT) || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1292NCPDT) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT)\ + || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129EKCPDT) || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_ETHERNET_MAC TRUE #endif /* Ethernet PHY attributes.*/ -#if defined(TM4C1290NCPDT)|| defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT) \ - || defined(TM4C1292NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) +#if defined(PART_TM4C1290NCPDT)|| defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) \ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) #define TIVA_HAS_ETHERNET_PHY FALSE #endif -#if defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT) || defined(TM4C1294NCZAD)\ - || defined(TM4C1299KCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD)\ + || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_ETHERNET_PHY TRUE #endif /* USB attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_USB0 TRUE #endif /* LCD attributes.*/ -#if defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD) || defined(TM4C129DNCZAD)\ - || defined(TM4C129LNCZAD) || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C129DNCZAD)\ + || defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_LCD TRUE #endif -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT)\ - || defined(TM4C129CNCZAD) || defined(TM4C129DNCPDT) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT)\ + || defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) #define TIVA_HAS_LCD FALSE #endif /* AC attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_AC0 TRUE #define TIVA_HAS_AC1 TRUE #define TIVA_HAS_AC2 TRUE #endif /* PWM attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_PWM0 TRUE #define TIVA_HAS_PWM1 FALSE #endif /* QEI attributes.*/ -#if defined(TM4C1290NCPDT) || defined(TM4C1290NCZAD) || defined(TM4C1292NCPDT)\ - || defined(TM4C1292NCZAD) || defined(TM4C1294KCPDT) || defined(TM4C1294NCPDT)\ - || defined(TM4C1294NCZAD) || defined(TM4C1297NCZAD) || defined(TM4C1299KCZAD)\ - || defined(TM4C1299NCZAD) || defined(TM4C129CNCPDT) || defined(TM4C129CNCZAD)\ - || defined(TM4C129DNCPDT) || defined(TM4C129DNCZAD) || defined(TM4C129EKCPDT)\ - || defined(TM4C129ENCPDT) || defined(TM4C129ENCZAD) || defined(TM4C129LNCZAD)\ - || defined(TM4C129XKCZAD) || defined(TM4C129XNCZAD) +#if defined(PART_TM4C1290NCPDT) || defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT)\ + || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || defined(PART_TM4C1294NCPDT)\ + || defined(PART_TM4C1294NCZAD) || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD)\ + || defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || defined(PART_TM4C129CNCZAD)\ + || defined(PART_TM4C129DNCPDT) || defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT)\ + || defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || defined(PART_TM4C129LNCZAD)\ + || defined(PART_TM4C129XKCZAD) || defined(PART_TM4C129XNCZAD) #define TIVA_HAS_QEI0 TRUE #define TIVA_HAS_QEI1 FALSE #endif diff --git a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h b/os/hal/ports/TIVA/TM4C129x/tm4c129x.h deleted file mode 100644 index 5a5f4f2..0000000 --- a/os/hal/ports/TIVA/TM4C129x/tm4c129x.h +++ /dev/null @@ -1,1131 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @addtogroup CMSIS - * @{ - */ - -/** - * @addtogroup TM4C129x - * @{ - */ - -#ifndef __TM4C129x_H -#define __TM4C129x_H - -/** - * @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /**< MPU present */ -#define __NVIC_PRIO_BITS 3 /**< Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /**< Use different SysTick Config */ -#define __FPU_PRESENT 1 /**< FPU present */ - -/** - * @brief TM4C129x Interrupt Number Definitions - */ -typedef enum IRQn -{ - /* TODO: check interrupt numbers with tm4c129 device */ - /***** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14, /**< Cortex-M4 Non-Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -3, /**< Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ - /***** TM4C129x Specific Interrupt Numbers *********************************/ - GPIOA_IRQn = 0, /**< GPIO Port A */ - GPIOB_IRQn = 1, /**< GPIO Port B */ - GPIOC_IRQn = 2, /**< GPIO Port C */ - GPIOD_IRQn = 3, /**< GPIO Port D */ - GPIOE_IRQn = 4, /**< GPIO Port E */ - UART0_IRQn = 5, /**< UART0 */ - UART1_IRQn = 6, /**< UART1 */ - SSI0_IRQn = 7, /**< SSI0 */ - I2C0_IRQn = 8, /**< I2C0 */ - PWM0FAULT_IRQn = 9, /**< PWM0 Fault */ - PWM0GEN0_IRQn = 10, /**< PWM0 Generator 0 */ - PWM0GEN1_IRQn = 11, /**< PWM0 Generator 1 */ - PWM0GEN2_IRQn = 12, /**< PWM0 Generator 2 */ - QEI0_IRQn = 13, /**< QEI0 */ - ADC0SEQ0_IRQn = 14, /**< ADC0 Sequence 0 */ - ADC0SEQ1_IRQn = 15, /**< ADC0 Sequence 1 */ - ADC0SEQ2_IRQn = 16, /**< ADC0 Sequence 2 */ - ADC0SEQ3_IRQn = 17, /**< ADC0 Sequence 3 */ - WATCHDOG_IRQn = 18, /**< Watchdog Timers 0 and 1 */ - TIMER0A_IRQn = 19, /**< 16/32-Bit Timer 0A */ - TIMER0B_IRQn = 20, /**< 16/32-Bit Timer 0B */ - TIMER1A_IRQn = 21, /**< 16/32-Bit Timer 1A */ - TIMER1B_IRQn = 22, /**< 16/32-Bit Timer 1B */ - TIMER2A_IRQn = 23, /**< 16/32-Bit Timer 2A */ - TIMER2B_IRQn = 24, /**< 16/32-Bit Timer 2B */ - ACOMP0_IRQn = 25, /**< Analog Comparator 0 */ - ACOMP1_IRQn = 26, /**< Analog Comparator 1 */ - SYSCON_IRQn = 28, /**< System Control */ - FMCEECON_IRQn = 29, /**< Flash Memory Control and EEPROM Control */ - GPIOF_IRQn = 30, /**< GPIO Port F */ - UART2_IRQn = 33, /**< UART2 */ - SSI1_IRQn = 34, /**< SSI1 */ - TIMER3A_IRQn = 35, /**< 16/32-Bit Timer 3A */ - TIMER3B_IRQn = 36, /**< 16/32-Bit Timer 3B */ - I2C1_IRQn = 37, /**< I2C1 */ - QEI1_IRQn = 38, /**< QEI1 */ - CAN0_IRQn = 39, /**< CAN0 */ - CAN1_IRQn = 40, /**< CAN1 */ - HIBMODULE_IRQn = 43, /**< Hibernation Module */ - USB_IRQn = 44, /**< USB */ - PWM0GEN3_IRQn = 45, /**< PWM0 Generator 3 */ - UDMASFW_IRQn = 46, /**< UDMA Software */ - UDMAERR_IRQn = 47, /**< UDMA Error */ - ADC1SEQ0_IRQn = 48, /**< ADC1 Sequence 0 */ - ADC1SEQ1_IRQn = 49, /**< ADC1 Sequence 1 */ - ADC1SEQ2_IRQn = 50, /**< ADC1 Sequence 2 */ - ADC1SEQ3_IRQn = 51, /**< ADC1 Sequence 3 */ - SSI2_IRQn = 57, /**< SSI2 */ - SSI3_IRQn = 58, /**< SSI3 */ - UART3_IRQn = 59, /**< UART3 */ - UART4_IRQn = 60, /**< UART4 */ - UART5_IRQn = 61, /**< UART5 */ - UART6_IRQn = 62, /**< UART6 */ - UART7_IRQn = 63, /**< UART7 */ - I2C2_IRQn = 68, /**< I2C2 */ - I2C3_IRQn = 69, /**< I2C3 */ - TIMER4A_IRQn = 70, /**< 16/32-Bit Timer 4A */ - TIMER4B_IRQn = 71, /**< 16/32-Bit Timer 4B */ - TIMER5A_IRQn = 92, /**< 16/32-Bit Timer 5A */ - TIMER5B_IRQn = 93, /**< 16/32-Bit Timer 5B */ - WTIMER0A_IRQn = 94, /**< 32/64-Bit Timer 0A */ - WTIMER0B_IRQn = 95, /**< 32/64-Bit Timer 0B */ - WTIMER1A_IRQn = 96, /**< 32/64-Bit Timer 1A */ - WTIMER1B_IRQn = 97, /**< 32/64-Bit Timer 1B */ - WTIMER2A_IRQn = 98, /**< 32/64-Bit Timer 2A */ - WTIMER2B_IRQn = 99, /**< 32/64-Bit Timer 2B */ - WTIMER3A_IRQn = 100, /**< 32/64-Bit Timer 3A */ - WTIMER3B_IRQn = 101, /**< 32/64-Bit Timer 3B */ - WTIMER4A_IRQn = 102, /**< 32/64-Bit Timer 4A */ - WTIMER4B_IRQn = 103, /**< 32/64-Bit Timer 4B */ - WTIMER5A_IRQn = 104, /**< 32/64-Bit Timer 5A */ - WTIMER5B_IRQn = 105, /**< 32/64-Bit Timer 5B */ - SYSEXCEPT_IRQn = 106, /**< System Exception (imprecise) */ - PWM1GEN0_IRQn = 134, /**< PWM1 Generator 0 */ - PWM1GEN1_IRQn = 135, /**< PWM1 Generator 1 */ - PWM1GEN2_IRQn = 136, /**< PWM1 Generator 2 */ - PWM1GEN3_IRQn = 137, /**< PWM1 Generator 3 */ - PWM1FAULT_IRQn = 138 /**< PWM1 Fault */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals.*/ -#include <stdint.h> - -/** - * @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog Comparator - */ -typedef struct -{ - __IO uint32_t MIS; /**< Masked Interrupt Status */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t REFCTL; /**< Reference Voltage Control */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __I uint32_t STAT0; /**< Status 0 */ - __IO uint32_t CTL0; /**< Control 0 */ - __I uint32_t _RESERVED2[6]; /**< Reserved */ - __I uint32_t STAT1; /**< Status 1 */ - __IO uint32_t CTL1; /**< Control 1 */ - __I uint32_t _RESERVED3[990];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} ACMP_TypeDef; - -/** - * @brief Analog-to-Digital Converter - */ -typedef struct -{ - __IO uint32_t MUX; /**< Sample Sequence Input Multiplexer - Select */ - __IO uint32_t CTL; /**< Sample Sequence Control */ - __I uint32_t FIFO; /**< Sample Sequence Result FIFO */ - __I uint32_t FSTAT; /**< Sample Sequence FIFO Status */ - __IO uint32_t OP; /**< Sample Sequence Operation */ - __IO uint32_t DC; /**< Sample Sequence Digital Comparator - Select */ - __I uint32_t _RESERVED0[2]; /**< Reserved */ -} ADC_SS_t; - -typedef struct -{ - __IO uint32_t ACTSS; /**< Active Sample Sequencer */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t IM; /**< Interrupt Mask */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __IO uint32_t OSTAT; /**< Overflow Status */ - __IO uint32_t EMUX; /**< Event Multiplexer Select */ - __IO uint32_t USTAT; /**< Underflow Status */ - __IO uint32_t TSSEL; /**< Trigger Source Select */ - __IO uint32_t SSPRI; /**< Sample Sequencer Priority */ - __IO uint32_t SPC; /**< Sample Phase Control */ - __IO uint32_t PSSI; /**< Processor Sample Sequence Initiate */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t SAC; /**< Sample Averaging Control */ - __IO uint32_t DCISC; /**< Digital Comparator Interrupt Status and - Clear */ - __IO uint32_t CTL; /**< Control */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - ADC_SS_t SS[4]; /**< Sample Sequence 0, 1, 2 and 3 */ - __I uint32_t _RESERVED2[784];/**< Reserved */ - __O uint32_t DCRIC; /**< Digital Comparator Reset Initial - Conditions */ - __I uint32_t _RESERVED3[63]; /**< Reserved */ - __IO uint32_t DCCTL[8]; /**< Digital Comparator Control 0 - 7 */ - __I uint32_t _RESERVED4[8]; /**< Reserved */ - __IO uint32_t DCCMP[8]; /**< Digital Comparator Range 0 - 7 */ - __I uint32_t _RESERVED5[88]; /**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __IO uint32_t PC; /**< Peripheral Configuration */ - __IO uint32_t CC; /**< Clock Configuration */ -} ADC_TypeDef; - -/** - * @brief Controller Area Network - */ -typedef struct -{ - __IO uint32_t CRQ; /**< Command Request */ - __IO uint32_t CMSK; /**< Command Mask */ - __IO uint32_t MSK[2]; /**< Mask 1 and 2 */ - __IO uint32_t ARB[2]; /**< Arbitration 1 and 2 */ - __IO uint32_t MCTL; /**< Message Control */ - __IO uint32_t DA[2]; /**< Data A1 and A2 */ - __IO uint32_t DB[2]; /**< Data B1 and B2 */ - __I uint32_t _RESERVED0[13]; /**< Reserved */ -} CAN_INTERFACE_t; - -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t STS; /**< Status */ - __I uint32_t ERR; /**< Error Counter */ - __IO uint32_t BIT; /**< Bit Timing */ - __I uint32_t INT; /**< Interrupt */ - __IO uint32_t TST; /**< Test */ - __IO uint32_t BRPE; /**< Baud Rate Prescaler Extension */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - CAN_INTERFACE_t IF[2]; /**< IF1 and IF2 */ - __I uint32_t _RESERVED1[8]; /**< Reserved */ - __I uint32_t TXRQ[2]; /**< Transmission Request 1 and 2 */ - __I uint32_t _RESERVED2[6]; /**< Reserved */ - __I uint32_t NWDA[2]; /**< New Data 1 and 2 */ - __I uint32_t _RESERVED3[6]; /**< Reserved */ - __I uint32_t MSGINT[2]; /**< Message 1 and 2 Interrupt Pending */ - __I uint32_t _RESERVED4[6]; /**< Reserved */ - __I uint32_t MSGVAL[2]; /**< Message 1 and 2 Valid */ -} CAN_TypeDef; - -/** - * @brief EEPROM Memory - */ -typedef struct -{ - __IO uint32_t EESIZE; /**< Size Information */ - __IO uint32_t EEBLOCK; /**< Current Block */ - __IO uint32_t EEOFFSET; /**< Current Offset */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t EERDWR; /**< Read-Write */ - __IO uint32_t EERDWRINC; /**< Read-Write with Increment */ - __IO uint32_t EEDONE; /**< Done Status */ - __IO uint32_t EESUPP; /**< Support Control and Status */ - __IO uint32_t EEUNLOCK; /**< Unlock */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __IO uint32_t EEPROT; /**< Protection */ - __IO uint32_t EEPASS[3]; /**< Password */ - __IO uint32_t EEINT; /**< Interrupt */ - __I uint32_t _RESERVED2[3]; /**< Reserved */ - __IO uint32_t EEHIDE; /**< Block Hide */ - __I uint32_t _RESERVED3[11]; /**< Reserved */ - __IO uint32_t EEDBGME; /**< Debug Mass Erase */ - __I uint32_t _RESERVED4[975];/**< Reserved */ - __IO uint32_t EEPROMPP; /**< Peripheral Properties */ -} EEPROM_TypeDef; - -/** - * @brief Flash Memory - */ -typedef struct -{ - __IO uint32_t FMA; /**< Flash Memory Address */ - __IO uint32_t FMD; /**< Flash Memory Data */ - __IO uint32_t FMC; /**< Flash Memory Control */ - __I uint32_t FCRIS; /**< Flash Controller Raw Interrupt Status */ - __IO uint32_t FCIM; /**< Flash Controller Interrupt Mask */ - __IO uint32_t FCMISC; /**< Masked Interrupt Status and Clear */ - __I uint32_t _RESERVED0[2]; /**< Reserved */ - __IO uint32_t FMC2; /**< Flash Memory Control 2 */ - __I uint32_t _RESERVED1[3]; /**< Reserved */ - __IO uint32_t FWBVAL; /**< Flash Write Buffer Valid */ - __I uint32_t _RESERVED2[51]; /**< Reserved */ - __IO uint32_t FWBN; /**< Flash Write Buffer n */ - __I uint32_t _RESERVED3[943];/**< Reserved */ - __I uint32_t FSIZE; /**< Flash Size */ - __I uint32_t SSIZE; /**< SRAM Size */ - __I uint32_t _RESERVED4[1]; /**< Reserved */ - __IO uint32_t ROMSWMAP; /**< ROM Software Map */ -} FLASH_TypeDef; - - - -/** - * @brief General Purpose Input/Outputs - */ -typedef struct -{ - union { - __IO uint32_t MASKED_ACCESS[256]; /**< Masked access of Data Register */ - struct { - __I uint32_t _RESERVED0[255]; /**< Reserved */ - __IO uint32_t DATA; /**< Data */ - }; - }; - __IO uint32_t DIR; /**< Direction */ - __IO uint32_t IS; /**< Interrupt Sense */ - __IO uint32_t IBE; /**< Interrupt Both Edges */ - __IO uint32_t IEV; /**< Interrupt Event */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t AFSEL; /**< Alternate Function Select */ - __I uint32_t _RESERVED1[55]; /**< Reserved */ - __IO uint32_t DR2R; /**< 2-mA Drive Select */ - __IO uint32_t DR4R; /**< 4-mA Drive Select */ - __IO uint32_t DR8R; /**< 8-mA Drive Select */ - __IO uint32_t ODR; /**< Open Drain Select */ - __IO uint32_t PUR; /**< Pull-Up Select */ - __IO uint32_t PDR; /**< Pull-Down Select */ - __IO uint32_t SLR; /**< Slew Rate Control Select */ - __IO uint32_t DEN; /**< Digital Enable */ - __IO uint32_t LOCK; /**< Lock */ - __IO uint32_t CR; /**< Commit */ - __IO uint32_t AMSEL; /**< Analog Mode Select */ - __IO uint32_t PCTL; /**< Port Control */ - __IO uint32_t ADCCTL; /**< ADC Control */ - __IO uint32_t DMACTL; /**< DMA Control */ - __IO uint32_t SI; /**< */ - __IO uint32_t DR12R; /**< */ - __IO uint32_t WAKEPEN; /**< */ - __IO uint32_t WAKELVL; /**< */ - __IO uint32_t WAKESTAT; /**< */ - __I uint32_t _RESERVED2[669];/**< */ - __I uint32_t PP; /**< */ - __IO uint32_t PC; /**< */ -} GPIO_TypeDef; - -/** - * @brief General Purpose Timer - */ -typedef struct -{ - __IO uint32_t CFG; /**< Configuration */ - __IO uint32_t TAMR; /**< Timer A Mode */ - __IO uint32_t TBMR; /**< Timer B Mode */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t SYNC; /**< Synchronize */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t IMR; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t TAILR; /**< Timer A Interval Load */ - __IO uint32_t TBILR; /**< Timer B Interval Load */ - __IO uint32_t TAMATCHR; /**< Timer A Match */ - __IO uint32_t TBMATCHR; /**< Timer B Match */ - __IO uint32_t TAPR; /**< Timer A Prescale */ - __IO uint32_t TBPR; /**< Timer B Prescale */ - __IO uint32_t TAPMR; /**< Timer A Prescale Match */ - __IO uint32_t TBPMR; /**< Timer B Prescale Match */ - __I uint32_t TAR; /**< Timer A */ - __I uint32_t TBR; /**< Timer B */ - __IO uint32_t TAV; /**< Timer A Value */ - __IO uint32_t TBV; /**< Timer B Value */ - __I uint32_t RTCPD; /**< RTC Predivide */ - __I uint32_t TAPS; /**< Timer A Prescale Snapshot */ - __I uint32_t TBPS; /**< Timer B Prescale Snapshot */ - __I uint32_t TAPV; /**< Timer A Prescale Value */ - __I uint32_t TBPV; /**< Timer B Prescale Value */ - __I uint32_t _RESERVED1[981];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} GPT_TypeDef; - -/** - * @brief Hibernation Module - */ -typedef struct -{ - __I uint32_t RTCC; /**< RTC Counter */ - __IO uint32_t RTCM0; /**< RTC Match 0 */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __IO uint32_t RTCLD; /**< RTC Load */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __IO uint32_t IC; /**< Interrupt Clear */ - __IO uint32_t RTCT; /**< RTC Trim */ - __IO uint32_t RTCSS; /**< RTC Sub Seconds */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - __IO uint32_t DATA; /**< Data */ -} HIB_TypeDef; - -/** - * @brief Inter-Integrated Circuit - */ -typedef struct -{ - __IO uint32_t MSA; /**< Master Slave Address */ - __IO uint32_t MCS; /**< Master Control/Status */ - __IO uint32_t MDR; /**< Master Data */ - __IO uint32_t MTPR; /**< Master Timer Period */ - __IO uint32_t MIMR; /**< Master Interrupt Mask */ - __I uint32_t MRIS; /**< Master Raw Interrupt Status */ - __IO uint32_t MMIS; /**< Master Masked Interrupt Status */ - __O uint32_t MICR; /**< Master Interrupt Clear */ - __IO uint32_t MCR; /**< Master Configuration */ - __IO uint32_t MCLKOCNT; /**< Master Clock Low Timeout Count */ - __I uint32_t _RESERVED0[1]; /**< Reserved */ - __I uint32_t MBMON; /**< Master Bus Monitor */ - __IO uint32_t MCR2; /**< Master Configuration 2 */ - __I uint32_t _RESERVED1[497];/**< Reserved */ - __IO uint32_t SOAR; /**< Slave Own Address */ - __IO uint32_t SCSR; /**< Slave Control/Status */ - __IO uint32_t SDR; /**< Slave Data */ - __IO uint32_t SIMR; /**< Slave Interrupt Mask */ - __I uint32_t SRIS; /**< Slave Raw Interrupt Status */ - __I uint32_t SMIS; /**< Slave Masked Interrupt Status */ - __O uint32_t SICR; /**< Slave Interrupt Clear */ - __IO uint32_t SOAR2; /**< Slave Own Address 2 */ - __IO uint32_t SACKCTL; /**< Slave ACK Control */ - __I uint32_t _RESERVED2[487];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __I uint32_t PC; /**< Peripheral Configuration */ -} I2C_TypeDef; - -/* - * @brief Pulse Width Modulator - */ -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t INTEN; /**< Interrupt and Trigger Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __IO uint32_t LOAD; /**< Load */ - __I uint32_t COUNT; /**< Counter */ - __IO uint32_t CMP[2]; /**< Compare A, B */ - __IO uint32_t GEN[2]; /**< Generator A, B Control */ - __IO uint32_t DBCTL; /**< Dead-Band Control */ - __IO uint32_t DBRISE; /**< Dead-Band Rising-Edge Delay */ - __IO uint32_t DBFALL; /**< Dead-Band Falling-Edge Delay */ - __IO uint32_t FLTSRC[2]; /**< Fault Source 0, 1 */ - __IO uint32_t MINFLTPER; /**< Minimum Fault Period */ -} PWM_GENERATOR_T; - -typedef struct -{ - union { - __IO uint32_t SEN; /**< Fault Pin Logic Sense, for GEN 0 and 1 */ - __I uint32_t _RESERVED0[1];/**< Reserved, for GEN 2 and 3 */ - }; - __IO uint32_t STAT[2]; /**< Fault Status */ - __I uint32_t _RESERVED1[29]; /**< Reserved */ -} PWM_FLT_t; - -typedef struct -{ - __IO uint32_t CTL; /**< Master Control */ - __IO uint32_t SYNC; /**< Time Base Sync */ - __IO uint32_t ENABLE; /**< Output Enable */ - __IO uint32_t INVERT; /**< Output Inversion */ - __IO uint32_t FAULT; /**< Output Fault */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ - __I uint32_t STATUS; /**< Status */ - __IO uint32_t FAULTVAL; /**< Fault Condition Value */ - __IO uint32_t ENUPD; /**< Enable Update */ - __I uint32_t _RESERVED0[5]; /**< Reserved */ - __IO PWM_GENERATOR_T PWM[4]; /**< PWM Generator 0, 1, 2 and 3 */ - __I uint32_t _RESERVED1[432];/**< Reserved */ - PWM_FLT_t FLT[4]; /**< Fault registers 0, 1, 2 and 3 */ - __I uint32_t _RESERVED2[368];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ -} PWM_TypeDef; - -/** - * @brief Quadrature Encoder Interface - */ -typedef struct -{ - __IO uint32_t CTL; /**< Control */ - __I uint32_t STAT; /**< Status */ - __IO uint32_t POS; /**< Position */ - __IO uint32_t MAXPOS; /**< Maximum Position */ - __IO uint32_t LOAD; /**< Timer Load */ - __I uint32_t TIME; /**< Timer */ - __I uint32_t COUNT; /**< Velocity Counter */ - __I uint32_t SPEED; /**< Velocity */ - __IO uint32_t INTEN; /**< Interrupt Enable */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t ISC; /**< Interrupt Status and Clear */ -} QEI_TypeDef; - -/** - * @brief Synchronous Serial Interface - */ -typedef struct -{ - __IO uint32_t CR[2]; /**< Control 0, 1 */ - __IO uint32_t DR; /**< Data */ - __I uint32_t SR; /**< Status */ - __IO uint32_t CPSR; /**< Clock Prescale */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t DMACTL; /**< DMA Control */ - __I uint32_t _RESERVED0[1000];/**< Reserved */ - __IO uint32_t CC; /**< Clock Configuration */ -} SSI_TypeDef; - -/** - * @brief System Control - */ -typedef struct -{ - __I uint32_t DID0; /**< Device Identification 0 */ - __I uint32_t DID1; /**< Device Identification 1 */ - __I uint32_t RESERVED0[12]; /**< Reserved */ - __IO uint32_t PBORCTL; /**< Power-Temp Brown Out Control */ - __I uint32_t RESERVED1[5]; /**< Reserved */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t IMC; /**< Interrupt Mask Control */ - __IO uint32_t MISC; /**< Interrupt Status and Clear */ - __IO uint32_t RESC; /**< Reset Cause */ - __IO uint32_t PWRTC; /**< Power-Temperature Cause */ - __IO uint32_t NMIC; /**< NMI Cause Register */ - __I uint32_t RESERVED2[5]; /**< Reserved */ - __IO uint32_t MOSCCTL; /**< Main Oscillator Control */ - __I uint32_t RESERVED3[12]; /**< Reserved */ - __IO uint32_t RSCLKCFG; /**< Run and Sleep Mode Configuration Register */ - __I uint32_t RESERVEDx[3]; - __IO uint32_t MEMTIM0; /**< Memory Timing Parameter Register 0 for Main Flash and EEPROM */ - __I uint32_t RESERVED4[29]; /**< Reserved */ - __IO uint32_t ALTCLKCFG; /**< Alternate Clock Configuration */ - __I uint32_t RESERVED5[2]; /**< Reserved */ - __IO uint32_t DSLPCLKCFG; /**< Deep Sleep Clock Configuration */ - __IO uint32_t DIVSCLK; /**< Divisor and Source Clock Configuration */ - __I uint32_t SYSPROP; /**< System Properties */ - __IO uint32_t PIOSCCAL; /**< PIOSC Calibration */ - __I uint32_t PIOSCSTAT; /**< PIOSC Statistics */ - __I uint32_t RESERVED6[2]; /**< Reserved */ - __IO uint32_t PLLFREQ0; /**< PLL Frequency 0 */ - __IO uint32_t PLLFREQ1; /**< PLL Frequency 1 */ - __I uint32_t PLLSTAT; /**< PLL Frequency Status */ - __I uint32_t RESERVED7[7]; /**< Reserved */ - __IO uint32_t SLPPWRCFG; /**< Sleep Power Configuration */ - __IO uint32_t DSLPPWRCFG; /**< Deep-Sleep Power Configuration */ - __I uint32_t RESERVED8[4]; /**< Reserved */ - __I uint32_t NVMSTAT; /**< Non-Volatile Memory Information */ - __I uint32_t RESERVED9[4]; /**< Reserved */ - __IO uint32_t LDOSPCTL; /**< LDO Sleep Power Control */ - __I uint32_t LDOSPCAL; /**< LDO Sleep Power Calibration */ - __IO uint32_t LDODPCTL; /**< LDO Deep-Sleep Power Control */ - __I uint32_t LDODPCAL; /**< LDO Deep-Sleep Power Calibration */ - __I uint32_t RESERVED10[2]; /**< Reserved */ - __I uint32_t SDPMST; /**< Sleep/Deep-Sleep Power Mode Status */ - __I uint32_t RESERVED11[2]; /**< Reserved */ - __IO uint32_t RESBEHAVCTL; /**< Reset Behavior Control Register */ - __I uint32_t RESERVED12[6]; /**< Reserved */ - __IO uint32_t HSSR; /**< Hardware System Service Request */ - __I uint32_t RESERVED[34]; /**< Reserved */ - __I uint32_t USBPDS; /**< USB Power Domain Status */ - __IO uint32_t USBMPC; /**< USB Memory Power Control */ - __I uint32_t EMACPDS; /**< Ethernet MAC Power Domain Status */ - __IO uint32_t EMACMPC; /**< Ethernet MAC Memory Power Control */ - __I uint32_t RESERVED13[2]; /**< Reserved */ - __I uint32_t CAN0PDS; /**< CAN 0 Power Domain Status */ - __IO uint32_t CAN0MPC; /**< CAN 0 Memory Power Control */ - __I uint32_t CAN1PDS; /**< CAN 1 Power Domain Status */ - __IO uint32_t CAN1MPC; /**< CAN 1 Memory Power Control */ - __I uint32_t RESERVED14[22]; /**< Reserved */ - __I uint32_t PPWD; /**< WDT Peripheral Present */ - __I uint32_t PPTIMER; /**< GPT Peripheral Present */ - __I uint32_t PPGPIO; /**< GPIO Peripheral Present */ - __I uint32_t PPDMA; /**< UDMA Peripheral Present */ - __I uint32_t PPEPI; /**< EPI Peripheral Present */ - __I uint32_t PPHIB; /**< HIB Peripheral Present */ - __I uint32_t PPUART; /**< UART Peripheral Present */ - __I uint32_t PPSSI; /**< SSI Peripheral Present */ - __I uint32_t PPI2C; /**< I2C Peripheral Present */ - __I uint32_t RESERVED15[1]; /**< Reserved */ - __I uint32_t PPUSB; /**< USB Peripheral Present */ - __I uint32_t RESERVED16[1]; /**< Reserved */ - __I uint32_t PPEPHY; /**< Ethernet PHY Peripheral Present */ - __I uint32_t PPCAN; /**< CAN Peripheral Present */ - __I uint32_t PPADC; /**< ADC Peripheral Present */ - __I uint32_t PPACMP; /**< ACMP Peripheral Present */ - __I uint32_t PPPWM; /**< PWM Peripheral Present */ - __I uint32_t PPQEI; /**< QEI Peripheral Present */ - __I uint32_t PPLPC; /**< Low Pin Count Interface Peripheral Present */ - __I uint32_t RESERVED17[1]; /**< Reserved */ - __I uint32_t PPPECI; /**< Platform Environment Control Interface Peripheral Present */ - __I uint32_t PPFAN; /**< Fan Control Peripheral Present */ - __I uint32_t PPEEPROM; /**< EEPROM Peripheral Present */ - __I uint32_t PPWTIMER; /**< Wide GPT Peripheral Present */ - __I uint32_t RESERVED18[4]; /**< Reserved */ - __I uint32_t PPRTS; /**< Remote Temperature Sensor Peripheral Present */ - __I uint32_t PPCCM; /**< CRC Module Peripheral Present */ - __I uint32_t RESERVED19[6]; /**< Reserved */ - __I uint32_t PPLCD; /**< LCD Peripheral Present */ - __I uint32_t RESERVED20[1]; /**< Reserved */ - __I uint32_t PPOWIRE; /**< 1-Wire Peripheral Present */ - __I uint32_t PPEMAC; /**< Ethernet MAC Peripheral Present */ - __I uint32_t PPPRB; /**< Power Regulator Bus Peripheral Present */ - __I uint32_t PPHIM; /**< Human Interface Master Peripheral Present */ - __I uint32_t RESERVED21[86]; /**< Reserved */ - __IO uint32_t SRWD; /**< WDT Software Reset */ - __IO uint32_t SRTIMER; /**< GPT Software Reset */ - __IO uint32_t SRGPIO; /**< GPIO Software Reset */ - __IO uint32_t SRDMA; /**< UDMA Software Reset */ - __IO uint32_t SREPI; /**< EPI Software Reset */ - __IO uint32_t SRHIB; /**< HIB Software Reset */ - __IO uint32_t SRUART; /**< UART Software Reset */ - __IO uint32_t SRSSI; /**< SSI Software Reset */ - __IO uint32_t SRI2C; /**< I2C Software Reset */ - __I uint32_t RESERVED22[1]; /**< Reserved */ - __IO uint32_t SRUSB; /**< USB Software Reset */ - __I uint32_t RESERVED23[1]; /**< Reserved */ - __IO uint32_t SREPHY; /**< Ethernet PHY Software Reset */ - __IO uint32_t SRCAN; /**< CAN Software Reset */ - __IO uint32_t SRADC; /**< ADC Software Reset */ - __IO uint32_t SRACMP; /**< ACMP Software Reset */ - __IO uint32_t SRPWM; /**< PWM Software Reset */ - __IO uint32_t SRQEI; /**< QEI Software Reset */ - __I uint32_t RESERVED24[4]; /**< Reserved */ - __IO uint32_t SREEPROM; /**< EEPROM Software Reset */ - __I uint32_t RESERVED25[6]; /**< Reserved */ - __IO uint32_t SRCCM; /**< CRC Module Software Reset */ - __I uint32_t RESERVED26[9]; /**< Reserved */ - __IO uint32_t SREMAC; /**< Ethernet MAC Software Reset */ - __I uint32_t RESERVED27[24]; /**< Reserved */ - __IO uint32_t RCGCWD; /**< WDT Run Mode Clock Gating Control */ - __IO uint32_t RCGCTIMER; /**< GPT Run Mode Clock Gating Control */ - __IO uint32_t RCGCGPIO; /**< GPIO Run Mode Clock Gating Control */ - __IO uint32_t RCGCDMA; /**< UDMA Run Mode Clock Gating Control */ - __IO uint32_t RCGCEPI; /**< EPI Run Mode Clock Gating Control */ - __IO uint32_t RCGCHIB; /**< HIB Run Mode Clock Gating Control */ - __IO uint32_t RCGCUART; /**< UART Run Mode Control */ - __IO uint32_t RCGCSSI; /**< SSI Run Mode Clock Gating Control */ - __IO uint32_t RCGCI2C; /**< I2C Run Mode Clock Gating Control */ - __I uint32_t RESERVED28[1]; /**< Reserved */ - __IO uint32_t RCGCUSB; /**< USB Run Mode Clock Gating Control */ - __I uint32_t RESERVED29[1]; /**< Reserved */ - __IO uint32_t RCGCEPHY; /**< Ethernet PHY Run Mode Clock Gating Control */ - __IO uint32_t RCGCCAN; /**< CAN Run Mode Clock Gating Control */ - __IO uint32_t RCGCADC; /**< ADC Run Mode Clock Gating Control */ - __IO uint32_t RCGCACMP; /**< ACMP Run Mode Clock Gating Control */ - __IO uint32_t RCGCPWM; /**< PWM Run Mode Clock Gating Control */ - __IO uint32_t RCGCQEI; /**< QEI Run Mode Clock Gating Control */ - __I uint32_t RESERVED30[4]; /**< Reserved */ - __IO uint32_t RCGCEEPROM; /**< EEPROM Run Mode Clock Gating Control */ - __I uint32_t RESERVED31[6]; /**< Reserved */ - __IO uint32_t RCGCCCM; /**< CRC Module Run Mode Clock Gating Control */ - __I uint32_t RESERVED32[9]; /**< Reserved */ - __IO uint32_t RCGCEMAC; /**< Ethernet MAC Run Mode Clock Gating Control */ - __I uint32_t RESERVED33[24]; /**< Reserved */ - __IO uint32_t SCGCWD; /**< WDT Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCTIMER; /**< GPT Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCGPIO; /**< GPIO Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCDMA; /**< UDMA Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCEPI; /**< EPI Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCHIB; /**< HIB Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCUART; /**< UART Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCSSI; /**< SSI Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCI2C; /**< I2C Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED34[1]; /**< Reserved */ - __IO uint32_t SCGCUSB; /**< USB Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED35[1]; /**< Reserved */ - __IO uint32_t SCGCEPHY; /**< Ethernet PHY Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCCAN; /**< CAN Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCADC; /**< ADC Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCACMP; /**< ACMP Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCPWM; /**< PWM Sleep Mode Clock Gating Control */ - __IO uint32_t SCGCQEI; /**< QEI Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED36[4]; /**< Reserved */ - __IO uint32_t SCGCEEPROM; /**< EEPROM Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED37[6]; /**< Reserved */ - __IO uint32_t SCGCCCM; /**< CRC Module Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED38[9]; /**< Reserved */ - __IO uint32_t SCGCEMAC; /**< Ethernet MAC Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED39[24]; /**< Reserved */ - __IO uint32_t DCGCWD; /**< WDT Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCTIMER; /**< GPT Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCGPIO; /**< GPIO Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCDMA; /**< UDMA Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCEPI; /**< EPI Deep-Sleep Mode Clock Gating Control */ - __IO uint32_t DCGCHIB; /**< HIB Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCUART; /**< UART Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCSSI; /**< SSI Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCI2C; /**< I2C Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED40[1]; /**< Reserved */ - __IO uint32_t DCGCUSB; /**< USB Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED41[1]; /**< Reserved */ - __IO uint32_t DCGCEPHY; /**< Ethernet PHY Deep-Sleep Mode Clock Gating Control */ - __IO uint32_t DCGCCAN; /**< CAN Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCADC; /**< ADC Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCACMP; /**< ACMP Deep-Sleep Mode Clock Gating - Control */ - __IO uint32_t DCGCPWM; /**< PWM Deep-Sleep Mode Clock Gating Control*/ - __IO uint32_t DCGCQEI; /**< QEI Deep-Sleep Mode Clock Gating Control*/ - __I uint32_t RESERVED42[4]; /**< Reserved */ - __IO uint32_t DCGCEEPROM; /**< EEPROM Deep-Sleep Mode Clock Gating - Control */ - __I uint32_t RESERVED43[6]; /**< Reserved */ - __IO uint32_t DCGCCCM; /**< CRC Module Deep-Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED44[9]; /**< Reserved */ - __IO uint32_t DCGCEMAC; /**< Ethernet MAC Deep-Sleep Mode Clock Gating Control */ - __I uint32_t RESERVED45[24]; /**< Reserved */ - __IO uint32_t PCWD; /**< Watchdog Timer Power Control */ - __IO uint32_t PCTIMER; /**< 16/32-Bit General-Purpose Timer Power Control */ - __IO uint32_t PCGPIO; /**< General-Purpose Input/Output Power Control */ - __IO uint32_t PCDMA; /**< Micro Direct Memory Access Power Control */ - __IO uint32_t PCEPI; /**< External Peripheral Interface Power Control */ - __IO uint32_t PCHIB; /**< Hibernation Power Control */ - __IO uint32_t PCUART; /**< Universal Asynchronous Receiver/Transmitter Power Control */ - __IO uint32_t PCSSI; /**< Synchronous Serial Interface Power Control */ - __IO uint32_t PCI2C; /**< Inter-Integrated Circuit Power Control */ - __I uint32_t RESERVED46[1]; /**< Reserved */ - __IO uint32_t PCUSB; /**< Universal Serial Bus Power Control */ - __I uint32_t RESERVED47[1]; /**< Reserved */ - __IO uint32_t PCEPHY; /**< Ethernet PHY Power Control */ - __IO uint32_t PCCAN; /**< Controller Area Network Power Control */ - __IO uint32_t PCADC; /**< Analog-to-Digital Converter Power Control */ - __IO uint32_t PCACMP; /**< Analog Comparator Power Control */ - __IO uint32_t PCPWM; /**< Pulse Width Modulator Power Control */ - __IO uint32_t PCQEI; /**< Quadrature Encoder Interface Power Control */ - __I uint32_t RESERVED48[4]; /**< Reserved */ - __IO uint32_t PCEEPROM; /**< EEPROM Power Control */ - __I uint32_t RESERVED49[6]; /**< Reserved */ - __IO uint32_t PCCCM; /**< CRC Module Power Control */ - __I uint32_t RESERVED50[9]; /**< Reserved */ - __IO uint32_t PCEMAC; /**< Ethernet MAC Power Control */ - __I uint32_t RESERVED51[24]; /**< Reserved */ - __IO uint32_t PRWD; /**< WDT Peripheral Ready */ - __IO uint32_t PRTIMER; /**< GPT Peripheral Ready */ - __IO uint32_t PRGPIO; /**< GPIO Peripheral Ready */ - __IO uint32_t PRDMA; /**< UDMA Peripheral Ready */ - __IO uint32_t PREPI; /**< EPI Peripheral Ready */ - __IO uint32_t PRHIB; /**< HIB Peripheral Ready */ - __IO uint32_t PRUART; /**< UART Peripheral Ready */ - __IO uint32_t PRSSI; /**< SSI Peripheral Ready */ - __IO uint32_t PRI2C; /**< I2C Peripheral Ready */ - __I uint32_t RESERVED52[1]; /**< Reserved */ - __IO uint32_t PRUSB; /**< USB Peripheral Ready */ - __I uint32_t RESERVED53[1]; /**< Reserved */ - __IO uint32_t PREPHY; /**< Ethernet PHY Peripheral Ready */ - __IO uint32_t PRCAN; /**< CAN Peripheral Ready */ - __IO uint32_t PRADC; /**< ADC Peripheral Ready */ - __IO uint32_t PRACMP; /**< ACMP Peripheral Ready */ - __IO uint32_t PRPWM; /**< PWM Peripheral Ready */ - __IO uint32_t PRQEI; /**< QEI Peripheral Ready */ - __I uint32_t RESERVED54[4]; /**< Reserved */ - __IO uint32_t PREEPROM; /**< EEPROM Peripheral Ready */ - __I uint32_t RESERVED55[6]; /**< Reserved */ - __IO uint32_t PRCCM; /**< CRC Module Peripheral Ready */ - __I uint32_t RESERVED56[9]; /**< Reserved */ - __IO uint32_t PREMAC; /**< Ethernet MAC Peripheral Ready */ -} SYSCTL_TypeDef; - -/** - * @brief Universal Asynchronous Receiver/Transmitter - */ -typedef struct -{ - __IO uint32_t DR; /**< Data */ - union { - __I uint32_t RSR; /**< Receive Status */ - __O uint32_t ECR; /**< Error Clear */ - }; - __I uint32_t _RESERVED0[4]; /**< Reserved */ - __I uint32_t FR; /**< Flag */ - __I uint32_t _RESERVED1[1]; /**< Reserved */ - __IO uint32_t ILPR; /**< IrDA Low-Power Register */ - __IO uint32_t IBRD; /**< Integer Baud-Rate Divisor */ - __IO uint32_t FBRD; /**< Fractional Baud-Rate Divisor */ - __IO uint32_t LCRH; /**< Line Control */ - __IO uint32_t CTL; /**< Control */ - __IO uint32_t IFLS; /**< Interrupt FIFO Level Select */ - __IO uint32_t IM; /**< Interrupt Mask */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __O uint32_t ICR; /**< Interrupt Clear */ - __IO uint32_t DMACTL; /**< DMA Control */ - __I uint32_t _RESERVED2[22]; /**< Reserved */ - __IO uint32_t BIT9ADDR; /**< 9-Bit Self Address */ - __IO uint32_t BIT9AMASK; /**< 9-Bit Self Address Mask */ - __I uint32_t _RESERVED3[965];/**< Reserved */ - __I uint32_t PP; /**< Peripheral Properties */ - __I uint32_t _RESERVED4[1]; /**< Reserved */ - __IO uint32_t CC; /**< Clock Configuration */ -} UART_TypeDef; - -/** - * @brief Micro Direct Memory Access - */ -typedef struct -{ - __IO uint32_t SET; /**< Set */ - __O uint32_t CLR; /**< Clear */ -} UDMA_SC_t; - -typedef struct -{ - __IO uint32_t STAT; /**< Status */ - __O uint32_t CFG; /**< Configuration */ - __IO uint32_t CTLBASE; /**< Channel Control Base Pointer */ - __IO uint32_t ALTBASE; /**< Alternate Channel Control Base Pointer */ - __IO uint32_t WAITSTAT; /**< Channel Wait-on-Request Status */ - __O uint32_t SWREQ; /**< Channel Software Request */ - UDMA_SC_t USEBURST; /**< Channel Useburst registers */ - UDMA_SC_t REQMASK; /**< Channel Request Mask registers */ - UDMA_SC_t ENA; /**< Channel Enable registers */ - UDMA_SC_t ALT; /**< Channel Primary Alternate registers */ - UDMA_SC_t PRIO; /**< Channel Priority registers */ - __I uint32_t _RESERVED0[3]; /**< Reserved */ - __IO uint32_t ERRCLR; /**< Bus Error Clear */ - __I uint32_t _RESERVED1[300];/**< Reserved */ - __IO uint32_t CHASGN; /**< Channel Assignment */ - __IO uint32_t CHIS; /**< Channel Interrupt Status */ - __I uint32_t _RESERVED2[2]; /**< Reserved */ - __IO uint32_t CHMAP[4]; /**< Channel Map Select 0, 1, 2 and 3 */ -} UDMA_TypeDef; - -// USB - -/** - * @brief Watchdog Timer - */ -typedef struct -{ - __IO uint32_t LOAD; /**< Load */ - __I uint32_t VALUE; /**< Value */ - __IO uint32_t CTL; /**< Control */ - __O uint32_t ICR; /**< Interrupt Clear */ - __I uint32_t RIS; /**< Raw Interrupt Status */ - __I uint32_t MIS; /**< Masked Interrupt Status */ - __I uint32_t _RESERVED0[256];/**< Reserved */ - __IO uint32_t TEST; /**< Test */ - __I uint32_t _RESERVED1[505];/**< Reserved */ - __IO uint32_t LOCK; /**< Lock */ -} WDG_TypeDef; - -/** - * @brief Ethernet peripheral - */ -typedef struct { - __IO uint32_t CFG; /**< Configuration */ - __IO uint32_t FRAMEFLTR; /**< Frame Filter */ - __IO uint32_t HASHTBLH; /**< Hash Table High */ - __IO uint32_t HASHTBLL; /**< Hash Table Low */ - __IO uint32_t MIIADDR; /**< MII Address */ - __IO uint32_t MIIDATA; /**< MII Data Register */ - __IO uint32_t FLOWCTL; /**< Flow Control */ - __IO uint32_t VLANTG; /**< VLAN Tag */ - __I uint32_t RESERVED0[1]; /**< Reserved */ - __IO uint32_t STATUS; /**< Status */ - __IO uint32_t RWUFF; /**< Remote Wake-Up Frame Filter */ - __IO uint32_t PMTCTLSTAT; /**< PMT Control and Status Register */ - __I uint32_t RESERVED1[2]; /**< Reserved */ - __IO uint32_t RIS; /**< Raw Interrupt Status */ - __IO uint32_t IM; /**< Interrupt Mask */ - __IO uint32_t ADDR0H; /**< Address 0 High */ - __IO uint32_t ADDR0L; /**< Address 0 Low Register */ - __IO uint32_t ADDR1H; /**< Address 1 High */ - __IO uint32_t ADDR1L; /**< Address 1 Low */ - __IO uint32_t ADDR2H; /**< Address 2 High */ - __IO uint32_t ADDR2L; /**< Address 2 Low */ - __IO uint32_t ADDR3H; /**< Address 3 High */ - __IO uint32_t ADDR3L; /**< Address 3 Low */ - __I uint32_t RESERVED2[31]; /**< Reserved */ - __IO uint32_t WDOGTO; /**< Watchdog Timeout */ - __I uint32_t RESERVED3[8]; /**< Reserved */ - __IO uint32_t MMCCTRL; /**< MMC Control */ - __IO uint32_t MMCRXRIS; /**< MMC Receive Raw Interrupt Status */ - __IO uint32_t MMCTXRIS; /**< MMC Transmit Raw Interrupt Status */ - __IO uint32_t MMCRXIM; /**< MMC Receive Interrupt Mask */ - __IO uint32_t MMCTXIM; /**< MMC Transmit Interrupt Mask */ - __I uint32_t RESERVED4[1]; /**< Reserved */ - __IO uint32_t TXCNTGB; /**< Transmit Frame Count for Good and Bad - Frames */ - __I uint32_t RESERVED5[12]; /**< Reserved */ - __IO uint32_t TXCNTSCOL; /**< Transmit Frame Count for Frames - Transmitted after Single Collision */ - __IO uint32_t TXCNTMCOL; /**< Transmit Frame Count for Frames - Transmitted after Multiple Collisions */ - __I uint32_t RESERVED6[4]; /**< Reserved */ - __IO uint32_t TXOCTCNTG; /**< Transmit Octet Count Good */ - __I uint32_t RESERVED7[6]; /**< Reserved */ - __IO uint32_t RXCNTGB; /**< Receive Frame Count for Good and Bad - Frames */ - __I uint32_t RESERVED8[4]; /**< Reserved */ - __IO uint32_t RXCNTCRCERR; /**< Receive Frame Count for CRC Error Frames*/ - __IO uint32_t RXCNTALGNERR; /**< Receive Frame Count for Alignment Error - Frames */ - __I uint32_t RESERVED9[10]; /**< Reserved */ - __IO uint32_t RXCNTGUNI; /**< Receive Frame Count for Good Unicast - Frames */ - __I uint32_t RESERVED10[239];/**< Reserved */ - __IO uint32_t VLNINCREP; /**< VLAN Tag Inclusion or Replacement */ - __IO uint32_t VLANHASH; /**< VLAN Hash Table */ - __I uint32_t RESERVED11[93]; /**< Reserved */ - __IO uint32_t TIMSTCTRL; /**< Timestamp Control */ - __IO uint32_t SUBSECINC; /**< Sub-Second Increment */ - __IO uint32_t TIMSEC; /**< System Time - Seconds */ - __IO uint32_t TIMNANO; /**< System Time - Nanoseconds */ - __IO uint32_t TIMSECU; /**< System Time - Seconds Update */ - __IO uint32_t TIMNANOU; /**< System Time - Nanoseconds Update */ - __IO uint32_t TIMADD; /**< Timestamp Addend */ - __IO uint32_t TARGSEC; /**< Target Time Seconds */ - __IO uint32_t TARGNANO; /**< Target Time Nanoseconds */ - __IO uint32_t HWORDSEC; /**< System Time-Higher Word Seconds */ - __IO uint32_t TIMSTAT; /**< Timestamp Status */ - __IO uint32_t PPSCTRL; /**< PPS Control */ - __I uint32_t RESERVED12[12]; /**< Reserved */ - __IO uint32_t PPS0INTVL; /**< PPS0 Interval */ - __IO uint32_t PPS0WIDTH; /**< PPS0 Width */ - __I uint32_t RESERVED13[294];/**< Reserved */ - __IO uint32_t DMABUSMOD; /**< DMA Bus Mode */ - __O uint32_t TXPOLLD; /**< Transmit Poll Demand */ - __O uint32_t RXPOLLD; /**< Receive Poll Demand */ - __IO uint32_t RXDLADDR; /**< Receive Descriptor List Address */ - __IO uint32_t TXDLADDR; /**< Transmit Descriptor List Address */ - __IO uint32_t DMARIS; /**< DMA Interrupt Status */ - __IO uint32_t DMAOPMODE; /**< DMA Operation Mode */ - __IO uint32_t DMAIM; /**< DMA Interrupt Mask Register */ - __IO uint32_t MFBOC; /**< Missed Frame and Buffer Overflow Counter*/ - __IO uint32_t RXINTWDT; /**< Receive Interrupt Watchdog Timer */ - __I uint32_t RESERVED14[8]; /**< Reserved */ - __IO uint32_t HOSTXDESC; /**< Current Host Transmit Descriptor */ - __IO uint32_t HOSRXDESC; /**< Current Host Receive Descriptor */ - __IO uint32_t HOSTXBA; /**< Current Host Transmit Buffer Address */ - __IO uint32_t HOSRXBA; /**< Current Host Receive Buffer Address */ - __I uint32_t RESERVED15[218];/**< Reserved */ - __IO uint32_t PP; /**< Peripheral Property Register */ - __IO uint32_t PC; /**< Peripheral Configuration Register */ - __IO uint32_t CC; /**< Clock Configuration Register */ - __I uint32_t RESERVED16[1]; /**< Reserved */ - __I uint32_t PHYRIS; /**< PHY Raw Interrupt Status */ - __IO uint32_t PHYIM; /**< PHY Interrupt Mask */ - __IO uint32_t PHYMISC; /**< PHY Masked Interrupt Status and Clear */ -} ETH_TypeDef; - -/** - * @} - */ - -/** - * @addtogroup Peripheral_memorymap - * @{ - */ - -#define SYSCTL_BASE 0x400FE000 -#define HIB_BASE 0x400FC000 -#define FLASH_BASE 0x400FD000 -#define EEPROM_BASE 0x400AF000 -#define UDMA_BASE 0x400FF000 -#define GPIOA_BASE 0x40058000 -#define GPIOB_BASE 0x40059000 -#define GPIOC_BASE 0x4005A000 -#define GPIOD_BASE 0x4005B000 -#define GPIOE_BASE 0x4005C000 -#define GPIOF_BASE 0x4005D000 -#define GPIOG_BASE 0x4005E000 -#define GPIOH_BASE 0x4005F000 -#define GPIOJ_BASE 0x40060000 -#define GPIOK_BASE 0x40061000 -#define GPIOL_BASE 0x40062000 -#define GPIOM_BASE 0x40063000 -#define GPION_BASE 0x40064000 -#define GPIOP_BASE 0x40065000 -#define GPIOQ_BASE 0x40066000 -#define GPIOR_BASE 0x40067000 -#define GPIOS_BASE 0x40068000 -#define GPIOT_BASE 0x40069000 -#define GPT0_BASE 0x40030000 -#define GPT1_BASE 0x40031000 -#define GPT2_BASE 0x40032000 -#define GPT3_BASE 0x40033000 -#define GPT4_BASE 0x40034000 -#define GPT5_BASE 0x40035000 -#define GPT6_BASE 0x400E0000 -#define GPT7_BASE 0x400E1000 -#define WDT0_BASE 0x40000000 -#define WDT1_BASE 0x40001000 -#define ADC0_BASE 0x40038000 -#define ADC1_BASE 0x40039000 -#define UART0_BASE 0x4000C000 -#define UART1_BASE 0x4000D000 -#define UART2_BASE 0x4000E000 -#define UART3_BASE 0x4000F000 -#define UART4_BASE 0x40010000 -#define UART5_BASE 0x40011000 -#define UART6_BASE 0x40012000 -#define UART7_BASE 0x40013000 -#define SSI0_BASE 0x40008000 -#define SSI1_BASE 0x40009000 -#define SSI2_BASE 0x4000A000 -#define SSI3_BASE 0x4000B000 -#define I2C0_BASE 0x40020000 -#define I2C1_BASE 0x40021000 -#define I2C2_BASE 0x40022000 -#define I2C3_BASE 0x40023000 -#define I2C4_BASE 0x400C0000 -#define I2C5_BASE 0x400C1000 -#define I2C6_BASE 0x400C2000 -#define I2C7_BASE 0x400C3000 -#define I2C8_BASE 0x400B8000 -#define I2C9_BASE 0x400B9000 -#define CAN0_BASE 0x40040000 -#define CAN1_BASE 0x40041000 -// usb -#define ACMP_BASE 0x4003C000 -#define PWM0_BASE 0x40028000 -#define QEI0_BASE 0x4002C000 -#define QEI1_BASE 0x4002D000 - -#define ETH_BASE 0x400EC000 - -/** - * @} - */ - -/** - * @addtogroup Peripheral_declaration - * @{ - */ - -#define SYSCTL ((SYSCTL_TypeDef *) SYSCTL_BASE) -#define HIB ((HIB_TypeDef *) HIB_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_BASE) -#define EEPROM ((EEPROM_TypeDef *) EEPROM_BASE) -#define UDMA ((UDMA_TypeDef *) UDMA_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) -#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) -#define GPIOL ((GPIO_TypeDef *) GPIOL_BASE) -#define GPIOM ((GPIO_TypeDef *) GPIOM_BASE) -#define GPION ((GPIO_TypeDef *) GPION_BASE) -#define GPIOP ((GPIO_TypeDef *) GPIOP_BASE) -#define GPIOQ ((GPIO_TypeDef *) GPIOQ_BASE) -#define GPIOR ((GPIO_TypeDef *) GPIOR_BASE) -#define GPIOS ((GPIO_TypeDef *) GPIOS_BASE) -#define GPIOT ((GPIO_TypeDef *) GPIOT_BASE) -#define GPT0 ((GPT_TypeDef *) GPT0_BASE) -#define GPT1 ((GPT_TypeDef *) GPT1_BASE) -#define GPT2 ((GPT_TypeDef *) GPT2_BASE) -#define GPT3 ((GPT_TypeDef *) GPT3_BASE) -#define GPT4 ((GPT_TypeDef *) GPT4_BASE) -#define GPT5 ((GPT_TypeDef *) GPT5_BASE) -#define GPT6 ((GPT_TypeDef *) GPT6_BASE) -#define GPT7 ((GPT_TypeDef *) GPT7_BASE) -#define WDT0 ((WDT_TypeDef *) WDT0_BASE) -#define WDT1 ((WDT_TypeDef *) WDT1_BASE) -#define ADC0 ((ADC_TypeDef*) ADC0_BASE) -#define ADC1 ((ADC_TypeDef*) ADC1_BASE) -#define UART0 ((UART_TypeDef *) UART0_BASE) -#define UART1 ((UART_TypeDef *) UART1_BASE) -#define UART2 ((UART_TypeDef *) UART2_BASE) -#define UART3 ((UART_TypeDef *) UART3_BASE) -#define UART4 ((UART_TypeDef *) UART4_BASE) -#define UART5 ((UART_TypeDef *) UART5_BASE) -#define UART6 ((UART_TypeDef *) UART6_BASE) -#define UART7 ((UART_TypeDef *) UART7_BASE) -#define SSI0 ((SSI_TypeDef *) SSI0_BASE) -#define SSI1 ((SSI_TypeDef *) SSI1_BASE) -#define SSI2 ((SSI_TypeDef *) SSI2_BASE) -#define SSI3 ((SSI_TypeDef *) SSI3_BASE) -#define I2C0 ((I2C_TypeDef *) I2C0_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define I2C4 ((I2C_TypeDef *) I2C4_BASE) -#define I2C5 ((I2C_TypeDef *) I2C5_BASE) -#define I2C6 ((I2C_TypeDef *) I2C6_BASE) -#define I2C7 ((I2C_TypeDef *) I2C7_BASE) -#define I2C8 ((I2C_TypeDef *) I2C8_BASE) -#define I2C9 ((I2C_TypeDef *) I2C9_BASE) -#define CAN0 ((CAN_TypeDef *) CAN0_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -// usb -#define ACMP ((ACMP_TypeDef *) ACMP_BASE) -#define PWM0 ((PWM_TypeDef *) PWM0_BASE) -#define QEI0 ((QEI_TypeDef *) QEI0_BASE) -#define QEI1 ((QEI_TypeDef *) QEI1_BASE) - -#define ETH ((ETH_TypeDef *) ETH_BASE) - -/** - * @} - */ - -#endif /* __TM4C129x_H */ - -/** - * @} - */ - -/** - * @} - */ |