fish

5 files changed, 71 insertions, 105 deletions

diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v
deleted file mode 100644
index bfd69c3..0000000
--- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v
+++ /dev/null
@@ -1,44 +0,0 @@
-// async_8bit_bus_adapter.v
-
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
-// to your version control system if you want to keep it.
-
-`timescale 1 ps / 1 ps
-module async_8bit_bus_adapter #(
-		parameter AUTO_CLOCK_CLOCK_RATE = "-1"
-	) (
-		input  wire        clk,       //         clock.clk
-		input  wire        rst_n,     //         reset.reset_n
-		input  wire        cs_n,      //  avalon_slave.chipselect_n
-		input  wire [15:0] address,   //              .address
-		input  wire [7:0]  writedata, //              .writedata
-		input  wire        wr_n,      //              .write_n
-		input  wire        rd_n,      //              .read_n
-		output wire        wait_n,    //              .waitrequest_n
-		output wire [7:0]  readdata,  //              .readdata
-		output wire        b_cs_n,    // eight_bit_bus.export
-		output wire        b_rd_n,    //              .export
-		output wire        b_wr_n,    //              .export
-		input  wire        b_wait_n,  //              .export
-		output wire [15:0] b_addr,    //              .export
-		inout  wire [7:0]  b_data     //              .export
-	);
-
-	// TODO: Auto-generated HDL template
-
-	assign readdata = 8'b00000000;
-
-	assign b_cs_n = 1'b0;
-
-	assign b_wr_n = 1'b0;
-
-	assign b_rd_n = 1'b0;
-
-	assign b_addr = 16'b0000000000000000;
-
-endmodule
diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd
deleted file mode 100644
index 5983f63..0000000
--- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd
+++ /dev/null
@@ -1,53 +0,0 @@
--- async_8bit_bus_adapter.vhd
-
--- This file was auto-generated as a prototype implementation of a module
--- created in component editor.  It ties off all outputs to ground and
--- ignores all inputs.  It needs to be edited to make it do something
--- useful.
--- 
--- This file will not be automatically regenerated.  You should check it in
--- to your version control system if you want to keep it.
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity async_8bit_bus_adapter is
-	generic (
-		AUTO_CLOCK_CLOCK_RATE : string := "-1"
-	);
-	port (
-		clk       : in    std_logic                     := '0';             --         clock.clk
-		rst_n     : in    std_logic                     := '0';             --         reset.reset_n
-		cs_n      : in    std_logic                     := '0';             --  avalon_slave.chipselect_n
-		address   : in    std_logic_vector(15 downto 0) := (others => '0'); --              .address
-		writedata : in    std_logic_vector(7 downto 0)  := (others => '0'); --              .writedata
-		wr_n      : in    std_logic                     := '0';             --              .write_n
-		rd_n      : in    std_logic                     := '0';             --              .read_n
-		wait_n    : out   std_logic;                                        --              .waitrequest_n
-		readdata  : out   std_logic_vector(7 downto 0);                     --              .readdata
-		b_cs_n    : out   std_logic;                                        -- eight_bit_bus.export
-		b_rd_n    : out   std_logic;                                        --              .export
-		b_wr_n    : out   std_logic;                                        --              .export
-		b_wait_n  : in    std_logic                     := '0';             --              .export
-		b_addr    : out   std_logic;                                        --              .export
-		b_data    : inout std_logic                     := '0'              --              .export
-	);
-end entity async_8bit_bus_adapter;
-
-architecture rtl of async_8bit_bus_adapter is
-begin
-
-	-- TODO: Auto-generated HDL template
-
-	readdata <= "00000000";
-
-	b_cs_n <= '0';
-
-	b_wr_n <= '0';
-
-	b_rd_n <= '0';
-
-	b_addr <= '0';
-
-end architecture rtl; -- of async_8bit_bus_adapter
diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl
index d4f8021..d4b4688 100644
--- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl
+++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 13.0sp1
-# Sun Oct 13 12:34:21 BST 2013
+# Mon Oct 14 15:03:03 BST 2013
 # DO NOT MODIFY
 
 
 # 
 # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0
-#  2013.10.13.12:34:21
+#  2013.10.14.15:03:03
 # 
 # 
 
@@ -39,7 +39,7 @@ set_module_property ALLOW_GREYBOX_GENERATION false
 add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
 set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_8bit_bus_adapter
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-add_fileset_file async_8bit_bus_adapter.v VERILOG PATH async_8bit_bus_adapter.v TOP_LEVEL_FILE
+add_fileset_file async_8bit_bus_adapter.vhd VHDL PATH hdl/async_8bit_bus_adapter.vhd TOP_LEVEL_FILE
 
 add_fileset SIM_VHDL SIM_VHDL "" ""
 set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter
@@ -137,5 +137,6 @@ add_interface_port eight_bit_bus b_rd_n export Output 1
 add_interface_port eight_bit_bus b_wr_n export Output 1
 add_interface_port eight_bit_bus b_wait_n export Input 1
 add_interface_port eight_bit_bus b_addr export Output 16
-add_interface_port eight_bit_bus b_data export Bidir 8
+add_interface_port eight_bit_bus b_data_in export Input 8
+add_interface_port eight_bit_bus b_data_out export Output 8
 
diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~
index bd77527..5171d01 100644
--- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~
+++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~
@@ -1,11 +1,11 @@
 # TCL File Generated by Component Editor 13.0sp1
-# Sun Oct 13 12:34:12 BST 2013
+# Mon Oct 14 15:01:25 BST 2013
 # DO NOT MODIFY
 
 
 # 
 # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0
-#  2013.10.13.12:34:12
+#  2013.10.14.15:01:25
 # 
 # 
 
@@ -26,7 +26,7 @@ set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property GROUP my_lib
 set_module_property AUTHOR ""
 set_module_property DISPLAY_NAME async_8bit_bus_adapter
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE false
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
 set_module_property EDITABLE true
 set_module_property ANALYZE_HDL AUTO
 set_module_property REPORT_TO_TALKBACK false
@@ -36,6 +36,11 @@ set_module_property ALLOW_GREYBOX_GENERATION false
 # 
 # file sets
 # 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_8bit_bus_adapter
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+add_fileset_file async_8bit_bus_adapter.vhd VHDL PATH hdl/async_8bit_bus_adapter.vhd TOP_LEVEL_FILE
+
 add_fileset SIM_VHDL SIM_VHDL "" ""
 set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter
 set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
@@ -132,5 +137,6 @@ add_interface_port eight_bit_bus b_rd_n export Output 1
 add_interface_port eight_bit_bus b_wr_n export Output 1
 add_interface_port eight_bit_bus b_wait_n export Input 1
 add_interface_port eight_bit_bus b_addr export Output 16
-add_interface_port eight_bit_bus b_data export Bidir 8
+add_interface_port eight_bit_bus b_data_in export Input 8
+add_interface_port eight_bit_bus b_data_out export Output 8
 
diff --git a/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd
new file mode 100644
index 0000000..29e4ff3
--- /dev/null
+++ b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd
@@ -0,0 +1,56 @@
+-- async_8bit_bus_adapter.vhd
+
+-- This file was auto-generated as a prototype implementation of a module
+-- created in component editor.  It ties off all outputs to ground and
+-- ignores all inputs.  It needs to be edited to make it do something
+-- useful.
+-- 
+-- This file will not be automatically regenerated.  You should check it in
+-- to your version control system if you want to keep it.
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity async_8bit_bus_adapter is
+	generic (
+		AUTO_CLOCK_CLOCK_RATE : string := "-1"
+	);
+	port (
+		clk        : in  std_logic                     := '0';             --         clock.clk
+		rst_n      : in  std_logic                     := '0';             --         reset.reset_n
+		cs_n       : in  std_logic                     := '0';             --  avalon_slave.chipselect_n
+		address    : in  std_logic_vector(15 downto 0) := (others => '0'); --              .address
+		writedata  : in  std_logic_vector(7 downto 0)  := (others => '0'); --              .writedata
+		wr_n       : in  std_logic                     := '0';             --              .write_n
+		rd_n       : in  std_logic                     := '0';             --              .read_n
+		wait_n     : out std_logic;                                        --              .waitrequest_n
+		readdata   : out std_logic_vector(7 downto 0);                     --              .readdata
+		b_cs_n     : out std_logic;                                        -- eight_bit_bus.export
+		b_rd_n     : out std_logic;                                        --              .export
+		b_wr_n     : out std_logic;                                        --              .export
+		b_wait_n   : in  std_logic                     := '0';             --              .export
+		b_addr     : out std_logic_vector(15 downto 0);                    --              .export
+		b_data_in  : in  std_logic_vector(7 downto 0)  := (others => '0'); --              .export
+		b_data_out : out std_logic_vector(7 downto 0)                      --              .export
+	);
+end entity async_8bit_bus_adapter;
+
+architecture rtl of async_8bit_bus_adapter is
+begin
+
+	-- TODO: Auto-generated HDL template
+
+	readdata <= "00000000";
+
+	b_cs_n <= '0';
+
+	b_wr_n <= '0';
+
+	b_rd_n <= '0';
+
+	b_data_out <= "00000000";
+
+	b_addr <= "0000000000000000";
+
+end architecture rtl; -- of async_8bit_bus_adapter