diff options
Diffstat (limited to 'async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v')
| -rw-r--r-- | async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v deleted file mode 100644 index bfd69c3..0000000 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.v +++ /dev/null @@ -1,44 +0,0 @@ -// async_8bit_bus_adapter.v - -// This file was auto-generated as a prototype implementation of a module -// created in component editor. It ties off all outputs to ground and -// ignores all inputs. It needs to be edited to make it do something -// useful. -// -// This file will not be automatically regenerated. You should check it in -// to your version control system if you want to keep it. - -`timescale 1 ps / 1 ps -module async_8bit_bus_adapter #( - parameter AUTO_CLOCK_CLOCK_RATE = "-1" - ) ( - input wire clk, // clock.clk - input wire rst_n, // reset.reset_n - input wire cs_n, // avalon_slave.chipselect_n - input wire [15:0] address, // .address - input wire [7:0] writedata, // .writedata - input wire wr_n, // .write_n - input wire rd_n, // .read_n - output wire wait_n, // .waitrequest_n - output wire [7:0] readdata, // .readdata - output wire b_cs_n, // eight_bit_bus.export - output wire b_rd_n, // .export - output wire b_wr_n, // .export - input wire b_wait_n, // .export - output wire [15:0] b_addr, // .export - inout wire [7:0] b_data // .export - ); - - // TODO: Auto-generated HDL template - - assign readdata = 8'b00000000; - - assign b_cs_n = 1'b0; - - assign b_wr_n = 1'b0; - - assign b_rd_n = 1'b0; - - assign b_addr = 16'b0000000000000000; - -endmodule |