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Diffstat (limited to 'async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd')
-rw-r--r--async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd53
1 files changed, 0 insertions, 53 deletions
diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd
deleted file mode 100644
index 5983f63..0000000
--- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter.vhd
+++ /dev/null
@@ -1,53 +0,0 @@
--- async_8bit_bus_adapter.vhd
-
--- This file was auto-generated as a prototype implementation of a module
--- created in component editor. It ties off all outputs to ground and
--- ignores all inputs. It needs to be edited to make it do something
--- useful.
---
--- This file will not be automatically regenerated. You should check it in
--- to your version control system if you want to keep it.
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity async_8bit_bus_adapter is
- generic (
- AUTO_CLOCK_CLOCK_RATE : string := "-1"
- );
- port (
- clk : in std_logic := '0'; -- clock.clk
- rst_n : in std_logic := '0'; -- reset.reset_n
- cs_n : in std_logic := '0'; -- avalon_slave.chipselect_n
- address : in std_logic_vector(15 downto 0) := (others => '0'); -- .address
- writedata : in std_logic_vector(7 downto 0) := (others => '0'); -- .writedata
- wr_n : in std_logic := '0'; -- .write_n
- rd_n : in std_logic := '0'; -- .read_n
- wait_n : out std_logic; -- .waitrequest_n
- readdata : out std_logic_vector(7 downto 0); -- .readdata
- b_cs_n : out std_logic; -- eight_bit_bus.export
- b_rd_n : out std_logic; -- .export
- b_wr_n : out std_logic; -- .export
- b_wait_n : in std_logic := '0'; -- .export
- b_addr : out std_logic; -- .export
- b_data : inout std_logic := '0' -- .export
- );
-end entity async_8bit_bus_adapter;
-
-architecture rtl of async_8bit_bus_adapter is
-begin
-
- -- TODO: Auto-generated HDL template
-
- readdata <= "00000000";
-
- b_cs_n <= '0';
-
- b_wr_n <= '0';
-
- b_rd_n <= '0';
-
- b_addr <= '0';
-
-end architecture rtl; -- of async_8bit_bus_adapter