diff options
Diffstat (limited to 'async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~')
| -rw-r--r-- | async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ index bd77527..5171d01 100644 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Sun Oct 13 12:34:12 BST 2013 +# Mon Oct 14 15:01:25 BST 2013 # DO NOT MODIFY # # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 -# 2013.10.13.12:34:12 +# 2013.10.14.15:01:25 # # @@ -26,7 +26,7 @@ set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP my_lib set_module_property AUTHOR "" set_module_property DISPLAY_NAME async_8bit_bus_adapter -set_module_property INSTANTIATE_IN_SYSTEM_MODULE false +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property ANALYZE_HDL AUTO set_module_property REPORT_TO_TALKBACK false @@ -36,6 +36,11 @@ set_module_property ALLOW_GREYBOX_GENERATION false # # file sets # +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL async_8bit_bus_adapter +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +add_fileset_file async_8bit_bus_adapter.vhd VHDL PATH hdl/async_8bit_bus_adapter.vhd TOP_LEVEL_FILE + add_fileset SIM_VHDL SIM_VHDL "" "" set_fileset_property SIM_VHDL TOP_LEVEL async_8bit_bus_adapter set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false @@ -132,5 +137,6 @@ add_interface_port eight_bit_bus b_rd_n export Output 1 add_interface_port eight_bit_bus b_wr_n export Output 1 add_interface_port eight_bit_bus b_wait_n export Input 1 add_interface_port eight_bit_bus b_addr export Output 16 -add_interface_port eight_bit_bus b_data export Bidir 8 +add_interface_port eight_bit_bus b_data_in export Input 8 +add_interface_port eight_bit_bus b_data_out export Output 8 |