diff options
author | James <james.mckenzie@citrix.com> | 2013-10-14 19:06:11 +0100 |
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committer | James <james.mckenzie@citrix.com> | 2013-10-14 19:06:11 +0100 |
commit | 16af4b953306063c2aed52ab2ecde07e0bc6b5e4 (patch) | |
tree | 83839ec3e3308396a22576ffeac5a4b7cce6bf26 | |
parent | 3b79402993f7857243ab033644d7ca6b757be76d (diff) | |
download | sdram-16af4b953306063c2aed52ab2ecde07e0bc6b5e4.tar.gz sdram-16af4b953306063c2aed52ab2ecde07e0bc6b5e4.tar.bz2 sdram-16af4b953306063c2aed52ab2ecde07e0bc6b5e4.zip |
works!
-rw-r--r-- | Makefile | 6 | ||||
-rw-r--r-- | async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl | 5 | ||||
-rw-r--r-- | async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ | 4 | ||||
-rw-r--r-- | async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd | 21 | ||||
-rw-r--r-- | sdram.vhd | 49 | ||||
-rw-r--r-- | sdram_ctrl.vhd | 73 | ||||
-rw-r--r-- | sdram_mcu.qsys | 86 | ||||
-rw-r--r-- | sdram_util.vhd | 1 | ||||
-rw-r--r-- | src/sdram.c | 65 |
9 files changed, 174 insertions, 136 deletions
@@ -37,12 +37,12 @@ fit.stamp: ans.stamp tools/wrap quartus_fit --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ} touch $@ -ans.stamp: source.stamp #ans.stamp: source.stamp ${SOPC_FILE} +ans.stamp: source.stamp tools/wrap quartus_map --read_settings_files=on --write_settings_files=off ${PROJ} -c ${PROJ} touch $@ -${SOPC_FILE}:ans.stamp +${SOPC_FILE}:asm.stamp #${SOPC_FILE}:${QSYS}.qsys # rm -rf ${QSYS} @@ -52,7 +52,7 @@ ${SOPC_FILE}:ans.stamp source.stamp:${SRCS} touch source.stamp -${ELF}: src/Makefile +${ELF}: src/Makefile $(wildcard src/*.c) tools/wrap make -C src elf.stamp:${ELF} diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl index 0b52d75..9aefbce 100644 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Mon Oct 14 15:16:40 BST 2013 +# Mon Oct 14 17:51:02 BST 2013 # DO NOT MODIFY # # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 -# 2013.10.14.15:16:40 +# 2013.10.14.17:51:02 # # @@ -138,4 +138,5 @@ add_interface_port eight_bit_bus b_wait_n export Input 1 add_interface_port eight_bit_bus b_addr export Output 16 add_interface_port eight_bit_bus b_data_in export Input 8 add_interface_port eight_bit_bus b_data_out export Output 8 +add_interface_port eight_bit_bus b_reset_n export Output 1 diff --git a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ index 19ea7ae..0b52d75 100644 --- a/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ +++ b/async_8bit_bus_adapter_hw/async_8bit_bus_adapter_hw.tcl~ @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 13.0sp1 -# Mon Oct 14 15:03:03 BST 2013 +# Mon Oct 14 15:16:40 BST 2013 # DO NOT MODIFY # # async_8bit_bus_adapter "async_8bit_bus_adapter" v1.0 -# 2013.10.14.15:03:03 +# 2013.10.14.15:16:40 # # diff --git a/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd index 14c45e7..c48663f 100644 --- a/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd +++ b/async_8bit_bus_adapter_hw/hdl/async_8bit_bus_adapter.vhd @@ -26,7 +26,8 @@ entity async_8bit_bus_adapter is rd_n : in std_logic := '0'; -- .read_n wait_n : out std_logic; -- .waitrequest_n readdata : out std_logic_vector(7 downto 0); -- .readdata - b_cs_n : out std_logic; -- eight_bit_bus.export + b_reset_n : out std_logic; -- eight_bit_bus.export + b_cs_n : out std_logic; -- .export b_rnw : out std_logic; -- .export b_wait_n : in std_logic := '0'; -- .export b_addr : out std_logic_vector(15 downto 0); -- .export @@ -36,18 +37,18 @@ entity async_8bit_bus_adapter is end entity async_8bit_bus_adapter; architecture rtl of async_8bit_bus_adapter is -begin - - -- TODO: Auto-generated HDL template - readdata <= "00000000"; - - b_cs_n <= '0'; +signal state:std_logic_vector(2 downto 0); +begin - b_rnw <= '0'; + b_addr <= address; + readdata <= b_data_in; + b_data_out <= writedata; - b_data_out <= "00000000"; + b_reset_n <= rst_n; + b_cs_n <= cs_n or ( wr_n and rd_n ); + b_rnw <= wr_n; + wait_n <= b_wait_n; - b_addr <= "0000000000000000"; end architecture rtl; -- of async_8bit_bus_adapter @@ -45,13 +45,14 @@ component sdram_mcu is port ( clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X'; -- reset_n - pio_0_d_export : out std_logic_vector(7 downto 0); -- export +-- pio_0_d_export : out std_logic_vector(7 downto 0); -- export ebb_0_cs_n : out std_logic; -- cs_n ebb_0_rnw : out std_logic; -- rnw ebb_0_wait_n : in std_logic := 'X'; -- wait_n ebb_0_addr : out std_logic_vector(15 downto 0); -- addr ebb_0_data_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- data_in - ebb_0_data_out : out std_logic_vector(7 downto 0) -- data_out + ebb_0_data_out : out std_logic_vector(7 downto 0); -- data_out + ebb_0_reset_n : out std_logic -- reset_n ); end component sdram_mcu; @@ -83,7 +84,9 @@ component sdram_ctrl is sdram_ba : out std_logic_vector(1 downto 0); sdram_dq : inout data_t; - sdram_dqm : out dqm_t + sdram_dqm : out dqm_t; + + debug : out std_logic_vector(7 downto 0) ); end component; @@ -99,10 +102,15 @@ signal b_rnw : std_logic; signal b_wait_n : std_logic; signal pll_reset : std_logic; +signal mcu_clock : std_logic; signal clock_100 : std_logic; signal pll_locked : std_logic; +signal debug : std_logic_vector(7 downto 0); signal global_reset_n : std_logic; +signal b_reset_n : std_logic; + +signal buf8 : std_logic_vector(7 downto 0); begin @@ -113,16 +121,19 @@ begin clock_100, pll_locked ); + mcu_clock <= clock_50; + u0 : component sdram_mcu port map ( - clk_clk => clock_100, -- clk.clk + clk_clk => mcu_clock, -- clk.clk reset_reset_n => global_reset_n, -- reset.reset_n - pio_0_d_export => seven_seg, -- pio_0_d.export +-- pio_0_d_export => seven_seg, -- pio_0_d.export ebb_0_cs_n => b_cs_n, -- ebb_0.cs_n ebb_0_rnw => b_rnw, -- .rnw ebb_0_wait_n => b_wait_n, -- .wait_n ebb_0_addr => b_addr16, -- .addr ebb_0_data_in => b_data_in8, -- .data - ebb_0_data_out => b_data_out8 -- .data + ebb_0_data_out => b_data_out8, -- .data + ebb_0_reset_n => b_reset_n ); -- bodge buses together @@ -130,14 +141,32 @@ begin b_data_in(7 downto 0) <= b_data_out8; b_data_in(15 downto 8) <= (others =>'0'); + + ss_process: process (global_reset_n,b_rnw,b_cs_n,b_addr16) begin + if l2b_al(global_reset_n) then + buf8<=(others => '0'); + elsif falling_edge(b_cs_n) and l2b_al(b_rnw) then + buf8 <= b_data_out8; + end if; + end process; + +-- seven_seg <= buf8; + + seven_seg <= debug; + --b_data_in8 <= buf8; + --b_wait_n <= '1'; b_data_in8 <= b_data_out(7 downto 0); + --seven_seg <= b_data_in8; + --b_data_in8 <= "01011010"; + b_addr(15 downto 0) <= b_addr16; b_addr(23 downto 16) <= (others => '0'); + sdram_ctrl0: sdram_ctrl port map ( - clock_100 => clock_100, - reset_n => global_reset_n, + clock_100 => clock_50, + reset_n => b_reset_n, bus_cs_n => b_cs_n, bus_rnw => b_rnw, @@ -160,7 +189,9 @@ begin sdram_ba => sdram_ba, sdram_dq => sdram_dq, - sdram_dqm => sdram_dqm + sdram_dqm => sdram_dqm, + + debug => debug ); pll_reset <= '0'; diff --git a/sdram_ctrl.vhd b/sdram_ctrl.vhd index d41b1b6..58064bd 100644 --- a/sdram_ctrl.vhd +++ b/sdram_ctrl.vhd @@ -36,7 +36,9 @@ entity sdram_ctrl is sdram_ba : out std_logic_vector(1 downto 0); sdram_dq : inout data_t; - sdram_dqm : out dqm_t + sdram_dqm : out dqm_t; + + debug : out std_logic_vector(7 downto 0) ); end entity; @@ -46,6 +48,18 @@ architecture rtl of sdram_ctrl is signal clock : std_logic; + + constant DEBUG_0 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#3F#,7)); + constant DEBUG_1 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#06#,7)); + constant DEBUG_2 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#5B#,7)); + constant DEBUG_3 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#4F#,7)); + constant DEBUG_4 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#66#,7)); + constant DEBUG_5 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#6D#,7)); + constant DEBUG_6 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#7D#,7)); + constant DEBUG_7 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#07#,7)); + constant DEBUG_8 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#7F#,7)); + constant DEBUG_9 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#6F#,7)); + -- bits in the MEM_CMD register RAS_N CAS_N WE_N constant MEM_CMD_NOP : std_logic_vector(2 downto 0 ):="111"; @@ -74,6 +88,11 @@ architecture rtl of sdram_ctrl is signal i_next : uint3_t; signal i_refs : uint3_t; + -- debuging + signal i_debug : std_logic_vector(6 downto 0); + signal m_debug : std_logic_vector(7 downto 0); + signal b_debug : std_logic_vector(7 downto 0); + -- init fsm signal i_state :uint3_t; @@ -193,10 +212,11 @@ begin end if; end process; - request_pending_process: process(reset_n, clock, post_request, request_pending,ack_request) begin + request_pending_process: process(reset_n, clock, post_request, request_pending,ack_request,refresh_counter) begin if l2b_al(reset_n) then request_pending <= '0'; elsif rising_edge(clock) then + --request_pending <= post_request or (request_pending and not b2l_ah(refresh_counter = 0 )); request_pending <= post_request or (request_pending and not ack_request); end if; end process; @@ -218,9 +238,11 @@ begin i_cmd <= MEM_CMD_NOP; i_addr <= (others => '1'); i_count <= 0; + i_debug <= DEBUG_0; elsif rising_edge(clock) then if i_state = I_ST_RESET_WAIT then + i_debug <= DEBUG_1; -- after reset wait until the refresh_counter ticks over for RAM to stabalize i_cs_n <=MEM_CS_N_NONE; i_cmd <= MEM_CMD_NOP; @@ -229,6 +251,7 @@ begin i_state <= I_ST_PRECHARGE; end if; elsif i_state = I_ST_PRECHARGE then + i_debug <= DEBUG_2; -- precharge all banks, wait one clock, then go to refresh i_cs_n <=MEM_CS_N_ALL; i_cmd <=MEM_CMD_PRE; @@ -236,6 +259,7 @@ begin i_count <= 1; i_next <= I_ST_REFRESH; elsif i_state =I_ST_REFRESH then + i_debug <= DEBUG_3; -- repeat 7 times { refresh, wait 5 counts } i_cs_n <=MEM_CS_N_ALL; i_cmd <=MEM_CMD_REF; @@ -250,6 +274,7 @@ begin i_next <= I_ST_REFRESH; end if; elsif i_state = I_ST_WAIT_COUNT then + i_debug <= DEBUG_4; -- wait i_count ticks then goto state i_next i_cs_n <=MEM_CS_N_ALL; i_cmd <= MEM_CMD_NOP; @@ -260,6 +285,7 @@ begin end if; elsif i_state=I_ST_SET_MODE then + i_debug <= DEBUG_5; -- set mode, wait 3 ticks then goto done i_cs_n <=MEM_CS_N_ALL; i_cmd <= MEM_CMD_MRS; @@ -274,8 +300,10 @@ begin i_addr <= "0000000110000"; i_count <= 3; i_next <= I_ST_DONE; + i_state <= I_ST_WAIT_COUNT; elsif i_state=I_ST_DONE then + i_debug <= DEBUG_6; i_state <= I_ST_DONE; else i_state <= I_ST_RESET_WAIT; @@ -283,7 +311,7 @@ begin end if; end process; - main_fsm: process (reset_n,clock,m_state,need_refresh,request_pending,request_addr,request_data,request_cs_n,request_rnw,request_dqm) begin + main_fsm: process (reset_n,clock,m_state,need_refresh,request_pending,request_addr,request_data,request_cs_n,request_rnw,request_dqm,i_debug) begin if reset_n ='0' then m_state <= M_ST_WAITING_INIT; @@ -298,8 +326,12 @@ begin ack_refresh <= '0'; ack_request <= '0'; mem_oe <= '0'; + m_debug(6 downto 0) <=(others =>'0'); + m_debug(7) <='1'; elsif rising_edge(clock) then if m_state =M_ST_WAITING_INIT then + m_debug(6 downto 0) <= i_debug; + m_debug(7) <='1'; mem_addr <= i_addr; mem_cmd <= i_cmd; mem_cs_n <= i_cs_n; @@ -308,6 +340,8 @@ begin m_state <= M_ST_IDLE; end if; elsif m_state = M_ST_IDLE then + m_debug(6 downto 0) <= DEBUG_1; + m_debug(7) <='0'; mem_cmd <= MEM_CMD_NOP; ack_refresh <='0'; @@ -342,6 +376,7 @@ begin end if; end if; elsif m_state = M_ST_RAS then + m_debug(6 downto 0) <= DEBUG_2; -- activate the relevant ROW, wait 3 clocks, then go and do the read or write ack_request <='0'; @@ -362,6 +397,7 @@ begin m_next <= M_ST_WRITE; end if; elsif m_state = M_ST_NOP_COUNT then + m_debug(6 downto 0) <= DEBUG_3; -- send nops for m_count, then go to state m_next mem_cmd <=MEM_CMD_NOP; if m_count > 1 then @@ -370,6 +406,7 @@ begin m_state <= m_next; end if; elsif m_state = M_ST_READ then + m_debug(6 downto 0) <= DEBUG_4; ack_request <='0'; mem_cmd <=MEM_CMD_READ; @@ -377,8 +414,9 @@ begin mem_addr(12 downto 9) <= (others => '0'); mem_addr(8 downto 0) <= active_addr(8 downto 0); - m_next <= M_ST_ACTIVE; + m_state <= M_ST_ACTIVE; elsif m_state = M_ST_WRITE then + m_debug(6 downto 0) <= DEBUG_5; ack_request <='0'; mem_cmd<=MEM_CMD_WRIT; @@ -391,6 +429,7 @@ begin m_state <=M_ST_ACTIVE; elsif m_state = M_ST_ACTIVE then + m_debug(6 downto 0) <= DEBUG_6; -- turn off drivers (we might have come from a write) mem_oe <= '0'; @@ -428,6 +467,7 @@ begin end if; elsif m_state = M_ST_WAIT_FOR_PRECHARGE then + m_debug(6 downto 0) <= DEBUG_7; -- wait count then do a precharge mem_cmd <= MEM_CMD_NOP; if m_count > 1 then @@ -436,12 +476,14 @@ begin m_state<=M_ST_PRECHARGE; end if; elsif m_state = M_ST_PRECHARGE then + m_debug(6 downto 0) <= DEBUG_8; -- do a precharge, wait two clocks, then goto m_next mem_addr <= (others => '1'); mem_cmd <= MEM_CMD_PRE; m_count <= 1; m_state <= M_ST_NOP_COUNT; elsif m_state=M_ST_REFRESH then + m_debug(6 downto 0) <= DEBUG_9; -- do a refresh, wait six clocks, return to idle mem_cmd <= MEM_CMD_REF; @@ -453,6 +495,8 @@ begin ack_refresh <= '1'; else -- shouldn't be here - crash + m_debug(7) <='1'; + m_debug(6 downto 0) <= DEBUG_9; mem_cmd <=MEM_CMD_NOP; mem_cs_n <= MEM_CS_N_NONE; mem_oe <= '0'; @@ -503,32 +547,37 @@ begin request_cs_n <= MEM_CS_N_NONE; request_dqm <= "00"; b_state <= B_ST_WAIT_CS_N_LOW; + b_debug(6 downto 0) <= DEBUG_0; + b_debug(7) <='0'; + bus_wait_n <= '0'; elsif rising_edge(clock) then if b_state = B_ST_WAIT_CS_N_LOW then + b_debug(6 downto 0) <= DEBUG_1; + bus_wait_n <= '0'; if l2b_al(bus_cs_n) then -- new request ship it to the main state machine post_request <='1'; request_addr <= bus_addr; request_rnw <= bus_rnw; request_data <= bus_data_in; - request_rnw <= '0'; -- send to first chip and all bytes request_cs_n <= "0"; -- (others => '1'); request_dqm <= "00"; - bus_wait_n <= '0'; b_state <= B_ST_LODGE_REQUEST; end if; elsif b_state =B_ST_LODGE_REQUEST then + b_debug(6 downto 0) <= DEBUG_2; post_request <='0'; b_state <= B_ST_WAIT_ACK; elsif b_state =B_ST_WAIT_ACK then + b_debug(6 downto 0) <= DEBUG_3; if not l2b_ah(request_pending) then -- the logic has pushed the request to the ram if l2b_al(request_rnw) then - -- if it's a write we're all done bus_wait_n <= '1'; + -- if it's a write we're all done b_state <= B_ST_WAIT_CS_N_HIGH; else -- if it's a read we have to wait for the data @@ -536,20 +585,28 @@ begin end if; end if; elsif b_state = B_ST_WAIT_DATA then + b_debug(6 downto 0) <= DEBUG_4; if l2b_ah(r_data_valid(0)) then bus_data_out <= mem_data_in; - bus_wait_n <= '1'; +-- bus_data_out <= request_addr(15 downto 0); + bus_wait_n <= '1'; b_state <= B_ST_WAIT_CS_N_HIGH; end if; elsif b_state = B_ST_WAIT_CS_N_HIGH then + b_debug(6 downto 0) <= DEBUG_5; + b_debug(7) <='1'; if not l2b_al(bus_cs_n) then + bus_wait_n <= '0'; b_state <=B_ST_WAIT_CS_N_LOW; end if; else b_state <=B_ST_WAIT_CS_N_LOW; end if; end if; + end process; +-- debug <=b_debug; + debug <= m_debug; end; diff --git a/sdram_mcu.qsys b/sdram_mcu.qsys index ef018be..dabb9ba 100644 --- a/sdram_mcu.qsys +++ b/sdram_mcu.qsys @@ -16,7 +16,7 @@ { datum _sortIndex { - value = "7"; + value = "6"; type = "int"; } } @@ -24,7 +24,7 @@ { datum baseAddress { - value = "172128"; + value = "172104"; type = "String"; } } @@ -77,7 +77,7 @@ { datum _sortIndex { - value = "5"; + value = "4"; type = "int"; } } @@ -93,26 +93,10 @@ { datum _sortIndex { - value = "6"; - type = "int"; - } - } - element pio_0 - { - datum _sortIndex - { - value = "4"; + value = "5"; type = "int"; } } - element onchip_memory2_0.s1 - { - datum baseAddress - { - value = "147456"; - type = "String"; - } - } element timer_0.s1 { datum baseAddress @@ -121,11 +105,11 @@ type = "String"; } } - element pio_0.s1 + element onchip_memory2_0.s1 { datum baseAddress { - value = "172112"; + value = "147456"; type = "String"; } } @@ -152,17 +136,12 @@ <parameter name="projectName" value="sdram.qpf" /> <parameter name="sopcBorderPoints" value="false" /> <parameter name="systemHash" value="1" /> - <parameter name="timeStamp" value="1381760107235" /> + <parameter name="timeStamp" value="1381769366909" /> <parameter name="useTestBenchNamingPattern" value="false" /> <instanceScript></instanceScript> <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" /> <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" /> <interface - name="pio_0_d" - internal="pio_0.external_connection" - type="conduit" - dir="end" /> - <interface name="ebb_0" internal="async_8bit_bus_adapter_0.eight_bit_bus" type="conduit" @@ -278,8 +257,8 @@ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" /> <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" /> <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" /> - <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='async_8bit_bus_adapter_0.avalon_slave' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x24000' end='0x26EE0' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x29000' end='0x29800' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x29800' end='0x2A000' /><slave name='timer_0.s1' start='0x2A020' end='0x2A040' /><slave name='pio_0.s1' start='0x2A050' end='0x2A060' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2A060' end='0x2A068' /></address-map>]]></parameter> - <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='async_8bit_bus_adapter_0.avalon_slave' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x24000' end='0x26EE0' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x29000' end='0x29800' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x29800' end='0x2A000' /><slave name='timer_0.s1' start='0x2A020' end='0x2A040' /><slave name='pio_0.s1' start='0x2A050' end='0x2A060' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2A060' end='0x2A068' /></address-map>]]></parameter> + <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='async_8bit_bus_adapter_0.avalon_slave' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x24000' end='0x26EE0' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x29000' end='0x29800' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x29800' end='0x2A000' /><slave name='timer_0.s1' start='0x2A020' end='0x2A040' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2A048' end='0x2A050' /></address-map>]]></parameter> + <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='async_8bit_bus_adapter_0.avalon_slave' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x24000' end='0x26EE0' /><slave name='nios2_qsys_0.jtag_debug_module' start='0x29000' end='0x29800' /><slave name='epcs_flash_controller_0.epcs_control_port' start='0x29800' end='0x2A000' /><slave name='timer_0.s1' start='0x2A020' end='0x2A040' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2A048' end='0x2A050' /></address-map>]]></parameter> <parameter name="clockFrequency" value="80000000" /> <parameter name="deviceFamilyName" value="Cyclone II" /> <parameter name="internalIrqMaskSystemInfo" value="7" /> @@ -321,24 +300,6 @@ <parameter name="systemFrequency" value="80000000" /> </module> <module - kind="altera_avalon_pio" - version="13.0.1.99.2" - enabled="1" - name="pio_0"> - <parameter name="bitClearingEdgeCapReg" value="false" /> - <parameter name="bitModifyingOutReg" value="false" /> - <parameter name="captureEdge" value="false" /> - <parameter name="direction" value="Output" /> - <parameter name="edgeType" value="RISING" /> - <parameter name="generateIRQ" value="false" /> - <parameter name="irqType" value="LEVEL" /> - <parameter name="resetValue" value="0" /> - <parameter name="simDoTestBenchWiring" value="false" /> - <parameter name="simDrivenValue" value="0" /> - <parameter name="width" value="8" /> - <parameter name="clockRate" value="80000000" /> - </module> - <module kind="altera_avalon_jtag_uart" version="13.0.1.99.2" enabled="1" @@ -435,22 +396,6 @@ version="13.0" start="nios2_qsys_0.jtag_debug_module_reset" end="timer_0.reset" /> - <connection kind="clock" version="13.0" start="clk_0.clk" end="pio_0.clk" /> - <connection kind="reset" version="13.0" start="clk_0.clk_reset" end="pio_0.reset" /> - <connection - kind="avalon" - version="13.0" - start="nios2_qsys_0.data_master" - end="pio_0.s1"> - <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x0002a050" /> - <parameter name="defaultConnection" value="false" /> - </connection> - <connection - kind="reset" - version="13.0" - start="nios2_qsys_0.jtag_debug_module_reset" - end="pio_0.reset" /> <connection kind="clock" version="13.0" start="clk_0.clk" end="jtag_uart_0.clk" /> <connection kind="reset" @@ -468,7 +413,7 @@ start="nios2_qsys_0.data_master" end="jtag_uart_0.avalon_jtag_slave"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x0002a060" /> + <parameter name="baseAddress" value="0x0002a048" /> <parameter name="defaultConnection" value="false" /> </connection> <connection @@ -574,18 +519,9 @@ kind="avalon" version="13.0" start="nios2_qsys_0.instruction_master" - end="pio_0.s1"> - <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x0002a050" /> - <parameter name="defaultConnection" value="false" /> - </connection> - <connection - kind="avalon" - version="13.0" - start="nios2_qsys_0.instruction_master" end="jtag_uart_0.avalon_jtag_slave"> <parameter name="arbitrationPriority" value="1" /> - <parameter name="baseAddress" value="0x0002a060" /> + <parameter name="baseAddress" value="0x0002a048" /> <parameter name="defaultConnection" value="false" /> </connection> <connection diff --git a/sdram_util.vhd b/sdram_util.vhd index 23c1d1e..7dfcb47 100644 --- a/sdram_util.vhd +++ b/sdram_util.vhd @@ -6,6 +6,7 @@ package sdram_util is subtype uint3_t is integer range 0 to 7; subtype uint4_t is integer range 0 to 15; +subtype uint8_t is integer range 0 to 255; subtype uint13_t is integer range 0 to 8191; subtype cs_n_t is std_logic_vector(0 downto 0); subtype addr_t is std_logic_vector(23 downto 0); diff --git a/src/sdram.c b/src/sdram.c index 60b9459..91bdad1 100644 --- a/src/sdram.c +++ b/src/sdram.c @@ -9,46 +9,57 @@ #define msleep(msec) usleep(1000*msec); +#ifdef PIO_0_BASE pio_write (unsigned int data) { IOWR (PIO_0_BASE, 0, data); } +#endif - -static void -show_score (int score) +void +ebb_write (unsigned int addr, uint8_t data) { - // int to seven segment lookup: MSB dp g f e d c b a LSB - const uint8_t lookup[10] = - { 0x3F, 0x6, 0x5B, 0x4F, 0x66, 0x6D, 0x7D, 0x7, 0x7F, 0x6F }; - - uint8_t ss = 0; + IOWR (ASYNC_8BIT_BUS_ADAPTER_0_BASE, addr, data); +} - // show negative with DP - if (score < 0) - { - ss |= 0x80; - score = -score; - } +uint8_t +ebb_read (unsigned int addr) +{ + return (uint8_t) IORD (ASYNC_8BIT_BUS_ADAPTER_0_BASE, addr); +} - if (score > 9) - score = 9; - ss |= lookup[score]; - pio_write (ss); -} int main (void) { int i; printf ("Working...\n"); - for (;;) { - for (i=-9;i<10;++i) - { - printf("%d\n",i); - show_score(i); - msleep(200); - } - } + srand (12833213); + for (;;) + { + printf ("W:"); + printf(" xx"); + printf(" xx"); + printf(" xx"); + for (i = 0; i < 32; ++i) + { + uint8_t v; + v = rand () & 0xff; + ebb_write (i, v); + printf (" %02x", v); + } + printf ("\n"); + msleep (1000); + printf ("R:"); + printf (" %02x", ebb_read (0)); + printf (" %02x", ebb_read (0)); + printf (" %02x", ebb_read (0)); + for (i = 0; i < 32; ++i) + { + printf (" %02x", ebb_read (i)); + } + printf ("\n"); + msleep (1000); + } } |