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-rw-r--r--sdram_ctrl.vhd73
1 files changed, 65 insertions, 8 deletions
diff --git a/sdram_ctrl.vhd b/sdram_ctrl.vhd
index d41b1b6..58064bd 100644
--- a/sdram_ctrl.vhd
+++ b/sdram_ctrl.vhd
@@ -36,7 +36,9 @@ entity sdram_ctrl is
sdram_ba : out std_logic_vector(1 downto 0);
sdram_dq : inout data_t;
- sdram_dqm : out dqm_t
+ sdram_dqm : out dqm_t;
+
+ debug : out std_logic_vector(7 downto 0)
);
end entity;
@@ -46,6 +48,18 @@ architecture rtl of sdram_ctrl is
signal clock : std_logic;
+
+ constant DEBUG_0 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#3F#,7));
+ constant DEBUG_1 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#06#,7));
+ constant DEBUG_2 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#5B#,7));
+ constant DEBUG_3 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#4F#,7));
+ constant DEBUG_4 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#66#,7));
+ constant DEBUG_5 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#6D#,7));
+ constant DEBUG_6 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#7D#,7));
+ constant DEBUG_7 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#07#,7));
+ constant DEBUG_8 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#7F#,7));
+ constant DEBUG_9 : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(16#6F#,7));
+
-- bits in the MEM_CMD register RAS_N CAS_N WE_N
constant MEM_CMD_NOP : std_logic_vector(2 downto 0 ):="111";
@@ -74,6 +88,11 @@ architecture rtl of sdram_ctrl is
signal i_next : uint3_t;
signal i_refs : uint3_t;
+ -- debuging
+ signal i_debug : std_logic_vector(6 downto 0);
+ signal m_debug : std_logic_vector(7 downto 0);
+ signal b_debug : std_logic_vector(7 downto 0);
+
-- init fsm
signal i_state :uint3_t;
@@ -193,10 +212,11 @@ begin
end if;
end process;
- request_pending_process: process(reset_n, clock, post_request, request_pending,ack_request) begin
+ request_pending_process: process(reset_n, clock, post_request, request_pending,ack_request,refresh_counter) begin
if l2b_al(reset_n) then
request_pending <= '0';
elsif rising_edge(clock) then
+ --request_pending <= post_request or (request_pending and not b2l_ah(refresh_counter = 0 ));
request_pending <= post_request or (request_pending and not ack_request);
end if;
end process;
@@ -218,9 +238,11 @@ begin
i_cmd <= MEM_CMD_NOP;
i_addr <= (others => '1');
i_count <= 0;
+ i_debug <= DEBUG_0;
elsif rising_edge(clock) then
if i_state = I_ST_RESET_WAIT then
+ i_debug <= DEBUG_1;
-- after reset wait until the refresh_counter ticks over for RAM to stabalize
i_cs_n <=MEM_CS_N_NONE;
i_cmd <= MEM_CMD_NOP;
@@ -229,6 +251,7 @@ begin
i_state <= I_ST_PRECHARGE;
end if;
elsif i_state = I_ST_PRECHARGE then
+ i_debug <= DEBUG_2;
-- precharge all banks, wait one clock, then go to refresh
i_cs_n <=MEM_CS_N_ALL;
i_cmd <=MEM_CMD_PRE;
@@ -236,6 +259,7 @@ begin
i_count <= 1;
i_next <= I_ST_REFRESH;
elsif i_state =I_ST_REFRESH then
+ i_debug <= DEBUG_3;
-- repeat 7 times { refresh, wait 5 counts }
i_cs_n <=MEM_CS_N_ALL;
i_cmd <=MEM_CMD_REF;
@@ -250,6 +274,7 @@ begin
i_next <= I_ST_REFRESH;
end if;
elsif i_state = I_ST_WAIT_COUNT then
+ i_debug <= DEBUG_4;
-- wait i_count ticks then goto state i_next
i_cs_n <=MEM_CS_N_ALL;
i_cmd <= MEM_CMD_NOP;
@@ -260,6 +285,7 @@ begin
end if;
elsif i_state=I_ST_SET_MODE then
+ i_debug <= DEBUG_5;
-- set mode, wait 3 ticks then goto done
i_cs_n <=MEM_CS_N_ALL;
i_cmd <= MEM_CMD_MRS;
@@ -274,8 +300,10 @@ begin
i_addr <= "0000000110000";
i_count <= 3;
i_next <= I_ST_DONE;
+ i_state <= I_ST_WAIT_COUNT;
elsif i_state=I_ST_DONE then
+ i_debug <= DEBUG_6;
i_state <= I_ST_DONE;
else
i_state <= I_ST_RESET_WAIT;
@@ -283,7 +311,7 @@ begin
end if;
end process;
- main_fsm: process (reset_n,clock,m_state,need_refresh,request_pending,request_addr,request_data,request_cs_n,request_rnw,request_dqm) begin
+ main_fsm: process (reset_n,clock,m_state,need_refresh,request_pending,request_addr,request_data,request_cs_n,request_rnw,request_dqm,i_debug) begin
if reset_n ='0' then
m_state <= M_ST_WAITING_INIT;
@@ -298,8 +326,12 @@ begin
ack_refresh <= '0';
ack_request <= '0';
mem_oe <= '0';
+ m_debug(6 downto 0) <=(others =>'0');
+ m_debug(7) <='1';
elsif rising_edge(clock) then
if m_state =M_ST_WAITING_INIT then
+ m_debug(6 downto 0) <= i_debug;
+ m_debug(7) <='1';
mem_addr <= i_addr;
mem_cmd <= i_cmd;
mem_cs_n <= i_cs_n;
@@ -308,6 +340,8 @@ begin
m_state <= M_ST_IDLE;
end if;
elsif m_state = M_ST_IDLE then
+ m_debug(6 downto 0) <= DEBUG_1;
+ m_debug(7) <='0';
mem_cmd <= MEM_CMD_NOP;
ack_refresh <='0';
@@ -342,6 +376,7 @@ begin
end if;
end if;
elsif m_state = M_ST_RAS then
+ m_debug(6 downto 0) <= DEBUG_2;
-- activate the relevant ROW, wait 3 clocks, then go and do the read or write
ack_request <='0';
@@ -362,6 +397,7 @@ begin
m_next <= M_ST_WRITE;
end if;
elsif m_state = M_ST_NOP_COUNT then
+ m_debug(6 downto 0) <= DEBUG_3;
-- send nops for m_count, then go to state m_next
mem_cmd <=MEM_CMD_NOP;
if m_count > 1 then
@@ -370,6 +406,7 @@ begin
m_state <= m_next;
end if;
elsif m_state = M_ST_READ then
+ m_debug(6 downto 0) <= DEBUG_4;
ack_request <='0';
mem_cmd <=MEM_CMD_READ;
@@ -377,8 +414,9 @@ begin
mem_addr(12 downto 9) <= (others => '0');
mem_addr(8 downto 0) <= active_addr(8 downto 0);
- m_next <= M_ST_ACTIVE;
+ m_state <= M_ST_ACTIVE;
elsif m_state = M_ST_WRITE then
+ m_debug(6 downto 0) <= DEBUG_5;
ack_request <='0';
mem_cmd<=MEM_CMD_WRIT;
@@ -391,6 +429,7 @@ begin
m_state <=M_ST_ACTIVE;
elsif m_state = M_ST_ACTIVE then
+ m_debug(6 downto 0) <= DEBUG_6;
-- turn off drivers (we might have come from a write)
mem_oe <= '0';
@@ -428,6 +467,7 @@ begin
end if;
elsif m_state = M_ST_WAIT_FOR_PRECHARGE then
+ m_debug(6 downto 0) <= DEBUG_7;
-- wait count then do a precharge
mem_cmd <= MEM_CMD_NOP;
if m_count > 1 then
@@ -436,12 +476,14 @@ begin
m_state<=M_ST_PRECHARGE;
end if;
elsif m_state = M_ST_PRECHARGE then
+ m_debug(6 downto 0) <= DEBUG_8;
-- do a precharge, wait two clocks, then goto m_next
mem_addr <= (others => '1');
mem_cmd <= MEM_CMD_PRE;
m_count <= 1;
m_state <= M_ST_NOP_COUNT;
elsif m_state=M_ST_REFRESH then
+ m_debug(6 downto 0) <= DEBUG_9;
-- do a refresh, wait six clocks, return to idle
mem_cmd <= MEM_CMD_REF;
@@ -453,6 +495,8 @@ begin
ack_refresh <= '1';
else
-- shouldn't be here - crash
+ m_debug(7) <='1';
+ m_debug(6 downto 0) <= DEBUG_9;
mem_cmd <=MEM_CMD_NOP;
mem_cs_n <= MEM_CS_N_NONE;
mem_oe <= '0';
@@ -503,32 +547,37 @@ begin
request_cs_n <= MEM_CS_N_NONE;
request_dqm <= "00";
b_state <= B_ST_WAIT_CS_N_LOW;
+ b_debug(6 downto 0) <= DEBUG_0;
+ b_debug(7) <='0';
+ bus_wait_n <= '0';
elsif rising_edge(clock) then
if b_state = B_ST_WAIT_CS_N_LOW then
+ b_debug(6 downto 0) <= DEBUG_1;
+ bus_wait_n <= '0';
if l2b_al(bus_cs_n) then
-- new request ship it to the main state machine
post_request <='1';
request_addr <= bus_addr;
request_rnw <= bus_rnw;
request_data <= bus_data_in;
- request_rnw <= '0';
-- send to first chip and all bytes
request_cs_n <= "0"; -- (others => '1');
request_dqm <= "00";
- bus_wait_n <= '0';
b_state <= B_ST_LODGE_REQUEST;
end if;
elsif b_state =B_ST_LODGE_REQUEST then
+ b_debug(6 downto 0) <= DEBUG_2;
post_request <='0';
b_state <= B_ST_WAIT_ACK;
elsif b_state =B_ST_WAIT_ACK then
+ b_debug(6 downto 0) <= DEBUG_3;
if not l2b_ah(request_pending) then
-- the logic has pushed the request to the ram
if l2b_al(request_rnw) then
- -- if it's a write we're all done
bus_wait_n <= '1';
+ -- if it's a write we're all done
b_state <= B_ST_WAIT_CS_N_HIGH;
else
-- if it's a read we have to wait for the data
@@ -536,20 +585,28 @@ begin
end if;
end if;
elsif b_state = B_ST_WAIT_DATA then
+ b_debug(6 downto 0) <= DEBUG_4;
if l2b_ah(r_data_valid(0)) then
bus_data_out <= mem_data_in;
- bus_wait_n <= '1';
+-- bus_data_out <= request_addr(15 downto 0);
+ bus_wait_n <= '1';
b_state <= B_ST_WAIT_CS_N_HIGH;
end if;
elsif b_state = B_ST_WAIT_CS_N_HIGH then
+ b_debug(6 downto 0) <= DEBUG_5;
+ b_debug(7) <='1';
if not l2b_al(bus_cs_n) then
+ bus_wait_n <= '0';
b_state <=B_ST_WAIT_CS_N_LOW;
end if;
else
b_state <=B_ST_WAIT_CS_N_LOW;
end if;
end if;
+
end process;
+-- debug <=b_debug;
+ debug <= m_debug;
end;
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-06 13:42:58 +0000