iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	now ignore init attributes on non-register wires in sat command	Clifford Wolf	2014-07-05	2	-0/+19
*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02	1	-0/+7
*	Fixed handling of mixed real/int ternary expressions	Clifford Wolf	2014-06-25	1	-3/+6
*	Little steps in realmath test bench	Clifford Wolf	2014-06-21	2	-2/+8
*	Added test case for AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17	1	-0/+12
*	Improved handling of relational op of real values	Clifford Wolf	2014-06-17	1	-4/+8
*	Little steps in realmath test bench	Clifford Wolf	2014-06-16	2	-0/+3
*	Removed long running tests from tests/simple/realexpr.v (replaced by tests/re...	Clifford Wolf	2014-06-15	1	-55/+0
*	Added tests/realmath to "make test"	Clifford Wolf	2014-06-15	4	-4/+5
*	Improved realmath test bench	Clifford Wolf	2014-06-15	2	-5/+13
*	improved realmath test bench	Clifford Wolf	2014-06-14	1	-1/+4
*	progress in realmath test bench	Clifford Wolf	2014-06-14	2	-4/+45
*	added first draft of real math testcase generator	Clifford Wolf	2014-06-14	1	-0/+52
*	Added support for math functions	Clifford Wolf	2014-06-14	1	-0/+57
*	Added realexpr.v test case	Clifford Wolf	2014-06-14	1	-0/+13
*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12	2	-2/+2
*	added tests for new verilog features	Clifford Wolf	2014-06-07	2	-6/+37
*	Added tests/simple/repwhile.v	Clifford Wolf	2014-06-06	1	-0/+20
*	Progress in Verific bindings	Clifford Wolf	2014-03-17	3	-2/+13
*	Progress in Verific bindings	Clifford Wolf	2014-03-14	1	-5/+9
*	Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh	Clifford Wolf	2014-03-11	1	-1/+1
*	Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)	Clifford Wolf	2014-03-11	1	-1/+1
*	Use private namespace in mem_simple_4x1_map	Clifford Wolf	2014-02-21	1	-4/+4
*	Added tests/techmap/mem_simple_4x1	Clifford Wolf	2014-02-21	7	-0/+214
*	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	Clifford Wolf	2014-02-19	2	-0/+170
*	Added frontend (-f) option to autotest.sh	Clifford Wolf	2014-02-15	1	-5/+8
*	Updated ABC and some related changes	Clifford Wolf	2014-02-13	1	-2/+1
*	Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)	Clifford Wolf	2014-02-12	1	-1/+2
*	Added test cases for expose -evert-dff	Clifford Wolf	2014-02-08	2	-0/+48
*	Added splice command	Clifford Wolf	2014-02-07	2	-0/+28
*	Added counters sat test case	Clifford Wolf	2014-02-06	2	-0/+45
*	Removed old unused files from tests/	Clifford Wolf	2014-02-05	14	-2602/+0
*	Added test cases for sat command	Clifford Wolf	2014-02-04	6	-0/+126
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+39
*	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	Clifford Wolf	2014-02-03	1	-50/+10
*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30	1	-0/+24
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-0/+17
*	Added autotest.sh -p option	Clifford Wolf	2014-01-02	1	-3/+8
*	Use "abc -dff" in "make test"	Clifford Wolf	2013-12-31	1	-3/+2
*	Fixed commented out techmap call in tests/tools/autotest.sh	Clifford Wolf	2013-12-31	1	-1/+1
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	1	-0/+11
*	Added multiplier test case from eda playground	Clifford Wolf	2013-12-18	1	-0/+132
*	Added elsif preproc support	Clifford Wolf	2013-12-18	1	-1/+229
*	Added support for macro arguments	Clifford Wolf	2013-12-18	1	-0/+9
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	1	-0/+27
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-1/+1
*	Fix in sincos testbench gen	Clifford Wolf	2013-12-04	1	-1/+1
*	Added sincos test case	Clifford Wolf	2013-12-04	1	-0/+124
*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24	2	-2/+2
*	Removed now obsolete test cases	Clifford Wolf	2013-11-24	3	-72/+0