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* hierarchy - proc reorderMiodrag Milanovic2019-10-189-14/+18
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* Check latches type one by oneMiodrag Milanovic2019-10-042-40/+25
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* Removed top module where not neededMiodrag Milanovic2019-10-044-37/+4
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* Test muxes synth one by oneMiodrag Milanovic2019-10-042-38/+39
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* Cleaned verilog code from not used definesMiodrag Milanovic2019-10-041-6/+0
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* Check for MULT18X18D, since that is working nowMiodrag Milanovic2019-10-042-14/+11
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* Check flops one by oneMiodrag Milanovic2019-10-044-71/+50
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* Removed alu and div_mod tests as agreedMiodrag Milanovic2019-10-044-57/+0
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* equiv_opt with -assertEddie Hung2019-09-301-3/+1
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* Update resource count for alu.ysEddie Hung2019-09-301-3/+3
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* Move $x to end as per 7f0eec8Eddie Hung2019-09-301-1/+1
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* Update fsm.ys resource countEddie Hung2019-09-301-3/+3
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* Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys ↵Eddie Hung2019-09-3036-0/+800
|\ | | | | | | into eddie/pr1352
| * Add comment to dpram test about related issue.SergeyDegtyar2019-09-181-0/+1
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| * adffs test update (equiv_opt -multiclock). div_mod test fixSergeyDegtyar2019-09-173-17/+12
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| * Remove stat command form shifter.ys testSergeyDegtyar2019-09-041-1/+1
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| * Fix ecp5 testsSergeyDegtyar2019-09-0411-2421/+26
| | | | | | | | | | - remove *_synth.v files and generation in scripts; - change synth_ice40 to synth_ecp5;
| * Uncomment sat command in memory.ys test.SergeyDegtyar2019-09-031-2/+1
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| * Add tests for ECP5 architectureSergeyDegtyar2019-09-0339-0/+3200
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* | Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-306-0/+152
|\ \ | | | | | | rpc: new frontend
| * | rpc: new frontend.whitequark2019-09-306-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.
* | | Add latch test modified from #1363Eddie Hung2019-09-302-0/+73
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* | | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2910-11/+325
|\ \ \ | | | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| * \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-231-0/+62
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| * | | | Add more complicated macc testcaseEddie Hung2019-09-192-5/+39
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| * | | | Add mac.sh and macc_tb.v for testingEddie Hung2019-09-192-0/+99
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| * | | | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-191-0/+41
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| * | | | | Format macc.vEddie Hung2019-09-191-8/+8
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| * | | | | Remove statEddie Hung2019-09-181-1/+0
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| * | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-181-2/+26
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| * | | | | | Add .gitignoreEddie Hung2019-09-181-0/+1
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| * | | | | | Refine macc testcaseEddie Hung2019-09-182-9/+17
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| * | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-123-1/+63
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| * | | | | | | Add AREG=2 BREG=2 testEddie Hung2019-09-111-2/+6
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-111-0/+71
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| * | | | | | | | Update test with a/b resetEddie Hung2019-09-111-2/+4
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| * | | | | | | | Extend test for RSTP and RSTMEddie Hung2019-09-112-3/+50
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| * | | | | | | | Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-111-1/+18
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| * \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-111-6/+6
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| * \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-112-7/+105
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| * | | | | | | | | | | Add SIMD testEddie Hung2019-09-091-0/+25
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| * | | | | | | | | | | Update macc testEddie Hung2019-09-062-42/+42
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| * | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-052-21/+63
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| * \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-051-1/+3
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| * \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dspEddie Hung2019-09-041-0/+8
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| * \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-045-9/+39
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| * | | | | | | | | | | | | | | Add macc test, with equiv_opt not currently passingEddie Hung2019-08-302-0/+54
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| * | | | | | | | | | | | | | | Update test for ffMEddie Hung2019-08-301-2/+2
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| * | | | | | | | | | | | | | | Add mul_unsigned testEddie Hung2019-08-302-0/+41
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* | | | | | | | | | | | | | | | Fix _TECHMAP_REMOVEINIT_ handling.Marcin Kościelnicki2019-09-271-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, this wire was handled in the code that populated the "do or do not" techmap cache, resulting in init value removal being performed only for the first use of a given template. Fixes the problem identified in #1396.
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