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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 10:31:51 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 10:31:51 +0200 |
| commit | 7785f23719cdbcae6816415cf2dc124aba312c66 (patch) | |
| tree | 2f0f8216e078b62228b694e9fd291e55f400c7d3 /tests | |
| parent | 3358b2f18597c59ee3cac5f123f954ca79e0baad (diff) | |
| download | yosys-7785f23719cdbcae6816415cf2dc124aba312c66.tar.gz yosys-7785f23719cdbcae6816415cf2dc124aba312c66.tar.bz2 yosys-7785f23719cdbcae6816415cf2dc124aba312c66.zip | |
Check latches type one by one
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ecp5/latches.v | 34 | ||||
| -rw-r--r-- | tests/ecp5/latches.ys | 31 |
2 files changed, 25 insertions, 40 deletions
diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v index 9dc43e4c2..adb5d5319 100644 --- a/tests/ecp5/latches.v +++ b/tests/ecp5/latches.v @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys index b9d8faf87..f32998232 100644 --- a/tests/ecp5/latches.ys +++ b/tests/ecp5/latches.ys @@ -1,16 +1,35 @@ + read_verilog latches.v design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock -flatten +hierarchy -top latchp +# Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 + +select -assert-none t:LUT4 %% t:* %D + design -load read +proc +hierarchy -top latchn +# Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 -cd top -select -assert-count 4 t:LUT4 +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 + +select -assert-none t:LUT4 %% t:* %D + + +design -load read +proc +hierarchy -top latchsr +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ecp5 +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:LUT4 select -assert-count 1 t:PFUMX + select -assert-none t:LUT4 t:PFUMX %% t:* %D |